diff options
Diffstat (limited to 'firmware/export/dm320.h')
-rw-r--r-- | firmware/export/dm320.h | 79 |
1 files changed, 40 insertions, 39 deletions
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index 5e164cff57..f072e8975f 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h | |||
@@ -27,6 +27,7 @@ | |||
27 | #define FRAME ((short *) (0x4470000)) | 27 | #define FRAME ((short *) (0x4470000)) |
28 | 28 | ||
29 | #define PHY_IO_BASE 0x00030000 | 29 | #define PHY_IO_BASE 0x00030000 |
30 | #define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr))) | ||
30 | 31 | ||
31 | /* Timer 0-3 */ | 32 | /* Timer 0-3 */ |
32 | #define IO_TIMER0_TMMD 0x0000 | 33 | #define IO_TIMER0_TMMD 0x0000 |
@@ -58,20 +59,20 @@ | |||
58 | #define IO_TIMER3_TMCNT 0x018A | 59 | #define IO_TIMER3_TMCNT 0x018A |
59 | 60 | ||
60 | /* Serial 0/1 */ | 61 | /* Serial 0/1 */ |
61 | #define IO_SERIAL0_TX_DATA 0x0200 | 62 | #define IO_SERIAL0_TX_DATA DM320_REG(0x0200) |
62 | #define IO_SERIAL0_RX_DATA 0x0202 | 63 | #define IO_SERIAL0_RX_DATA DM320_REG(0x0202) |
63 | #define IO_SERIAL0_TX_ENABLE 0x0204 | 64 | #define IO_SERIAL0_TX_ENABLE DM320_REG(0x0204) |
64 | #define IO_SERIAL0_MODE 0x0206 | 65 | #define IO_SERIAL0_MODE DM320_REG(0x0206) |
65 | #define IO_SERIAL0_DMA_TRIGGER 0x0208 | 66 | #define IO_SERIAL0_DMA_TRIGGER DM320_REG(0x0208) |
66 | #define IO_SERIAL0_DMA_MODE 0x020A | 67 | #define IO_SERIAL0_DMA_MODE DM320_REG(0x020A) |
67 | #define IO_SERIAL0_DMA_SDRAM_LOW 0x020C | 68 | #define IO_SERIAL0_DMA_SDRAM_LOW DM320_REG(0x020C) |
68 | #define IO_SERIAL0_DMA_SDRAM_HI 0x020E | 69 | #define IO_SERIAL0_DMA_SDRAM_HI DM320_REG(0x020E) |
69 | #define IO_SERIAL0_DMA_STATUS 0x0210 | 70 | #define IO_SERIAL0_DMA_STATUS DM320_REG(0x0210) |
70 | 71 | ||
71 | #define IO_SERIAL1_TX_DATA 0x0280 | 72 | #define IO_SERIAL1_TX_DATA DM320_REG(0x0280) |
72 | #define IO_SERIAL1_RX_DATA 0x0282 | 73 | #define IO_SERIAL1_RX_DATA DM320_REG(0x0282) |
73 | #define IO_SERIAL1_TX_ENABLE 0x0284 | 74 | #define IO_SERIAL1_TX_ENABLE DM320_REG(0x0284) |
74 | #define IO_SERIAL1_MODE 0x0286 | 75 | #define IO_SERIAL1_MODE DM320_REG(0x0286) |
75 | 76 | ||
76 | /* UART 0/1 */ | 77 | /* UART 0/1 */ |
77 | #define IO_UART0_DTRR 0x0300 | 78 | #define IO_UART0_DTRR 0x0300 |
@@ -383,31 +384,31 @@ | |||
383 | #define IO_VID_ENC_ATR0 0x0854 | 384 | #define IO_VID_ENC_ATR0 0x0854 |
384 | 385 | ||
385 | /* Clock Controller */ | 386 | /* Clock Controller */ |
386 | #define IO_CLK_PLLA 0x0880 | 387 | #define IO_CLK_PLLA DM320_REG(0x0880) |
387 | #define IO_CLK_PLLB 0x0882 | 388 | #define IO_CLK_PLLB DM320_REG(0x0882) |
388 | #define IO_CLK_SEL0 0x0884 | 389 | #define IO_CLK_SEL0 DM320_REG(0x0884) |
389 | #define IO_CLK_SEL1 0x0886 | 390 | #define IO_CLK_SEL1 DM320_REG(0x0886) |
390 | #define IO_CLK_SEL2 0x0888 | 391 | #define IO_CLK_SEL2 DM320_REG(0x0888) |
391 | #define IO_CLK_DIV0 0x088A | 392 | #define IO_CLK_DIV0 DM320_REG(0x088A) |
392 | #define IO_CLK_DIV1 0x088C | 393 | #define IO_CLK_DIV1 DM320_REG(0x088C) |
393 | #define IO_CLK_DIV2 0x088E | 394 | #define IO_CLK_DIV2 DM320_REG(0x088E) |
394 | #define IO_CLK_DIV3 0x0890 | 395 | #define IO_CLK_DIV3 DM320_REG(0x0890) |
395 | #define IO_CLK_DIV4 0x0892 | 396 | #define IO_CLK_DIV4 DM320_REG(0x0892) |
396 | #define IO_CLK_BYP 0x0894 | 397 | #define IO_CLK_BYP DM320_REG(0x0894) |
397 | #define IO_CLK_INV 0x0896 | 398 | #define IO_CLK_INV DM320_REG(0x0896) |
398 | #define IO_CLK_MOD0 0x0898 | 399 | #define IO_CLK_MOD0 DM320_REG(0x0898) |
399 | #define IO_CLK_MOD1 0x089A | 400 | #define IO_CLK_MOD1 DM320_REG(0x089A) |
400 | #define IO_CLK_MOD2 0x089C | 401 | #define IO_CLK_MOD2 DM320_REG(0x089C) |
401 | #define IO_CLK_LPCTL0 0x089E | 402 | #define IO_CLK_LPCTL0 DM320_REG(0x089E) |
402 | #define IO_CLK_LPCTL1 0x08A0 | 403 | #define IO_CLK_LPCTL1 DM320_REG(0x08A0) |
403 | #define IO_CLK_OSEL 0x08A2 | 404 | #define IO_CLK_OSEL DM320_REG(0x08A2) |
404 | #define IO_CLK_00DIV 0x08A4 | 405 | #define IO_CLK_00DIV DM320_REG(0x08A4) |
405 | #define IO_CLK_O1DIV 0x08A6 | 406 | #define IO_CLK_O1DIV DM320_REG(0x08A6) |
406 | #define IO_CLK_02DIV 0x08A8 | 407 | #define IO_CLK_02DIV DM320_REG(0x08A8) |
407 | #define IO_CLK_PWM0C 0x08AA | 408 | #define IO_CLK_PWM0C DM320_REG(0x08AA) |
408 | #define IO_CLK_PWM0H 0x08AC | 409 | #define IO_CLK_PWM0H DM320_REG(0x08AC) |
409 | #define IO_CLK_PWM1C 0x08AE | 410 | #define IO_CLK_PWM1C DM320_REG(0x08AE) |
410 | #define IO_CLK_PWM1H 0x08B0 | 411 | #define IO_CLK_PWM1H DM320_REG(0x08B0) |
411 | 412 | ||
412 | /* Bus Controller */ | 413 | /* Bus Controller */ |
413 | #define IO_BUSC_ECR 0x0900 | 414 | #define IO_BUSC_ECR 0x0900 |