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author | Michael Sevakis <jethead71@rockbox.org> | 2010-06-24 08:40:05 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2010-06-24 08:40:05 +0000 |
commit | c2851389b9b4c145a9bc0fbe245f3ff9546375df (patch) | |
tree | fc4dad674d03c85ee57e1dd657f54b6ea05e633b | |
parent | 1ae6ee263b9ef6f356760002f3f02197927a963b (diff) | |
download | rockbox-c2851389b9b4c145a9bc0fbe245f3ff9546375df.tar.gz rockbox-c2851389b9b4c145a9bc0fbe245f3ff9546375df.zip |
Gigabeat S: Use statically initialized channel descriptors. Also, there's no need for them to be in non-cached memory since they're only used on the AP side.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27103 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/imx31/ata-imx31.c | 48 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | 42 |
2 files changed, 51 insertions, 39 deletions
diff --git a/firmware/target/arm/imx31/ata-imx31.c b/firmware/target/arm/imx31/ata-imx31.c index 4c6bebd168..6ba49cada0 100644 --- a/firmware/target/arm/imx31/ata-imx31.c +++ b/firmware/target/arm/imx31/ata-imx31.c | |||
@@ -251,8 +251,33 @@ static struct wakeup ata_dma_wakeup; | |||
251 | /* Array of buffer descriptors for large transfers and alignnment */ | 251 | /* Array of buffer descriptors for large transfers and alignnment */ |
252 | static struct buffer_descriptor ata_bda[ATA_BD_COUNT] NOCACHEBSS_ATTR; | 252 | static struct buffer_descriptor ata_bda[ATA_BD_COUNT] NOCACHEBSS_ATTR; |
253 | /* ATA channel descriptors */ | 253 | /* ATA channel descriptors */ |
254 | static struct channel_descriptor ata_cd_rd NOCACHEBSS_ATTR; /* read channel */ | 254 | /* Read/write channels share buffer descriptors and callbacks */ |
255 | static struct channel_descriptor ata_cd_wr NOCACHEBSS_ATTR; /* write channel */ | 255 | static void ata_dma_callback(void); |
256 | |||
257 | static struct channel_descriptor ata_cd_rd = /* read channel */ | ||
258 | { | ||
259 | .bd_count = ATA_BD_COUNT, | ||
260 | .callback = ata_dma_callback, | ||
261 | .shp_addr = SDMA_PER_ADDR_ATA_RX, | ||
262 | .wml = SDMA_ATA_WML, | ||
263 | .per_type = SDMA_PER_ATA, | ||
264 | .tran_type = SDMA_TRAN_PER_2_EMI, | ||
265 | .event_id1 = SDMA_REQ_ATA_TXFER_END, | ||
266 | .event_id2 = SDMA_REQ_ATA_RX, | ||
267 | }; | ||
268 | |||
269 | static struct channel_descriptor ata_cd_wr = /* write channel */ | ||
270 | { | ||
271 | .bd_count = ATA_BD_COUNT, | ||
272 | .callback = ata_dma_callback, | ||
273 | .shp_addr = SDMA_PER_ADDR_ATA_TX, | ||
274 | .wml = SDMA_ATA_WML, | ||
275 | .per_type = SDMA_PER_ATA, | ||
276 | .tran_type = SDMA_TRAN_EMI_2_PER, | ||
277 | .event_id1 = SDMA_REQ_ATA_TXFER_END, | ||
278 | .event_id2 = SDMA_REQ_ATA_TX, | ||
279 | }; | ||
280 | |||
256 | /* DMA channel to be started for transfer */ | 281 | /* DMA channel to be started for transfer */ |
257 | static unsigned int current_channel = 0; | 282 | static unsigned int current_channel = 0; |
258 | 283 | ||
@@ -654,25 +679,6 @@ void ata_device_init(void) | |||
654 | /* Called for first time at startup */ | 679 | /* Called for first time at startup */ |
655 | wakeup_init(&ata_dma_wakeup); | 680 | wakeup_init(&ata_dma_wakeup); |
656 | 681 | ||
657 | /* Read/write channels share buffer descriptors */ | ||
658 | ata_cd_rd.bd_count = ATA_BD_COUNT; | ||
659 | ata_cd_rd.callback = ata_dma_callback; | ||
660 | ata_cd_rd.shp_addr = SDMA_PER_ADDR_ATA_RX; | ||
661 | ata_cd_rd.wml = SDMA_ATA_WML; | ||
662 | ata_cd_rd.per_type = SDMA_PER_ATA; | ||
663 | ata_cd_rd.tran_type = SDMA_TRAN_PER_2_EMI; | ||
664 | ata_cd_rd.event_id1 = SDMA_REQ_ATA_TXFER_END; | ||
665 | ata_cd_rd.event_id2 = SDMA_REQ_ATA_RX; | ||
666 | |||
667 | ata_cd_wr.bd_count = ATA_BD_COUNT; | ||
668 | ata_cd_wr.callback = ata_dma_callback; | ||
669 | ata_cd_wr.shp_addr = SDMA_PER_ADDR_ATA_TX; | ||
670 | ata_cd_wr.wml = SDMA_ATA_WML; | ||
671 | ata_cd_wr.per_type = SDMA_PER_ATA; | ||
672 | ata_cd_wr.tran_type = SDMA_TRAN_EMI_2_PER; | ||
673 | ata_cd_wr.event_id1 = SDMA_REQ_ATA_TXFER_END; | ||
674 | ata_cd_wr.event_id2 = SDMA_REQ_ATA_TX; | ||
675 | |||
676 | if (!sdma_channel_init(ATA_DMA_CH_NUM_RD, &ata_cd_rd, ata_bda) || | 682 | if (!sdma_channel_init(ATA_DMA_CH_NUM_RD, &ata_cd_rd, ata_bda) || |
677 | !sdma_channel_init(ATA_DMA_CH_NUM_WR, &ata_cd_wr, ata_bda)) | 683 | !sdma_channel_init(ATA_DMA_CH_NUM_WR, &ata_cd_wr, ata_bda)) |
678 | { | 684 | { |
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c index f74b167400..cfd83f0794 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | |||
@@ -33,7 +33,18 @@ | |||
33 | #define DMA_REC_CH_PRIORITY 6 | 33 | #define DMA_REC_CH_PRIORITY 6 |
34 | 34 | ||
35 | static struct buffer_descriptor dma_play_bd NOCACHEBSS_ATTR; | 35 | static struct buffer_descriptor dma_play_bd NOCACHEBSS_ATTR; |
36 | static struct channel_descriptor dma_play_cd NOCACHEBSS_ATTR; | 36 | |
37 | static void play_dma_callback(void); | ||
38 | static struct channel_descriptor dma_play_cd = | ||
39 | { | ||
40 | .bd_count = 1, | ||
41 | .callback = play_dma_callback, | ||
42 | .shp_addr = SDMA_PER_ADDR_SSI2_TX1, | ||
43 | .wml = SDMA_SSI_TXFIFO_WML*2, | ||
44 | .per_type = SDMA_PER_SSI_SHP, /* SSI2 shared with SDMA core */ | ||
45 | .tran_type = SDMA_TRAN_EMI_2_PER, | ||
46 | .event_id1 = SDMA_REQ_SSI2_TX1, | ||
47 | }; | ||
37 | 48 | ||
38 | /* The pcm locking relies on the fact the interrupt handlers run to completion | 49 | /* The pcm locking relies on the fact the interrupt handlers run to completion |
39 | * before lower-priority modes proceed. We don't have to touch hardware | 50 | * before lower-priority modes proceed. We don't have to touch hardware |
@@ -123,14 +134,6 @@ void pcm_dma_apply_settings(void) | |||
123 | void pcm_play_dma_init(void) | 134 | void pcm_play_dma_init(void) |
124 | { | 135 | { |
125 | /* Init channel information */ | 136 | /* Init channel information */ |
126 | dma_play_cd.bd_count = 1; | ||
127 | dma_play_cd.callback = play_dma_callback; | ||
128 | dma_play_cd.shp_addr = SDMA_PER_ADDR_SSI2_TX1; | ||
129 | dma_play_cd.wml = SDMA_SSI_TXFIFO_WML*2; | ||
130 | dma_play_cd.per_type = SDMA_PER_SSI_SHP; /* SSI2 shared with SDMA core */ | ||
131 | dma_play_cd.tran_type = SDMA_TRAN_EMI_2_PER; | ||
132 | dma_play_cd.event_id1 = SDMA_REQ_SSI2_TX1; | ||
133 | |||
134 | sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); | 137 | sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); |
135 | sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); | 138 | sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); |
136 | 139 | ||
@@ -372,7 +375,18 @@ void * pcm_dma_addr(void *addr) | |||
372 | 375 | ||
373 | #ifdef HAVE_RECORDING | 376 | #ifdef HAVE_RECORDING |
374 | static struct buffer_descriptor dma_rec_bd NOCACHEBSS_ATTR; | 377 | static struct buffer_descriptor dma_rec_bd NOCACHEBSS_ATTR; |
375 | static struct channel_descriptor dma_rec_cd NOCACHEBSS_ATTR; | 378 | |
379 | static void rec_dma_callback(void); | ||
380 | static struct channel_descriptor dma_rec_cd = | ||
381 | { | ||
382 | .bd_count = 1, | ||
383 | .callback = rec_dma_callback, | ||
384 | .shp_addr = SDMA_PER_ADDR_SSI1_RX1, | ||
385 | .wml = SDMA_SSI_RXFIFO_WML*2, | ||
386 | .per_type = SDMA_PER_SSI, | ||
387 | .tran_type = SDMA_TRAN_PER_2_EMI, | ||
388 | .event_id1 = SDMA_REQ_SSI1_RX1, | ||
389 | }; | ||
376 | 390 | ||
377 | static struct dma_data dma_rec_data = | 391 | static struct dma_data dma_rec_data = |
378 | { | 392 | { |
@@ -495,14 +509,6 @@ void pcm_rec_dma_init(void) | |||
495 | pcm_rec_dma_stop(); | 509 | pcm_rec_dma_stop(); |
496 | 510 | ||
497 | /* Init channel information */ | 511 | /* Init channel information */ |
498 | dma_rec_cd.bd_count = 1; | ||
499 | dma_rec_cd.callback = rec_dma_callback; | ||
500 | dma_rec_cd.shp_addr = SDMA_PER_ADDR_SSI1_RX1; | ||
501 | dma_rec_cd.wml = SDMA_SSI_RXFIFO_WML*2; | ||
502 | dma_rec_cd.per_type = SDMA_PER_SSI; | ||
503 | dma_rec_cd.tran_type = SDMA_TRAN_PER_2_EMI; | ||
504 | dma_rec_cd.event_id1 = SDMA_REQ_SSI1_RX1; | ||
505 | |||
506 | sdma_channel_init(DMA_REC_CH_NUM, &dma_rec_cd, &dma_rec_bd); | 512 | sdma_channel_init(DMA_REC_CH_NUM, &dma_rec_cd, &dma_rec_bd); |
507 | sdma_channel_set_priority(DMA_REC_CH_NUM, DMA_REC_CH_PRIORITY); | 513 | sdma_channel_set_priority(DMA_REC_CH_NUM, DMA_REC_CH_PRIORITY); |
508 | } | 514 | } |