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Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c42
1 files changed, 24 insertions, 18 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
index f74b167400..cfd83f0794 100644
--- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
@@ -33,7 +33,18 @@
33#define DMA_REC_CH_PRIORITY 6 33#define DMA_REC_CH_PRIORITY 6
34 34
35static struct buffer_descriptor dma_play_bd NOCACHEBSS_ATTR; 35static struct buffer_descriptor dma_play_bd NOCACHEBSS_ATTR;
36static struct channel_descriptor dma_play_cd NOCACHEBSS_ATTR; 36
37static void play_dma_callback(void);
38static struct channel_descriptor dma_play_cd =
39{
40 .bd_count = 1,
41 .callback = play_dma_callback,
42 .shp_addr = SDMA_PER_ADDR_SSI2_TX1,
43 .wml = SDMA_SSI_TXFIFO_WML*2,
44 .per_type = SDMA_PER_SSI_SHP, /* SSI2 shared with SDMA core */
45 .tran_type = SDMA_TRAN_EMI_2_PER,
46 .event_id1 = SDMA_REQ_SSI2_TX1,
47};
37 48
38/* The pcm locking relies on the fact the interrupt handlers run to completion 49/* The pcm locking relies on the fact the interrupt handlers run to completion
39 * before lower-priority modes proceed. We don't have to touch hardware 50 * before lower-priority modes proceed. We don't have to touch hardware
@@ -123,14 +134,6 @@ void pcm_dma_apply_settings(void)
123void pcm_play_dma_init(void) 134void pcm_play_dma_init(void)
124{ 135{
125 /* Init channel information */ 136 /* Init channel information */
126 dma_play_cd.bd_count = 1;
127 dma_play_cd.callback = play_dma_callback;
128 dma_play_cd.shp_addr = SDMA_PER_ADDR_SSI2_TX1;
129 dma_play_cd.wml = SDMA_SSI_TXFIFO_WML*2;
130 dma_play_cd.per_type = SDMA_PER_SSI_SHP; /* SSI2 shared with SDMA core */
131 dma_play_cd.tran_type = SDMA_TRAN_EMI_2_PER;
132 dma_play_cd.event_id1 = SDMA_REQ_SSI2_TX1;
133
134 sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); 137 sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd);
135 sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); 138 sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY);
136 139
@@ -372,7 +375,18 @@ void * pcm_dma_addr(void *addr)
372 375
373#ifdef HAVE_RECORDING 376#ifdef HAVE_RECORDING
374static struct buffer_descriptor dma_rec_bd NOCACHEBSS_ATTR; 377static struct buffer_descriptor dma_rec_bd NOCACHEBSS_ATTR;
375static struct channel_descriptor dma_rec_cd NOCACHEBSS_ATTR; 378
379static void rec_dma_callback(void);
380static struct channel_descriptor dma_rec_cd =
381{
382 .bd_count = 1,
383 .callback = rec_dma_callback,
384 .shp_addr = SDMA_PER_ADDR_SSI1_RX1,
385 .wml = SDMA_SSI_RXFIFO_WML*2,
386 .per_type = SDMA_PER_SSI,
387 .tran_type = SDMA_TRAN_PER_2_EMI,
388 .event_id1 = SDMA_REQ_SSI1_RX1,
389};
376 390
377static struct dma_data dma_rec_data = 391static struct dma_data dma_rec_data =
378{ 392{
@@ -495,14 +509,6 @@ void pcm_rec_dma_init(void)
495 pcm_rec_dma_stop(); 509 pcm_rec_dma_stop();
496 510
497 /* Init channel information */ 511 /* Init channel information */
498 dma_rec_cd.bd_count = 1;
499 dma_rec_cd.callback = rec_dma_callback;
500 dma_rec_cd.shp_addr = SDMA_PER_ADDR_SSI1_RX1;
501 dma_rec_cd.wml = SDMA_SSI_RXFIFO_WML*2;
502 dma_rec_cd.per_type = SDMA_PER_SSI;
503 dma_rec_cd.tran_type = SDMA_TRAN_PER_2_EMI;
504 dma_rec_cd.event_id1 = SDMA_REQ_SSI1_RX1;
505
506 sdma_channel_init(DMA_REC_CH_NUM, &dma_rec_cd, &dma_rec_bd); 512 sdma_channel_init(DMA_REC_CH_NUM, &dma_rec_cd, &dma_rec_bd);
507 sdma_channel_set_priority(DMA_REC_CH_NUM, DMA_REC_CH_PRIORITY); 513 sdma_channel_set_priority(DMA_REC_CH_NUM, DMA_REC_CH_PRIORITY);
508} 514}