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| author | Aidan MacDonald <amachronic@protonmail.com> | 2021-04-07 23:14:35 +0100 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2021-04-09 10:53:36 +0000 |
| commit | c0a823e2ab4fb9ceabdd28f0533354b01adfd395 (patch) | |
| tree | 02220a1c65f512c905cc971b649caa52e5bba546 | |
| parent | 54b8e9131c8775777dfb3c76f308a97c49c55fd9 (diff) | |
| download | rockbox-c0a823e2ab4fb9ceabdd28f0533354b01adfd395.tar.gz rockbox-c0a823e2ab4fb9ceabdd28f0533354b01adfd395.zip | |
x1000: Trim unused cache functions from the SPL build
Change-Id: Ib645d8ff10cfc672de8ac2debaa17d7dd50dfafb
| -rw-r--r-- | firmware/target/mips/ingenic_x1000/system-target.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/system-target.h b/firmware/target/mips/ingenic_x1000/system-target.h index a2f0a6ff70..050afcca9e 100644 --- a/firmware/target/mips/ingenic_x1000/system-target.h +++ b/firmware/target/mips/ingenic_x1000/system-target.h | |||
| @@ -28,6 +28,15 @@ | |||
| 28 | #define CACHEALIGN_BITS 5 | 28 | #define CACHEALIGN_BITS 5 |
| 29 | #define CACHE_SIZE (16*1024) | 29 | #define CACHE_SIZE (16*1024) |
| 30 | 30 | ||
| 31 | #ifdef BOOTLOADER_SPL | ||
| 32 | /* This saves ~200 bytes in the SPL by allowing -ffunction-sections to split | ||
| 33 | * up the cache management functions, most of which aren't called by the SPL. | ||
| 34 | * If they are placed in .icode, then they all end up in one section and the | ||
| 35 | * linker can't discard the unused functions. | ||
| 36 | */ | ||
| 37 | # define MIPS_CACHEFUNC_ATTR | ||
| 38 | #endif | ||
| 39 | |||
| 31 | #include "mmu-mips.h" | 40 | #include "mmu-mips.h" |
| 32 | #include "mipsregs.h" | 41 | #include "mipsregs.h" |
| 33 | #include "mipsr2-endian.h" | 42 | #include "mipsr2-endian.h" |