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author | Bertrik Sikken <bertrik@sikken.nl> | 2010-08-18 21:42:03 +0000 |
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committer | Bertrik Sikken <bertrik@sikken.nl> | 2010-08-18 21:42:03 +0000 |
commit | b73d15e9c6175ac48b2280b089a40f0554d15d6f (patch) | |
tree | d12eacb864e4335104ae8dc1270f4760653e3042 | |
parent | 2e572e4da09bbdc1a218b5c1113ec07983f5cd99 (diff) | |
download | rockbox-b73d15e9c6175ac48b2280b089a40f0554d15d6f.tar.gz rockbox-b73d15e9c6175ac48b2280b089a40f0554d15d6f.zip |
Sansa AMSv2: enable PLLB and use it to generate a more accurate PCM frequency (playback rate error improves from 1.1% to 0.04%) - FS #10906 by me.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27845 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 1689c59448..7c388ad6c9 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -73,7 +73,7 @@ | |||
73 | #define AS3525_PLLA_FREQ 240000000 | 73 | #define AS3525_PLLA_FREQ 240000000 |
74 | #define AS3525_PLLA_SETTING 0x113B | 74 | #define AS3525_PLLA_SETTING 0x113B |
75 | 75 | ||
76 | #define AS3525_PLLB_FREQ 192000000 | 76 | #define AS3525_PLLB_FREQ 192000000 /* allows 44.1kHz with 0.04% error*/ |
77 | #define AS3525_PLLB_SETTING 0x155F | 77 | #define AS3525_PLLB_SETTING 0x155F |
78 | 78 | ||
79 | #define AS3525_FCLK_PREDIV 0 | 79 | #define AS3525_FCLK_PREDIV 0 |
@@ -146,7 +146,14 @@ | |||
146 | #endif /* CONFIG_CPU == AS3525v2 */ | 146 | #endif /* CONFIG_CPU == AS3525v2 */ |
147 | 147 | ||
148 | /* MCLK */ | 148 | /* MCLK */ |
149 | #if CONFIG_CPU == AS3525v2 | ||
150 | /* on AMSv2 we can enable PLLB for MCLK to increase PCM sample rate accuracy | ||
151 | with no significant impact on battery life */ | ||
152 | #define AS3525_MCLK_SEL AS3525_CLK_PLLB | ||
153 | #else | ||
149 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA | 154 | #define AS3525_MCLK_SEL AS3525_CLK_PLLA |
155 | #endif /* CONFIG_CPU == AS3525v2 */ | ||
156 | |||
150 | #if (AS3525_MCLK_SEL==AS3525_CLK_PLLA) | 157 | #if (AS3525_MCLK_SEL==AS3525_CLK_PLLA) |
151 | #define AS3525_MCLK_FREQ AS3525_PLLA_FREQ | 158 | #define AS3525_MCLK_FREQ AS3525_PLLA_FREQ |
152 | #elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB) | 159 | #elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB) |