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authorRob Purchase <shotofadds@rockbox.org>2010-05-31 21:00:25 +0000
committerRob Purchase <shotofadds@rockbox.org>2010-05-31 21:00:25 +0000
commita6c1b54d4651920efdafd52a402fadf0f80b373c (patch)
tree115f197e177e62ae472640131eee0f8699f85136
parent64adb32cbfc805c01084ff935049998846c70dcd (diff)
downloadrockbox-a6c1b54d4651920efdafd52a402fadf0f80b373c.tar.gz
rockbox-a6c1b54d4651920efdafd52a402fadf0f80b373c.zip
Enable IRAM on TCC7801 (Cowon D2) for a 6-12% speedup in codecs that use it, and a small increase in battery life.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26436 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--apps/plugins/plugin.lds7
-rw-r--r--firmware/export/config.h1
-rw-r--r--firmware/target/arm/tcc780x/app.lds9
-rw-r--r--firmware/target/arm/tcc780x/crt0.S4
4 files changed, 11 insertions, 10 deletions
diff --git a/apps/plugins/plugin.lds b/apps/plugins/plugin.lds
index deb7813c49..f150b9d168 100644
--- a/apps/plugins/plugin.lds
+++ b/apps/plugins/plugin.lds
@@ -120,10 +120,13 @@ OUTPUT_FORMAT(elf32-littlemips)
120 120
121#elif defined(CPU_TCC780X) || defined(CPU_TCC77X) 121#elif defined(CPU_TCC780X) || defined(CPU_TCC77X)
122#define DRAMORIG 0x20000000 122#define DRAMORIG 0x20000000
123/*#define IRAMORIG 0x1000c000 123#if CONFIG_CPU==TCC7801
124#define IRAMSIZE 0xc000*/ 124#define IRAMORIG 0x1000c000
125#define IRAMSIZE 0xc000
126#else
125#define IRAM DRAM 127#define IRAM DRAM
126#define IRAMSIZE 0 128#define IRAMSIZE 0
129#endif
127 130
128#elif CONFIG_CPU==AS3525 || CONFIG_CPU==AS3525v2 131#elif CONFIG_CPU==AS3525 || CONFIG_CPU==AS3525v2
129#if defined(AMS_LOWMEM) || (CONFIG_CPU == AS3525v2) 132#if defined(AMS_LOWMEM) || (CONFIG_CPU == AS3525v2)
diff --git a/firmware/export/config.h b/firmware/export/config.h
index 0ed1be4157..b73f605d9d 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -727,6 +727,7 @@ Lyre prototype 1 */
727 (CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525 2MB: core only */ \ 727 (CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525 2MB: core only */ \
728 (CONFIG_CPU == AS3525v2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525v2: core only */ \ 728 (CONFIG_CPU == AS3525v2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525v2: core only */ \
729 (CONFIG_CPU == PNX0101) || \ 729 (CONFIG_CPU == PNX0101) || \
730 (CONFIG_CPU == TCC7801) || \
730 defined(CPU_S5L870X)) || /* Samsung S5L8700: core, plugins, codecs */ \ 731 defined(CPU_S5L870X)) || /* Samsung S5L8700: core, plugins, codecs */ \
731 (CONFIG_CPU == JZ4732 && !defined(PLUGIN) && !defined(CODEC)) /* Jz4740: core only */ 732 (CONFIG_CPU == JZ4732 && !defined(PLUGIN) && !defined(CODEC)) /* Jz4740: core only */
732#define ICODE_ATTR __attribute__ ((section(".icode"))) 733#define ICODE_ATTR __attribute__ ((section(".icode")))
diff --git a/firmware/target/arm/tcc780x/app.lds b/firmware/target/arm/tcc780x/app.lds
index a742908ce1..e31e46fde7 100644
--- a/firmware/target/arm/tcc780x/app.lds
+++ b/firmware/target/arm/tcc780x/app.lds
@@ -116,8 +116,7 @@ SECTIONS
116 *(.icode) 116 *(.icode)
117 . = ALIGN(0x4); 117 . = ALIGN(0x4);
118 _iramend = .; 118 _iramend = .;
119 /* } > SRAM AT> DRAM */ 119 } > SRAM AT> DRAM
120 } > DRAM
121 120
122 _iramcopy = LOADADDR(.iram); 121 _iramcopy = LOADADDR(.iram);
123 122
@@ -127,8 +126,7 @@ SECTIONS
127 *(.ibss) 126 *(.ibss)
128 . = ALIGN(0x4); 127 . = ALIGN(0x4);
129 _iend = .; 128 _iend = .;
130 /* } > SRAM */ 129 } > SRAM
131 } > DRAM
132 130
133 .stack : 131 .stack :
134 { 132 {
@@ -136,8 +134,7 @@ SECTIONS
136 stackbegin = .; 134 stackbegin = .;
137 . += 0x2000; 135 . += 0x2000;
138 stackend = .; 136 stackend = .;
139 /* } > SRAM */ 137 } > SRAM
140 } > DRAM
141 138
142 .bss : 139 .bss :
143 { 140 {
diff --git a/firmware/target/arm/tcc780x/crt0.S b/firmware/target/arm/tcc780x/crt0.S
index b1608915f1..f6eb6afbe9 100644
--- a/firmware/target/arm/tcc780x/crt0.S
+++ b/firmware/target/arm/tcc780x/crt0.S
@@ -155,8 +155,8 @@ copied_start:
155 ldr r0, =0x8001eec0 /* Region 6: 0x80000000-0xffffffff (2Gb) */ 155 ldr r0, =0x8001eec0 /* Region 6: 0x80000000-0xffffffff (2Gb) */
156 str r0, [r1,#0x18] /* AP: 3 EN: 1 DO: 6 CACHE_NONE */ 156 str r0, [r1,#0x18] /* AP: 3 EN: 1 DO: 6 CACHE_NONE */
157 157
158 ldr r0, =0x1001aee0 /* Region 7: 0x10000000-0x17ffffff (128Mb) */ 158 ldr r0, =0x1001aeec /* Region 7: 0x10000000-0x17ffffff (128Mb) */
159 str r0, [r1,#0x1c] /* AP: 3 EN: 1 DO: 7 CACHE_NONE */ 159 str r0, [r1,#0x1c] /* AP: 3 EN: 1 DO: 7 CACHE_ALL */
160 160
161 add r1, r1, #0x8000 161 add r1, r1, #0x8000
162 mcr p15, 0, r1, c2, c0, 0 /* Set TTBR = TABBASE (Virtual TLB) */ 162 mcr p15, 0, r1, c2, c0, 0 /* Set TTBR = TABBASE (Virtual TLB) */