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author | Jens Arnold <amiconn@rockbox.org> | 2010-05-31 20:13:27 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2010-05-31 20:13:27 +0000 |
commit | 64adb32cbfc805c01084ff935049998846c70dcd (patch) | |
tree | 98a9146856353fd6be1e5822099f76bc7b356e07 | |
parent | 85fd2d8be90ab3eb9f134180357725a60f988243 (diff) | |
download | rockbox-64adb32cbfc805c01084ff935049998846c70dcd.tar.gz rockbox-64adb32cbfc805c01084ff935049998846c70dcd.zip |
Port the greylib blitting optimisation to m:robe 100. It's even more efficient on monochrome LCDs - about 20% ISR speedup.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26435 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/olympus/mrobe-100/lcd-as-mr100.S | 42 |
1 files changed, 15 insertions, 27 deletions
diff --git a/firmware/target/arm/olympus/mrobe-100/lcd-as-mr100.S b/firmware/target/arm/olympus/mrobe-100/lcd-as-mr100.S index 2aede6d5e7..6db6c7efad 100644 --- a/firmware/target/arm/olympus/mrobe-100/lcd-as-mr100.S +++ b/firmware/target/arm/olympus/mrobe-100/lcd-as-mr100.S | |||
@@ -74,39 +74,27 @@ lcd_grey_data: | |||
74 | ldr lr, =LCD1_BASE | 74 | ldr lr, =LCD1_BASE |
75 | 75 | ||
76 | .greyloop: | 76 | .greyloop: |
77 | ldmia r1, {r3-r4} /* Fetch 8 pixel phases */ | 77 | ldmia r1, {r3-r4} |
78 | ldmia r0!, {r5-r6} /* Fetch 8 pixel values */ | 78 | |
79 | 79 | and r5, r12, r3 /* r5 = 3.......2.......1.......0....... */ | |
80 | mov r7, #0xff | 80 | and r6, r12, r4 /* r6 = 7.......6.......5.......4....... */ |
81 | tst r3, #0x80 | 81 | orr r5, r5, r6, lsr #4 /* r5 = 3...7...2...6...1...5...0...4... */ |
82 | biceq r7, r7, #0x80 | 82 | orr r5, r5, r5, lsr #9 /* r5 = 3...7...23..67..12..56..01..45.. */ |
83 | tst r3, #0x8000 | 83 | orr r5, r5, r5, lsr #9 /* r5 = 3...7...23..67..123.567.012.456. */ |
84 | biceq r7, r7, #0x40 | 84 | orr r5, r5, r5, lsr #9 /* r5 = 3...7...23..67..123.567.01234567 */ |
85 | tst r3, #0x800000 | 85 | |
86 | biceq r7, r7, #0x20 | 86 | ldmia r0!, {r6-r7} |
87 | tst r3, #0x80000000 | ||
88 | biceq r7, r7, #0x10 | ||
89 | bic r3, r3, r12 | 87 | bic r3, r3, r12 |
90 | add r3, r3, r5 | 88 | add r3, r3, r6 |
91 | |||
92 | tst r4, #0x80 | ||
93 | biceq r7, r7, #0x08 | ||
94 | tst r4, #0x8000 | ||
95 | biceq r7, r7, #0x04 | ||
96 | tst r4, #0x800000 | ||
97 | biceq r7, r7, #0x02 | ||
98 | tst r4, #0x80000000 | ||
99 | biceq r7, r7, #0x01 | ||
100 | bic r4, r4, r12 | 89 | bic r4, r4, r12 |
101 | add r4, r4, r6 | 90 | add r4, r4, r7 |
102 | |||
103 | stmia r1!, {r3-r4} | 91 | stmia r1!, {r3-r4} |
104 | 92 | ||
105 | 1: | 93 | 1: |
106 | ldr r5, [lr] | 94 | ldr r6, [lr] |
107 | tst r5, #LCD1_BUSY_MASK | 95 | tst r6, #LCD1_BUSY_MASK |
108 | bne 1b | 96 | bne 1b |
109 | str r7, [lr, #0x10] | 97 | str r5, [lr, #0x10] |
110 | 98 | ||
111 | subs r2, r2, #1 | 99 | subs r2, r2, #1 |
112 | bne .greyloop | 100 | bne .greyloop |