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authorMichael Sevakis <jethead71@rockbox.org>2009-02-08 22:32:41 +0000
committerMichael Sevakis <jethead71@rockbox.org>2009-02-08 22:32:41 +0000
commit94537f954e67d44fdd9703c062c4ee53599e0e74 (patch)
tree5dc555914ba4c6f943a90b0804fef9a5fead4a33
parent0222d0a5ebcc0be2e511abeb3ea8fbe7b4df8475 (diff)
downloadrockbox-94537f954e67d44fdd9703c062c4ee53599e0e74.tar.gz
rockbox-94537f954e67d44fdd9703c062c4ee53599e0e74.zip
Gigabeat S: Implement an SDMA API and use it in the PCM driver. Some other miscellaneous adjustments to recording and PCM buffer to accomodate use of physical addresses and cache coherency.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19949 a1c6a512-1295-4272-9138-f99709370657
Diffstat
-rw-r--r--apps/pcmbuf.c5
-rw-r--r--apps/recorder/pcm_record.c4
-rw-r--r--firmware/SOURCES2
-rw-r--r--firmware/export/config-gigabeat-s.h2
-rwxr-xr-xfirmware/export/imx31l.h151
-rw-r--r--firmware/export/pcm.h4
-rw-r--r--firmware/pcm.c3
-rw-r--r--firmware/target/arm/imx31/debug-imx31.c4
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c18
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h3
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/dma_start.c8
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c4
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c21
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/mmu-imx31.h2
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c366
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/system-imx31.c24
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/system-target.h2
-rw-r--r--firmware/target/arm/imx31/sdma-imx31.c807
-rw-r--r--firmware/target/arm/imx31/sdma-imx31.h225
-rw-r--r--firmware/target/arm/imx31/sdma_script_code.h1060
-rw-r--r--firmware/target/arm/imx31/sdma_struct.h426
21 files changed, 3001 insertions, 140 deletions
diff --git a/apps/pcmbuf.c b/apps/pcmbuf.c
index 99e56d160d..6e2234880e 100644
--- a/apps/pcmbuf.c
+++ b/apps/pcmbuf.c
@@ -1001,6 +1001,11 @@ void pcmbuf_beep(unsigned int frequency, size_t duration, int amplitude)
1001 /* Give 5ms clearance. */ 1001 /* Give 5ms clearance. */
1002 bufstart += NATIVE_FREQUENCY * 4 / 200; 1002 bufstart += NATIVE_FREQUENCY * 4 / 200;
1003 1003
1004#ifdef HAVE_PCM_DMA_ADDRESS
1005 /* Returned peak addresses are DMA addresses */
1006 bufend = pcm_dma_addr(bufend);
1007#endif
1008
1004 /* Wrapped above? */ 1009 /* Wrapped above? */
1005 if (bufstart >= bufend) 1010 if (bufstart >= bufend)
1006 bufstart -= pcmbuf_size; 1011 bufstart -= pcmbuf_size;
diff --git a/apps/recorder/pcm_record.c b/apps/recorder/pcm_record.c
index 8642150b18..8657aee1ba 100644
--- a/apps/recorder/pcm_record.c
+++ b/apps/recorder/pcm_record.c
@@ -1148,8 +1148,8 @@ static void pcmrec_init(void)
1148 1148
1149 buffer = audio_get_recording_buffer(&rec_buffer_size); 1149 buffer = audio_get_recording_buffer(&rec_buffer_size);
1150 1150
1151 /* Line align pcm_buffer 2^4=16 bytes */ 1151 /* Line align pcm_buffer 2^5=32 bytes */
1152 pcm_buffer = (unsigned char *)ALIGN_UP_P2((uintptr_t)buffer, 4); 1152 pcm_buffer = (unsigned char *)ALIGN_UP_P2((uintptr_t)buffer, 5);
1153 enc_buffer = pcm_buffer + ALIGN_UP_P2(PCM_NUM_CHUNKS*PCM_CHUNK_SIZE + 1153 enc_buffer = pcm_buffer + ALIGN_UP_P2(PCM_NUM_CHUNKS*PCM_CHUNK_SIZE +
1154 PCM_MAX_FEED_SIZE, 2); 1154 PCM_MAX_FEED_SIZE, 2);
1155 /* Adjust available buffer for possible align advancement */ 1155 /* Adjust available buffer for possible align advancement */
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 67a6a8a93a..0073b41f9f 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -756,7 +756,6 @@ target/arm/imx31/gigabeat-s/avic-imx31.c
756target/arm/imx31/gigabeat-s/backlight-imx31.c 756target/arm/imx31/gigabeat-s/backlight-imx31.c
757target/arm/imx31/gigabeat-s/button-imx31.c 757target/arm/imx31/gigabeat-s/button-imx31.c
758target/arm/imx31/gigabeat-s/clkctl-imx31.c 758target/arm/imx31/gigabeat-s/clkctl-imx31.c
759target/arm/imx31/gigabeat-s/dma_start.c
760target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c 759target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c
761target/arm/imx31/gigabeat-s/gpio-imx31.c 760target/arm/imx31/gigabeat-s/gpio-imx31.c
762target/arm/imx31/gigabeat-s/kernel-imx31.c 761target/arm/imx31/gigabeat-s/kernel-imx31.c
@@ -773,6 +772,7 @@ target/arm/imx31/gigabeat-s/system-imx31.c
773target/arm/imx31/gigabeat-s/usb-imx31.c 772target/arm/imx31/gigabeat-s/usb-imx31.c
774target/arm/imx31/gigabeat-s/wmcodec-imx31.c 773target/arm/imx31/gigabeat-s/wmcodec-imx31.c
775#ifndef BOOTLOADER 774#ifndef BOOTLOADER
775target/arm/imx31/sdma-imx31.c
776target/arm/imx31/gigabeat-s/audio-gigabeat-s.c 776target/arm/imx31/gigabeat-s/audio-gigabeat-s.c
777target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c 777target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
778target/arm/imx31/gigabeat-s/headphone-gigabeat-s.c 778target/arm/imx31/gigabeat-s/headphone-gigabeat-s.c
diff --git a/firmware/export/config-gigabeat-s.h b/firmware/export/config-gigabeat-s.h
index 6b993b6082..e5654fe0a2 100644
--- a/firmware/export/config-gigabeat-s.h
+++ b/firmware/export/config-gigabeat-s.h
@@ -214,6 +214,8 @@
214/* Define this if you have adjustable CPU frequency */ 214/* Define this if you have adjustable CPU frequency */
215/* #define HAVE_ADJUSTABLE_CPU_FREQ */ 215/* #define HAVE_ADJUSTABLE_CPU_FREQ */
216 216
217#define HAVE_PCM_DMA_ADDRESS
218
217#define BOOTFILE_EXT "gigabeat" 219#define BOOTFILE_EXT "gigabeat"
218#define BOOTFILE "rockbox." BOOTFILE_EXT 220#define BOOTFILE "rockbox." BOOTFILE_EXT
219#define BOOTDIR "/.rockbox" 221#define BOOTDIR "/.rockbox"
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index e31f30f1b0..cdae29f158 100755
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -118,6 +118,22 @@
118#define WDOG1_BASE_ADDR WDOG_BASE_ADDR 118#define WDOG1_BASE_ADDR WDOG_BASE_ADDR
119#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR 119#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
120 120
121/* IIM */
122#define IIM_PREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x20))
123 #define IIM_PREV_SIG (0x1f << 3)
124 #define IIM_PREV_SIG_IMX31 (0x01 << 3) /* i.MX31 */
125#define IIM_SREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x24))
126 #define IIM_SREV_SREV (0xff << 0)
127 #define IIM_SREV_1_0 0x00 /* i.MX31/L 1.0, L38W */
128 #define IIM_SREV_1_1 0x10 /* i.MX31 1.1, 2L38W */
129 #define IIM_SREV_1_1L 0x11 /* i.MX31L 1.1, 2L38W */
130 #define IIM_SREV_1_15 0x12 /* i.MX31 1.15, 2L38W/3L38W */
131 #define IIM_SREV_1_15L 0x13 /* i.MX31L 1.15, 2L38W/3L38W */
132 #define IIM_SREV_1_2 0x14 /* i.MX31 1.2, 3L38W, M45G */
133 #define IIM_SREV_1_2L 0x15 /* i.MX31L 1.2, 3L38W, M45G */
134 #define IIM_SREV_2_0_1 0x28 /* i.MX31 2.0/2.0.1, M91E */
135 #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */
136
121/* IOMUXC */ 137/* IOMUXC */
122#define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o))) 138#define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o)))
123 139
@@ -1618,6 +1634,141 @@
1618#define EUARTUTS_RXFULL (1 << 3) // RxFIFO full 1634#define EUARTUTS_RXFULL (1 << 3) // RxFIFO full
1619#define EUARTUTS_SOFTRST (1 << 0) // Software reset 1635#define EUARTUTS_SOFTRST (1 << 0) // Software reset
1620 1636
1637/* SDMA */
1638#define SDMA_MC0PTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x000))
1639#define SDMA_INTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x004))
1640#define SDMA_STOP_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x008))
1641#define SDMA_HSTART (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x00C))
1642#define SDMA_EVTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x010))
1643#define SDMA_DSPOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x014))
1644#define SDMA_HOSTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x018))
1645#define SDMA_EVTPEND (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x01C))
1646#define SDMA_DSPENBL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x020))
1647#define SDMA_RESET (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x024))
1648#define SDMA_EVTERR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x028))
1649#define SDMA_INTRMSK (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x02C))
1650#define SDMA_PSW (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x030))
1651#define SDMA_EVTERRDBG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x034))
1652#define SDMA_CONFIG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x038))
1653#define SDMA_ONCE_ENB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x040))
1654#define SDMA_ONCE_DATA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x044))
1655#define SDMA_ONCE_INSTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x048))
1656#define SDMA_ONCE_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x04C))
1657#define SDMA_ONCE_CMD (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x050))
1658#define SDMA_EVT_MIRROR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x054))
1659#define SDMA_ILLINSTADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x058))
1660#define SDMA_CHN0ADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x05C))
1661#define SDMA_ONCE_RTB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x060))
1662#define SDMA_XTRIG_CONF1 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x070))
1663#define SDMA_XTRIG_CONF2 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x074))
1664
1665/* SDMA_CHNENBL: 0x080 - 0x0FC */
1666#define SDMA_CHNENBL(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x080))[n]) /* 0..31 */
1667
1668/* SDMA_CHNPRI: 0x100 - 0x17C */
1669#define SDMA_CHNPRI(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x100))[n]) /* 0..31 */
1670
1671#define SDMA_ONCE_COUNT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x200))
1672#define SDMA_ONCE_ECTL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x204))
1673#define SDMA_ONCE_EAA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x208))
1674#define SDMA_ONCE_EAB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x20C))
1675#define SDMA_ONCE_EAM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x210))
1676#define SDMA_ONCE_ED (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x214))
1677#define SDMA_ONCE_EDM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x218))
1678#define SDMA_ONCE_PCMATCH (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x21C))
1679
1680/* SDMA_RESET */
1681#define SDMA_RESET_RESCHED (0x1 << 1)
1682#define SDMA_RESET_RESET (0x1 << 0)
1683
1684/* SDMA_PSW */
1685#define SDMA_PSW_NCP (0x7 << 13)
1686#define SDMA_PSW_NCR (0x1f << 8)
1687#define SDMA_PSW_CCP (0x7 << 5)
1688#define SDMA_PSW_CCR (0x1f << 0)
1689
1690/* SDMA_CONFIG */
1691#define SDMA_CONFIG_DSPDMA (0x1 << 12)
1692#define SDMA_CONFIG_RTDOBS (0x1 << 11)
1693#define SDMA_CONFIG_ACR (0x1 << 4)
1694#define SDMA_CONFIG_CSM (0x3 << 0)
1695 #define SDMA_CONFIG_CSM_STATIC (0x0 << 0)
1696 #define SDMA_CONFIG_CSM_DYNAMIC_LOW_POWER (0x1 << 0)
1697 #define SDMA_CONFIG_CSM_DYNAMIC_NO_LOOP (0x2 << 0)
1698 #define SDMA_CONFIG_CSM_DYNAMIC (0x3 << 0)
1699
1700/* SDMA_ONCE_ENB */
1701#define SDMA_ONCE_ENB_ENB (0x1 << 0)
1702
1703/* SDMA_ONCE_STAT */
1704#define SDMA_ONCE_STAT_PST (0xf << 12)
1705 #define SDMA_ONCE_STAT_PST_PROGRAM (0x0 << 12)
1706 #define SDMA_ONCE_STAT_PST_DATA (0x1 << 12)
1707 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW (0x2 << 12)
1708 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP (0x3 << 12)
1709 #define SDMA_ONCE_STAT_PST_DEBUG (0x4 << 12)
1710 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT (0x5 << 12)
1711 #define SDMA_ONCE_STAT_PST_SLEEP (0x6 << 12)
1712 #define SDMA_ONCE_STAT_PST_SAVE (0x7 << 12)
1713 #define SDMA_ONCE_STAT_PST_PROGRAM_IN_SLEEP (0x8 << 12)
1714 #define SDMA_ONCE_STAT_PST_DATA_IN_SLEEP (0x9 << 12)
1715 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_SLEEP (0xa << 12)
1716 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP_IN_SLEEP (0xb << 12)
1717 #define SDMA_ONCE_STAT_PST_DEBUG_IN_SLEEP (0xc << 12)
1718 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT_IN_SLEEP (0xd << 12)
1719 #define SDMA_ONCE_STAT_PST_SLEEP_AFTER_RESET (0xe << 12)
1720 #define SDMA_ONCE_STAT_PST_RESTORE (0xf << 12)
1721#define SDMA_ONCE_STAT_RCV (0x1 << 11)
1722#define SDMA_ONCE_STAT_EDR (0x1 << 10)
1723#define SDMA_ONCE_STAT_ODR (0x1 << 9)
1724#define SDMA_ONCE_STAT_SWB (0x1 << 8)
1725#define SDMA_ONCE_STAT_MST (0x1 << 7)
1726#define SDMA_ONCE_STAT_ECDR (0x7 << 0)
1727 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRA_COND (0x1 << 0)
1728 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRB_COND (0x1 << 1)
1729 #define SDMA_ONCE_STAT_ECDR_MATCHED_DATA_COND (0x1 << 2)
1730
1731/* SDMA_ONCE_CMD */
1732#define SDMA_ONCE_CMD_RSTATUS 0x0
1733#define SDMA_ONCE_CMD_DMOV 0x1
1734#define SDMA_ONCE_CMD_EXEC_ONCE 0x2
1735#define SDMA_ONCE_CMD_RUN_CORE 0x3
1736#define SDMA_ONCE_CMD_EXEC_CORE 0x4
1737#define SDMA_ONCE_CMD_DEBUG_RQST 0x5
1738#define SDMA_ONCE_CMD_RBUFFER 0x6
1739/* 7-15 reserved */
1740
1741/* SDMA_CHN0ADDR */
1742#define SDMA_CHN0ADDR_SMSZ (0x1 << 14)
1743/* 13:0 = 0x0050 by default (std. boot code) */
1744
1745/* SDMA_EVT_MIRROR */
1746#define SDMA_EVT_MIRROR_EVENTS(n) (0x1 << (n))
1747
1748/* SDMA_XTRIG_CONF1 */
1749#define SDMA_XTRIG_CONF1_CNF3 (0x1 << 30)
1750#define SDMA_XTRIG_CONF1_NUM3 (0x1f << 24)
1751#define SDMA_XTRIG_CONF1_CNF2 (0x1 << 22)
1752#define SDMA_XTRIG_CONF1_NUM2 (0x1f << 16)
1753#define SDMA_XTRIG_CONF1_CNF1 (0x1 << 14)
1754#define SDMA_XTRIG_CONF1_NUM1 (0x1f << 8)
1755#define SDMA_XTRIG_CONF1_CNF0 (0x1 << 6)
1756#define SDMA_XTRIG_CONF1_NUM0 (0x1f << 0)
1757
1758/* SDMA_XTRIG_CONF2 */
1759#define SDMA_XTRIG_CONF2_CNF7 (0x1 << 30)
1760#define SDMA_XTRIG_CONF2_NUM7 (0x1f << 24)
1761#define SDMA_XTRIG_CONF2_CNF6 (0x1 << 22)
1762#define SDMA_XTRIG_CONF2_NUM6 (0x1f << 16)
1763#define SDMA_XTRIG_CONF2_CNF5 (0x1 << 14)
1764#define SDMA_XTRIG_CONF2_NUM5 (0x1f << 8)
1765#define SDMA_XTRIG_CONF2_CNF4 (0x1 << 6)
1766#define SDMA_XTRIG_CONF2_NUM4 (0x1f << 0)
1767
1768/* SDMA_CHNENBL(n) */
1769#define SDMA_CHNENBL_ENBL(n) (0x1 << (n))
1770
1771
1621#define L2CC_ENABLED 1772#define L2CC_ENABLED
1622 1773
1623/* Assuming 26MHz input clock */ 1774/* Assuming 26MHz input clock */
diff --git a/firmware/export/pcm.h b/firmware/export/pcm.h
index 053f954767..444e0c9c09 100644
--- a/firmware/export/pcm.h
+++ b/firmware/export/pcm.h
@@ -90,6 +90,10 @@ extern unsigned long pcm_curr_sampr;
90extern unsigned long pcm_sampr; 90extern unsigned long pcm_sampr;
91extern int pcm_fsel; 91extern int pcm_fsel;
92 92
93#ifdef HAVE_PCM_DMA_ADDRESS
94void * pcm_dma_addr(void *addr);
95#endif
96
93/* the registered callback function to ask for more mp3 data */ 97/* the registered callback function to ask for more mp3 data */
94extern volatile pcm_more_callback_type pcm_callback_for_more; 98extern volatile pcm_more_callback_type pcm_callback_for_more;
95extern volatile bool pcm_playing; 99extern volatile bool pcm_playing;
diff --git a/firmware/pcm.c b/firmware/pcm.c
index 38204f883b..bc7ec0282a 100644
--- a/firmware/pcm.c
+++ b/firmware/pcm.c
@@ -53,6 +53,7 @@
53 * ==Playback/Recording== 53 * ==Playback/Recording==
54 * Semi-private - 54 * Semi-private -
55 * pcm_dma_apply_settings 55 * pcm_dma_apply_settings
56 * pcm_dma_addr
56 * 57 *
57 * ==Recording== 58 * ==Recording==
58 * Public - 59 * Public -
@@ -65,7 +66,7 @@
65 * pcm_rec_dma_stop 66 * pcm_rec_dma_stop
66 * pcm_rec_dma_get_peak_buffer 67 * pcm_rec_dma_get_peak_buffer
67 * Data Read/Written within TSP - 68 * Data Read/Written within TSP -
68 * pcm_rec_peak_addr (R) 69 * pcm_rec_peak_addr (R/W)
69 * pcm_callback_more_ready (R) 70 * pcm_callback_more_ready (R)
70 * pcm_recording (R) 71 * pcm_recording (R)
71 * 72 *
diff --git a/firmware/target/arm/imx31/debug-imx31.c b/firmware/target/arm/imx31/debug-imx31.c
index b72390cb63..ad436ea231 100644
--- a/firmware/target/arm/imx31/debug-imx31.c
+++ b/firmware/target/arm/imx31/debug-imx31.c
@@ -46,6 +46,10 @@ bool __dbg_hw_info(void)
46 while (1) 46 while (1)
47 { 47 {
48 line = 0; 48 line = 0;
49 snprintf(buf, sizeof (buf), "Sys Rev Code: 0x%02X",
50 iim_system_rev());
51 lcd_puts(0, line++, buf); line++;
52
49 mpctl = CLKCTL_MPCTL; 53 mpctl = CLKCTL_MPCTL;
50 spctl = CLKCTL_SPCTL; 54 spctl = CLKCTL_SPCTL;
51 upctl = CLKCTL_UPCTL; 55 upctl = CLKCTL_UPCTL;
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
index 784a3f6586..df592deecb 100644
--- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
@@ -24,6 +24,11 @@
24#include "cpu.h" 24#include "cpu.h"
25#include "clkctl-imx31.h" 25#include "clkctl-imx31.h"
26 26
27unsigned int imx31_get_src_pll(void)
28{
29 return (CLKCTL_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU;
30}
31
27void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg, 32void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
28 enum IMX31_CG_MODES mode) 33 enum IMX31_CG_MODES mode)
29{ 34{
@@ -72,8 +77,8 @@ unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll)
72 77
73unsigned int imx31_clkctl_get_ipg_clk(void) 78unsigned int imx31_clkctl_get_ipg_clk(void)
74{ 79{
75 unsigned int pll = imx31_clkctl_get_pll((CLKCTL_PMCR0 & 0xC0000000) == 0 ? 80 unsigned int pllnum = imx31_get_src_pll();
76 PLL_SERIAL : PLL_MCU); 81 unsigned int pll = imx31_clkctl_get_pll(pllnum);
77 uint32_t reg = CLKCTL_PDR0; 82 uint32_t reg = CLKCTL_PDR0;
78 unsigned int max_pdf = ((reg >> 3) & 0x7) + 1; 83 unsigned int max_pdf = ((reg >> 3) & 0x7) + 1;
79 unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1; 84 unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1;
@@ -81,6 +86,15 @@ unsigned int imx31_clkctl_get_ipg_clk(void)
81 return pll / (max_pdf * ipg_pdf); 86 return pll / (max_pdf * ipg_pdf);
82} 87}
83 88
89unsigned int imx31_clkctl_get_ahb_clk(void)
90{
91 unsigned int pllnum = imx31_get_src_pll();
92 unsigned int pll = imx31_clkctl_get_pll(pllnum);
93 unsigned int max_pdf = ((CLKCTL_PDR0 >> 3) & 0x7) + 1;
94
95 return pll / max_pdf;
96}
97
84unsigned int imx31_clkctl_get_ata_clk(void) 98unsigned int imx31_clkctl_get_ata_clk(void)
85{ 99{
86 return imx31_clkctl_get_ipg_clk(); 100 return imx31_clkctl_get_ipg_clk();
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
index 8d7f7dbb77..bd8f89a15b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
+++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
@@ -105,6 +105,9 @@ unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll);
105/* Return ipg_clk in HZ */ 105/* Return ipg_clk in HZ */
106unsigned int imx31_clkctl_get_ipg_clk(void); 106unsigned int imx31_clkctl_get_ipg_clk(void);
107 107
108/* Return ahb_clk in HZ */
109unsigned int imx31_clkctl_get_ahb_clk(void);
110
108/* Return the ATA frequency in HZ */ 111/* Return the ATA frequency in HZ */
109unsigned int imx31_clkctl_get_ata_clk(void); 112unsigned int imx31_clkctl_get_ata_clk(void);
110 113
diff --git a/firmware/target/arm/imx31/gigabeat-s/dma_start.c b/firmware/target/arm/imx31/gigabeat-s/dma_start.c
deleted file mode 100644
index c1ab6c15cb..0000000000
--- a/firmware/target/arm/imx31/gigabeat-s/dma_start.c
+++ /dev/null
@@ -1,8 +0,0 @@
1#include <sys/types.h>
2
3void dma_start(const void* addr, size_t size) {
4 (void) addr;
5 (void) size;
6 //TODO:
7}
8
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
index 3d7c577e3c..ff0c47abc2 100644
--- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
@@ -24,6 +24,7 @@
24#include "spi-imx31.h" 24#include "spi-imx31.h"
25#include "mc13783.h" 25#include "mc13783.h"
26#include "clkctl-imx31.h" 26#include "clkctl-imx31.h"
27#include "sdma-imx31.h"
27#include "kernel.h" 28#include "kernel.h"
28#include "thread.h" 29#include "thread.h"
29 30
@@ -64,6 +65,9 @@ void tick_start(unsigned int interval_in_ms)
64 65
65void kernel_device_init(void) 66void kernel_device_init(void)
66{ 67{
68#ifndef BOOTLOADER
69 sdma_init();
70#endif
67 spi_init(); 71 spi_init();
68 mc13783_init(); 72 mc13783_init();
69} 73}
diff --git a/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c
index 05de50c269..920a8c9fd3 100644
--- a/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c
@@ -22,21 +22,12 @@
22#include "mmu-imx31.h" 22#include "mmu-imx31.h"
23#include "mmu-arm.h" 23#include "mmu-arm.h"
24 24
25void memory_init(void) { 25unsigned long addr_virt_to_phys(unsigned long addr)
26#if 0 26{
27 ttb_init(); 27 return addr | CSD0_BASE_ADDR;
28 set_page_tables();
29 enable_mmu();
30#endif
31} 28}
32 29
33void set_page_tables() { 30unsigned long addr_phys_to_virt(unsigned long addr)
34#if 0 31{
35 map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */ 32 return addr & ~CSD0_BASE_ADDR;
36 /*This pa *might* change*/
37 map_section(0x80000000, 0, 64, CACHE_ALL); /* map RAM to 0 and enable caching for it */
38 map_section((int)FRAME1, (int)FRAME1, 1, BUFFERED); /* enable buffered writing for the framebuffer */
39 map_section((int)FRAME2, (int)FRAME2, 1, BUFFERED);
40#endif
41} 33}
42
diff --git a/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.h b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.h
index 930048c59b..c66a3d941d 100644
--- a/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.h
+++ b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.h
@@ -23,5 +23,7 @@
23 23
24void memory_init(void); 24void memory_init(void);
25void set_page_tables(void); 25void set_page_tables(void);
26unsigned long addr_virt_to_phys(unsigned long addr);
27unsigned long addr_phys_to_virt(unsigned long addr);
26 28
27#endif /* MMU_IMX31_H */ 29#endif /* MMU_IMX31_H */
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
index f53d98aee9..60801262b4 100644
--- a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
@@ -23,78 +23,93 @@
23#include "kernel.h" 23#include "kernel.h"
24#include "audio.h" 24#include "audio.h"
25#include "sound.h" 25#include "sound.h"
26#include "avic-imx31.h"
27#include "clkctl-imx31.h" 26#include "clkctl-imx31.h"
27#include "sdma-imx31.h"
28#include "mmu-imx31.h"
28 29
29/* This isn't DMA-based at the moment and is handled like Portal Player but 30#define DMA_PLAY_CH_NUM 2
30 * will suffice for starters. */ 31#define DMA_REC_CH_NUM 1
32
33static struct buffer_descriptor dma_play_bd DEVBSS_ATTR;
34static struct channel_descriptor dma_play_cd DEVBSS_ATTR;
31 35
32struct dma_data 36struct dma_data
33{ 37{
34 uint16_t *p;
35 size_t size;
36 int locked; 38 int locked;
39 int callback_pending; /* DMA interrupt happened while locked */
37 int state; 40 int state;
38}; 41};
39 42
40static struct dma_data dma_play_data = 43static struct dma_data dma_play_data =
41{ 44{
42 /* Initialize to a locked, stopped state */ 45 /* Initialize to a locked, stopped state */
43 .p = NULL,
44 .size = 0,
45 .locked = 0, 46 .locked = 0,
47 .callback_pending = 0,
46 .state = 0 48 .state = 0
47}; 49};
48 50
49void pcm_play_lock(void) 51static void play_dma_callback(void)
50{ 52{
51 if (++dma_play_data.locked == 1) 53 unsigned char *start;
54 size_t size;
55 pcm_more_callback_type get_more = pcm_callback_for_more;
56
57 if (dma_play_data.locked)
52 { 58 {
53 /* Atomically disable transmit interrupt */ 59 /* Callback is locked out */
54 imx31_regclr32(&SSI_SIER1, SSI_SIER_TIE); 60 dma_play_data.callback_pending = 1;
61 return;
55 } 62 }
56}
57 63
58void pcm_play_unlock(void) 64 if (get_more == NULL || (get_more(&start, &size), size == 0))
59{
60 if (--dma_play_data.locked == 0 && dma_play_data.state != 0)
61 { 65 {
62 /* Atomically enable transmit interrupt */ 66 /* Callback missing or no more DMA to do */
63 imx31_regset32(&SSI_SIER1, SSI_SIER_TIE); 67 pcm_play_dma_stop();
68 pcm_play_dma_stopped_callback();
69 }
70 else
71 {
72 start = (void*)(((unsigned long)start + 3) & ~3);
73 size &= ~3;
74
75 /* Flush any pending cache writes */
76 clean_dcache_range(start, size);
77 dma_play_bd.buf_addr = (void *)addr_virt_to_phys((unsigned long)start);
78 dma_play_bd.mode.count = size;
79 dma_play_bd.mode.command = TRANSFER_16BIT;
80 dma_play_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
81 sdma_channel_run(DMA_PLAY_CH_NUM);
64 } 82 }
65} 83}
66 84
67static void __attribute__((interrupt("IRQ"))) SSI1_HANDLER(void) 85void pcm_play_lock(void)
68{ 86{
69 register pcm_more_callback_type get_more; 87 if (++dma_play_data.locked == 1)
88 imx31_regclr32(&SSI_SIER1, SSI_SIER_TDMAE);
89}
70 90
71 do 91void pcm_play_unlock(void)
92{
93 if (--dma_play_data.locked == 0 && dma_play_data.state != 0)
72 { 94 {
73 while (dma_play_data.size > 0) 95 bool pending = false;
96 int oldstatus = disable_irq_save();
97
98 if (dma_play_data.callback_pending)
74 { 99 {
75 if (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 6) 100 pending = true;
76 { 101 dma_play_data.callback_pending = 0;
77 return;
78 }
79 SSI_STX0_1 = *dma_play_data.p++;
80 SSI_STX0_1 = *dma_play_data.p++;
81 dma_play_data.size -= 4;
82 } 102 }
83 103
84 /* p is empty, get some more data */ 104 SSI_SIER1 |= SSI_SIER_TDMAE;
85 get_more = pcm_callback_for_more; 105 restore_irq(oldstatus);
86 106
87 if (get_more) 107 /* Should an interrupt be forced instead? The upper pcm layer can
88 { 108 * call producer's callback in thread context so technically this is
89 get_more((unsigned char **)&dma_play_data.p, 109 * acceptable. */
90 &dma_play_data.size); 110 if (pending)
91 } 111 play_dma_callback();
92 } 112 }
93 while (dma_play_data.size > 0);
94
95 /* No more data, so disable the FIFO/interrupt */
96 pcm_play_dma_stop();
97 pcm_play_dma_stopped_callback();
98} 113}
99 114
100void pcm_dma_apply_settings(void) 115void pcm_dma_apply_settings(void)
@@ -104,6 +119,17 @@ void pcm_dma_apply_settings(void)
104 119
105void pcm_play_dma_init(void) 120void pcm_play_dma_init(void)
106{ 121{
122 /* Init channel information */
123 dma_play_cd.bd_count = 1;
124 dma_play_cd.callback = play_dma_callback;
125 dma_play_cd.shp_addr = SDMA_PER_ADDR_SSI1_TX1;
126 dma_play_cd.wml = SDMA_SSI_TXFIFO_WML*2;
127 dma_play_cd.per_type = SDMA_PER_SSI;
128 dma_play_cd.tran_type = SDMA_TRAN_EMI_2_PER;
129 dma_play_cd.event_id1 = SDMA_REQ_SSI1_TX1;
130
131 sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd);
132
107 imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL); 133 imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL);
108 imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL); 134 imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL);
109 135
@@ -111,8 +137,8 @@ void pcm_play_dma_init(void)
111 SSI_SCR2 &= ~SSI_SCR_SSIEN; 137 SSI_SCR2 &= ~SSI_SCR_SSIEN;
112 SSI_SCR1 &= ~SSI_SCR_SSIEN; 138 SSI_SCR1 &= ~SSI_SCR_SSIEN;
113 139
114 SSI_SIER1 = SSI_SIER_TFE0; /* TX0 can issue an interrupt */ 140 SSI_SIER1 = 0;
115 SSI_SIER2 = SSI_SIER_RFF0; /* RX0 can issue an interrupt */ 141 SSI_SIER2 = 0;
116 142
117 /* Set up audio mux */ 143 /* Set up audio mux */
118 144
@@ -155,8 +181,9 @@ void pcm_play_dma_init(void)
155 SSI_STCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) | 181 SSI_STCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
156 SSI_STRCCR_PMw(4-1); 182 SSI_STRCCR_PMw(4-1);
157 183
158 /* Transmit low watermark - 2 samples in FIFO */ 184 /* Transmit low watermark */
159 SSI_SFCSR1 = SSI_SFCSR_TFWM1w(1) | SSI_SFCSR_TFWM0w(2); 185 SSI_SFCSR1 = (SSI_SFCSR1 & ~SSI_SFCSR_TFWM0) |
186 SSI_SFCSR_TFWM0w(8-SDMA_SSI_TXFIFO_WML);
160 SSI_STMSK1 = 0; 187 SSI_STMSK1 = 0;
161 188
162 /* SSI2 - provides MCLK to codec. Receives data from codec. */ 189 /* SSI2 - provides MCLK to codec. Receives data from codec. */
@@ -186,8 +213,9 @@ void pcm_play_dma_init(void)
186 SSI_SRCCR2 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) | 213 SSI_SRCCR2 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
187 SSI_STRCCR_PMw(4-1); 214 SSI_STRCCR_PMw(4-1);
188 215
189 /* Receive high watermark - 6 samples in FIFO */ 216 /* Receive high watermark */
190 SSI_SFCSR2 = SSI_SFCSR_RFWM1w(8) | SSI_SFCSR_RFWM0w(6); 217 SSI_SFCSR2 = (SSI_SFCSR2 & ~SSI_SFCSR_RFWM0) |
218 SSI_SFCSR_RFWM0w(SDMA_SSI_RXFIFO_WML);
191 SSI_SRMSK2 = 0; 219 SSI_SRMSK2 = 0;
192 220
193 /* Enable SSI2 (codec clock) */ 221 /* Enable SSI2 (codec clock) */
@@ -199,7 +227,6 @@ void pcm_play_dma_init(void)
199void pcm_postinit(void) 227void pcm_postinit(void)
200{ 228{
201 audiohw_postinit(); 229 audiohw_postinit();
202 avic_enable_int(SSI1, IRQ, 8, SSI1_HANDLER);
203} 230}
204 231
205static void play_start_pcm(void) 232static void play_start_pcm(void)
@@ -207,32 +234,23 @@ static void play_start_pcm(void)
207 /* Stop transmission (if in progress) */ 234 /* Stop transmission (if in progress) */
208 SSI_SCR1 &= ~SSI_SCR_TE; 235 SSI_SCR1 &= ~SSI_SCR_TE;
209 236
210 /* Enable interrupt on unlock */
211 dma_play_data.state = 1;
212
213 /* Fill the FIFO or start when data is used up */
214 SSI_SCR1 |= SSI_SCR_SSIEN; /* Enable SSI */ 237 SSI_SCR1 |= SSI_SCR_SSIEN; /* Enable SSI */
215 SSI_STCR1 |= SSI_STCR_TFEN0; /* Enable TX FIFO */ 238 SSI_STCR1 |= SSI_STCR_TFEN0; /* Enable TX FIFO */
216 239
217 while (1) 240 dma_play_data.state = 1; /* Enable DMA requests on unlock */
218 {
219 if (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 6 || dma_play_data.size == 0)
220 {
221 SSI_SCR1 |= SSI_SCR_TE; /* Start transmitting */
222 return;
223 }
224 241
225 SSI_STX0_1 = *dma_play_data.p++; 242 /* Do prefill to prevent swapped channels (see TLSbo61214 in MCIMX31CE).
226 SSI_STX0_1 = *dma_play_data.p++; 243 * No actual solution was offered but this appears to work. */
227 dma_play_data.size -= 4; 244 SSI_STX0_1 = 0;
228 } 245 SSI_STX0_1 = 0;
246 SSI_STX0_1 = 0;
247 SSI_STX0_1 = 0;
248
249 SSI_SCR1 |= SSI_SCR_TE; /* Start transmitting */
229} 250}
230 251
231static void play_stop_pcm(void) 252static void play_stop_pcm(void)
232{ 253{
233 /* Disable interrupt */
234 SSI_SIER1 &= ~SSI_SIER_TIE;
235
236 /* Wait for FIFO to empty */ 254 /* Wait for FIFO to empty */
237 while (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 0); 255 while (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 0);
238 256
@@ -240,135 +258,227 @@ static void play_stop_pcm(void)
240 SSI_STCR1 &= ~SSI_STCR_TFEN0; 258 SSI_STCR1 &= ~SSI_STCR_TFEN0;
241 SSI_SCR1 &= ~(SSI_SCR_TE | SSI_SCR_SSIEN); 259 SSI_SCR1 &= ~(SSI_SCR_TE | SSI_SCR_SSIEN);
242 260
243 /* Do not enable interrupt on unlock */ 261 /* Do not enable DMA requests on unlock */
244 dma_play_data.state = 0; 262 dma_play_data.state = 0;
263 dma_play_data.callback_pending = 0;
245} 264}
246 265
247void pcm_play_dma_start(const void *addr, size_t size) 266void pcm_play_dma_start(const void *addr, size_t size)
248{ 267{
249 dma_play_data.p = (void *)(((uintptr_t)addr + 3) & ~3); 268 sdma_channel_stop(DMA_PLAY_CH_NUM);
250 dma_play_data.size = (size & ~3); 269
270 /* Disable transmission */
271 SSI_STCR1 &= ~SSI_STCR_TFEN0;
272 SSI_SCR1 &= ~(SSI_SCR_TE | SSI_SCR_SSIEN);
273
274 addr = (void *)(((unsigned long)addr + 3) & ~3);
275 size &= ~3;
276
277 clean_dcache_range(addr, size);
278 dma_play_bd.buf_addr =
279 (void *)addr_virt_to_phys((unsigned long)(void *)addr);
280 dma_play_bd.mode.count = size;
281 dma_play_bd.mode.command = TRANSFER_16BIT;
282 dma_play_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
251 283
252 play_start_pcm(); 284 play_start_pcm();
285 sdma_channel_start(DMA_PLAY_CH_NUM);
253} 286}
254 287
255void pcm_play_dma_stop(void) 288void pcm_play_dma_stop(void)
256{ 289{
290 sdma_channel_stop(DMA_PLAY_CH_NUM);
257 play_stop_pcm(); 291 play_stop_pcm();
258 dma_play_data.size = 0;
259} 292}
260 293
261void pcm_play_dma_pause(bool pause) 294void pcm_play_dma_pause(bool pause)
262{ 295{
263 if (pause) 296 if (pause)
264 { 297 {
298 sdma_channel_pause(DMA_PLAY_CH_NUM);
265 play_stop_pcm(); 299 play_stop_pcm();
266 } 300 }
267 else 301 else
268 { 302 {
269 uint32_t addr = (uint32_t)dma_play_data.p;
270 dma_play_data.p = (void *)((addr + 2) & ~3);
271 dma_play_data.size &= ~3;
272 play_start_pcm(); 303 play_start_pcm();
304 sdma_channel_run(DMA_PLAY_CH_NUM);
273 } 305 }
274} 306}
275 307
276/* Return the number of bytes waiting - full L-R sample pairs only */ 308/* Return the number of bytes waiting - full L-R sample pairs only */
277size_t pcm_get_bytes_waiting(void) 309size_t pcm_get_bytes_waiting(void)
278{ 310{
279 return dma_play_data.size & ~3; 311 static unsigned long dsa DEVBSS_ATTR;
312 long offs, size;
313 int oldstatus;
314
315 /* read burst dma source address register in channel context */
316 sdma_read_words(&dsa, CHANNEL_CONTEXT_ADDR(DMA_PLAY_CH_NUM)+0x0b, 1);
317
318 oldstatus = disable_irq_save();
319 offs = dsa - (unsigned long)dma_play_bd.buf_addr;
320 size = dma_play_bd.mode.count;
321 restore_irq(oldstatus);
322
323 /* Be addresses are coherent (no buffer change during read) */
324 if (offs >= 0 && offs < size)
325 {
326 return (size - offs) & ~3;
327 }
328
329 return 0;
280} 330}
281 331
282/* Return a pointer to the samples and the number of them in *count */ 332/* Return a pointer to the samples and the number of them in *count */
283const void * pcm_play_dma_get_peak_buffer(int *count) 333const void * pcm_play_dma_get_peak_buffer(int *count)
284{ 334{
285 uint32_t addr = (uint32_t)dma_play_data.p; 335 static unsigned long dsa DEVBSS_ATTR;
286 size_t cnt = dma_play_data.size; 336 unsigned long addr;
287 *count = cnt >> 2; 337 long offs, size;
288 return (void *)((addr + 2) & ~3); 338 int oldstatus;
339
340 /* read burst dma source address register in channel context */
341 sdma_read_words(&dsa, CHANNEL_CONTEXT_ADDR(DMA_PLAY_CH_NUM)+0x0b, 1);
342
343 oldstatus = disable_irq_save();
344 addr = dsa;
345 offs = addr - (unsigned long)dma_play_bd.buf_addr;
346 size = dma_play_bd.mode.count;
347 restore_irq(oldstatus);
348
349 /* Be addresses are coherent (no buffer change during read) */
350 if (offs >= 0 && offs < size)
351 {
352 *count = (size - offs) >> 2;
353 return (void *)((addr + 2) & ~3);
354 }
355
356 *count = 0;
357 return NULL;
358}
359
360void * pcm_dma_addr(void *addr)
361{
362 return (void *)addr_virt_to_phys((unsigned long)addr);
289} 363}
290 364
291#ifdef HAVE_RECORDING 365#ifdef HAVE_RECORDING
366static struct buffer_descriptor dma_rec_bd DEVBSS_ATTR;
367static struct channel_descriptor dma_rec_cd DEVBSS_ATTR;
368
292static struct dma_data dma_rec_data = 369static struct dma_data dma_rec_data =
293{ 370{
294 /* Initialize to a locked, stopped state */ 371 /* Initialize to a locked, stopped state */
295 .p = NULL,
296 .size = 0,
297 .locked = 0, 372 .locked = 0,
298 .state = 0 373 .state = 0
299}; 374};
300 375
301static void __attribute__((interrupt("IRQ"))) SSI2_HANDLER(void) 376static void rec_dma_callback(void)
302{ 377{
303 register pcm_more_callback_type2 more_ready; 378 pcm_more_callback_type2 more_ready;
379 int status = 0;
304 380
305 while (dma_rec_data.size > 0) 381 if (dma_rec_data.locked)
306 { 382 {
307 if (SSI_SFCSR_RFCNT0r(SSI_SFCSR2) < 2) 383 dma_rec_data.callback_pending = 1;
308 return; 384 return; /* Callback is locked out */
309
310 *dma_rec_data.p++ = SSI_SRX0_2;
311 *dma_rec_data.p++ = SSI_SRX0_2;
312 dma_rec_data.size -= 4;
313 } 385 }
314 386
387 if (dma_rec_bd.mode.status & BD_RROR)
388 status = DMA_REC_ERROR_DMA;
389
315 more_ready = pcm_callback_more_ready; 390 more_ready = pcm_callback_more_ready;
316 391
317 if (more_ready == NULL || more_ready(0) < 0) { 392 if (more_ready != NULL && more_ready(status) >= 0)
318 /* Finished recording */ 393 {
319 pcm_rec_dma_stop(); 394 sdma_channel_run(DMA_REC_CH_NUM);
320 pcm_rec_dma_stopped_callback(); 395 return;
321 } 396 }
397
398 /* Finished recording */
399 pcm_rec_dma_stop();
400 pcm_rec_dma_stopped_callback();
322} 401}
323 402
324void pcm_rec_lock(void) 403void pcm_rec_lock(void)
325{ 404{
326 if (++dma_rec_data.locked == 1) 405 if (++dma_rec_data.locked == 1)
327 { 406 imx31_regclr32(&SSI_SIER2, SSI_SIER_RDMAE);
328 /* Atomically disable receive interrupt */
329 imx31_regclr32(&SSI_SIER2, SSI_SIER_RIE);
330 }
331} 407}
332 408
333void pcm_rec_unlock(void) 409void pcm_rec_unlock(void)
334{ 410{
335 if (--dma_rec_data.locked == 0 && dma_rec_data.state != 0) 411 if (--dma_rec_data.locked == 0 && dma_rec_data.state != 0)
336 { 412 {
337 /* Atomically enable receive interrupt */ 413 bool pending = false;
338 imx31_regset32(&SSI_SIER2, SSI_SIER_RIE); 414 int oldstatus = disable_irq_save();
415
416 if (dma_rec_data.callback_pending)
417 {
418 pending = true;
419 dma_rec_data.callback_pending = 0;
420 }
421
422 SSI_SIER2 |= SSI_SIER_RDMAE;
423 restore_irq(oldstatus);
424
425 /* Should an interrupt be forced instead? The upper pcm layer can
426 * call consumer's callback in thread context so technically this is
427 * acceptable. */
428 if (pending)
429 rec_dma_callback();
339 } 430 }
340} 431}
341 432
342void pcm_record_more(void *start, size_t size) 433void pcm_record_more(void *start, size_t size)
343{ 434{
344 pcm_rec_peak_addr = start; /* Start peaking at dest */ 435 start = (void *)(((unsigned long)start + 3) & ~3);
345 dma_rec_data.p = start; /* Start of RX buffer */ 436 size &= ~3;
346 dma_rec_data.size = size; /* Bytes to transfer */ 437
438 /* Write back and invalidate - buffer must be coherent */
439 invalidate_dcache_range(start, size);
440
441 start = (void *)addr_virt_to_phys((unsigned long)start);
442
443 pcm_rec_peak_addr = start;
444 dma_rec_bd.buf_addr = start;
445 dma_rec_bd.mode.count = size;
446 dma_rec_bd.mode.command = TRANSFER_16BIT;
447 dma_rec_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
347} 448}
348 449
349void pcm_rec_dma_stop(void) 450void pcm_rec_dma_stop(void)
350{ 451{
351 /* Stop receiving data */ 452 /* Stop receiving data */
453 sdma_channel_stop(DMA_REC_CH_NUM);
454
455 imx31_regclr32(&SSI_SIER2, SSI_SIER_RDMAE);
456
352 SSI_SCR2 &= ~SSI_SCR_RE; /* Disable RX */ 457 SSI_SCR2 &= ~SSI_SCR_RE; /* Disable RX */
353 SSI_SRCR2 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */ 458 SSI_SRCR2 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */
354 459
355 dma_rec_data.state = 0; 460 dma_rec_data.state = 0;
356 461 dma_rec_data.callback_pending = 0;
357 avic_disable_int(SSI2);
358} 462}
359 463
360void pcm_rec_dma_start(void *addr, size_t size) 464void pcm_rec_dma_start(void *addr, size_t size)
361{ 465{
362 pcm_rec_dma_stop(); 466 pcm_rec_dma_stop();
363 467
468 addr = (void *)(((unsigned long)addr + 3) & ~3);
469 size &= ~3;
470
471 invalidate_dcache_range(addr, size);
472
473 addr = (void *)addr_virt_to_phys((unsigned long)addr);
364 pcm_rec_peak_addr = addr; 474 pcm_rec_peak_addr = addr;
365 dma_rec_data.p = addr; 475 dma_rec_bd.buf_addr = addr;
366 dma_rec_data.size = size; 476 dma_rec_bd.mode.count = size;
477 dma_rec_bd.mode.command = TRANSFER_16BIT;
478 dma_rec_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
367 479
368 dma_rec_data.state = 1; 480 dma_rec_data.state = 1;
369 481
370 avic_enable_int(SSI2, IRQ, 9, SSI2_HANDLER);
371
372 SSI_SRCR2 |= SSI_SRCR_RFEN0; /* Enable RX FIFO */ 482 SSI_SRCR2 |= SSI_SRCR_RFEN0; /* Enable RX FIFO */
373 483
374 /* Ensure clear FIFO */ 484 /* Ensure clear FIFO */
@@ -377,24 +487,58 @@ void pcm_rec_dma_start(void *addr, size_t size)
377 487
378 /* Enable receive */ 488 /* Enable receive */
379 SSI_SCR2 |= SSI_SCR_RE; 489 SSI_SCR2 |= SSI_SCR_RE;
490
491 sdma_channel_start(DMA_REC_CH_NUM);
380} 492}
381 493
382void pcm_rec_dma_close(void) 494void pcm_rec_dma_close(void)
383{ 495{
384 pcm_rec_dma_stop(); 496 pcm_rec_dma_stop();
497 sdma_channel_close(DMA_REC_CH_NUM);
385} 498}
386 499
387void pcm_rec_dma_init(void) 500void pcm_rec_dma_init(void)
388{ 501{
389 pcm_rec_dma_stop(); 502 pcm_rec_dma_stop();
503
504 /* Init channel information */
505 dma_rec_cd.bd_count = 1;
506 dma_rec_cd.callback = rec_dma_callback;
507 dma_rec_cd.shp_addr = SDMA_PER_ADDR_SSI2_RX1;
508 dma_rec_cd.wml = SDMA_SSI_RXFIFO_WML*2;
509 dma_rec_cd.per_type = SDMA_PER_SSI;
510 dma_rec_cd.tran_type = SDMA_TRAN_PER_2_EMI;
511 dma_rec_cd.event_id1 = SDMA_REQ_SSI2_RX1;
512
513 sdma_channel_init(DMA_REC_CH_NUM, &dma_rec_cd, &dma_rec_bd);
390} 514}
391 515
392const void * pcm_rec_dma_get_peak_buffer(int *count) 516const void * pcm_rec_dma_get_peak_buffer(int *count)
393{ 517{
394 unsigned long addr = (uint32_t)pcm_rec_peak_addr; 518 static unsigned long pda DEVBSS_ATTR;
395 unsigned long end = (uint32_t)dma_rec_data.p; 519 unsigned long buf, addr, end, bufend;
396 *count = (end >> 2) - (addr >> 2); 520 int oldstatus;
397 return (void *)(addr & ~3); 521
522 /* read burst dma destination address register in channel context */
523 sdma_read_words(&pda, CHANNEL_CONTEXT_ADDR(DMA_REC_CH_NUM)+0x0a, 1);
524
525 oldstatus = disable_irq_save();
526 end = pda;
527 buf = (unsigned long)dma_rec_bd.buf_addr;
528 addr = (unsigned long)pcm_rec_peak_addr;
529 bufend = buf + dma_rec_bd.mode.count;
530 restore_irq(oldstatus);
531
532 /* Be addresses are coherent (no buffer change during read) */
533 if (addr >= buf && addr < bufend &&
534 end >= buf && end < bufend)
535 {
536 *count = (end >> 2) - (addr >> 2);
537 return (void *)(addr & ~3);
538 }
539
540 *count = 0;
541 return NULL;
398} 542}
399 543
400#endif /* HAVE_RECORDING */ 544#endif /* HAVE_RECORDING */
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
index cb265af0a3..b3f0fd66c9 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
@@ -32,6 +32,28 @@
32#include "clkctl-imx31.h" 32#include "clkctl-imx31.h"
33#include "mc13783.h" 33#include "mc13783.h"
34 34
35static unsigned long product_rev;
36static unsigned long system_rev;
37
38/** IC revision info routines **/
39unsigned int iim_system_rev(void)
40{
41 return system_rev & IIM_SREV_SREV;
42}
43
44unsigned int iim_prod_rev(void)
45{
46 return product_rev;
47}
48
49static void iim_init(void)
50{
51 /* Initialize the IC revision info (required by SDMA) */
52 imx31_clkctl_module_clock_gating(CG_IIM, CGM_ON_ALL);
53 product_rev = IIM_PREV;
54 system_rev = IIM_SREV;
55}
56
35/** Watchdog timer routines **/ 57/** Watchdog timer routines **/
36 58
37/* Initialize the watchdog timer */ 59/* Initialize the watchdog timer */
@@ -155,6 +177,8 @@ void system_init(void)
155 /* MCR WFI enables wait mode */ 177 /* MCR WFI enables wait mode */
156 CLKCTL_CCMR &= ~(3 << 14); 178 CLKCTL_CCMR &= ~(3 << 14);
157 179
180 iim_init();
181
158 imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); 182 imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK);
159 imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); 183 imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK);
160 imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); 184 imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP);
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
index c7797e43c9..ae50ec4c78 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -43,6 +43,8 @@ void watchdog_service(void);
43void gpt_start(void); 43void gpt_start(void);
44void gpt_stop(void); 44void gpt_stop(void);
45 45
46unsigned int iim_system_rev(void);
47
46/* Prepare for transition to firmware */ 48/* Prepare for transition to firmware */
47void system_prepare_fw_start(void); 49void system_prepare_fw_start(void);
48void tick_stop(void); 50void tick_stop(void);
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c
new file mode 100644
index 0000000000..f845ed18d8
--- /dev/null
+++ b/firmware/target/arm/imx31/sdma-imx31.c
@@ -0,0 +1,807 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Michael Sevakis
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#include "config.h"
22#include "system.h"
23#include <string.h>
24#include "logf.h"
25#include "panic.h"
26#include "clkctl-imx31.h"
27#include "avic-imx31.h"
28#include "sdma_struct.h"
29#include "sdma-imx31.h"
30#include "sdma_script_code.h"
31#include "mmu-imx31.h"
32
33/* Most of the code in here is based upon the Linux BSP provided by Freescale
34 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. */
35
36/* Cut down to bare bones essentials */
37
38/* Script information that depends on system revision */
39static struct sdma_script_start_addrs script_info;
40/* Mask of channels with callback enabled */
41static unsigned long sdma_enabled_ints = 0;
42/* One channel control block per channel in physically mapped device RAM */
43static struct channel_control_block ccb_array[CH_NUM] DEVBSS_ATTR;
44/* Channel 0 (command channel) data */
45static struct buffer_descriptor_extd c0_buffer_desc DEVBSS_ATTR;
46
47/* All SDMA channel interrupts are handled here.
48 * Dispatches lower channel numbers first (prioritized by SDMA API callers
49 * who specify the desired channel number).
50 */
51static void __attribute__((interrupt("IRQ"))) SDMA_HANDLER(void)
52{
53 unsigned long pending = SDMA_INTR;
54
55 SDMA_INTR = pending; /* Ack all ints */
56 pending &= sdma_enabled_ints; /* Only dispatch ints with callback */
57
58 while (1)
59 {
60 unsigned int channel;
61
62 if (pending == 0)
63 break; /* No bits set */
64
65 channel = find_first_set_bit(pending);
66
67 pending &= ~(1ul << channel);
68
69 /* Call callback (required if using an interrupt) */
70 ccb_array[channel].channel_desc->callback();
71 }
72}
73
74/* Initialize script information based upon the system revision */
75static void init_script_info(void)
76{
77 if (iim_system_rev() == IIM_SREV_1_0)
78 {
79 /* Channel script info */
80 script_info.app_2_mcu_addr = app_2_mcu_ADDR_1;
81 script_info.ap_2_ap_addr = ap_2_ap_ADDR_1;
82 script_info.ap_2_bp_addr = -1;
83 script_info.bp_2_ap_addr = -1;
84 script_info.loopback_on_dsp_side_addr = -1;
85 script_info.mcu_2_app_addr = mcu_2_app_ADDR_1;
86 script_info.mcu_2_shp_addr = mcu_2_shp_ADDR_1;
87 script_info.mcu_interrupt_only_addr = -1;
88 script_info.shp_2_mcu_addr = shp_2_mcu_ADDR_1;
89 script_info.uartsh_2_mcu_addr = uartsh_2_mcu_ADDR_1;
90 script_info.uart_2_mcu_addr = uart_2_mcu_ADDR_1;
91 script_info.dptc_dvfs_addr = dptc_dvfs_ADDR_1;
92 script_info.firi_2_mcu_addr = firi_2_mcu_ADDR_1;
93 script_info.firi_2_per_addr = -1;
94 script_info.mshc_2_mcu_addr = mshc_2_mcu_ADDR_1;
95 script_info.per_2_app_addr = -1;
96 script_info.per_2_firi_addr = -1;
97 script_info.per_2_shp_addr = -1;
98 script_info.mcu_2_ata_addr = mcu_2_ata_ADDR_1;
99 script_info.mcu_2_firi_addr = mcu_2_firi_ADDR_1;
100 script_info.mcu_2_mshc_addr = mcu_2_mshc_ADDR_1;
101 script_info.ata_2_mcu_addr = ata_2_mcu_ADDR_1;
102 script_info.uartsh_2_per_addr = -1;
103 script_info.shp_2_per_addr = -1;
104 script_info.uart_2_per_addr = -1;
105 script_info.app_2_per_addr = -1;
106 /* Main code block info */
107 script_info.ram_code_size = RAM_CODE_SIZE_1;
108 script_info.ram_code_start_addr = RAM_CODE_START_ADDR_1;
109 script_info.mcu_start_addr = (unsigned long)sdma_code_1;
110 }
111 else
112 {
113 /* Channel script info */
114 script_info.app_2_mcu_addr = app_2_mcu_patched_ADDR_2;
115 script_info.ap_2_ap_addr = ap_2_ap_ADDR_2;
116 script_info.ap_2_bp_addr = ap_2_bp_ADDR_2;
117 script_info.bp_2_ap_addr = bp_2_ap_ADDR_2;
118 script_info.loopback_on_dsp_side_addr = -1;
119 script_info.mcu_2_app_addr = mcu_2_app_ADDR_2;
120 script_info.mcu_2_shp_addr = mcu_2_shp_patched_ADDR_2;
121 script_info.mcu_interrupt_only_addr = -1;
122 script_info.shp_2_mcu_addr = shp_2_mcu_patched_ADDR_2;
123 script_info.uartsh_2_mcu_addr = uartsh_2_mcu_patched_ADDR_2;
124 script_info.uart_2_mcu_addr = uart_2_mcu_patched_ADDR_2;
125 script_info.dptc_dvfs_addr = -1;
126 script_info.firi_2_mcu_addr = firi_2_mcu_ADDR_2;
127 script_info.firi_2_per_addr = -1;
128 script_info.mshc_2_mcu_addr = -1;
129 script_info.per_2_app_addr = -1;
130 script_info.per_2_firi_addr = -1;
131 script_info.per_2_shp_addr = per_2_shp_ADDR_2;
132 script_info.mcu_2_ata_addr = mcu_2_ata_ADDR_2;
133 script_info.mcu_2_firi_addr = mcu_2_firi_ADDR_2;
134 script_info.mcu_2_mshc_addr = -1;
135 script_info.ata_2_mcu_addr = ata_2_mcu_ADDR_2;
136 script_info.uartsh_2_per_addr = -1;
137 script_info.shp_2_per_addr = shp_2_per_ADDR_2;
138 script_info.uart_2_per_addr = -1;
139 script_info.app_2_per_addr = -1;
140 /* Main code block info */
141 script_info.ram_code_size = RAM_CODE_SIZE_2;
142 script_info.ram_code_start_addr = RAM_CODE_START_ADDR_2;
143 script_info.mcu_start_addr = (unsigned long)sdma_code_2;
144 }
145}
146
147/* Return pc of SDMA script in SDMA halfword space according to peripheral
148 * and transfer type */
149static unsigned long get_script_pc(unsigned int peripheral_type,
150 unsigned int transfer_type)
151{
152 unsigned long res = (unsigned short)-1;
153
154 switch (peripheral_type)
155 {
156 case SDMA_PER_MEMORY:
157 switch (transfer_type)
158 {
159 case SDMA_TRAN_EMI_2_INT:
160 case SDMA_TRAN_EMI_2_EMI:
161 case SDMA_TRAN_INT_2_EMI:
162 res = script_info.ap_2_ap_addr;
163 break;
164 default:
165 break;
166 }
167 break;
168
169#if 0 /* Not using this */
170 case SDMA_PER_DSP:
171 switch (transfer_type)
172 {
173 case SDMA_TRAN_EMI_2_DSP:
174 res = script_info.ap_2_bp_addr;
175 break;
176 case SDMA_TRAN_DSP_2_EMI:
177 res = script_info.bp_2_ap_addr;
178 break;
179 case SDMA_TRAN_DSP_2_EMI_LOOP:
180 res = script_info.loopback_on_dsp_side_addr;
181 break;
182 case SDMA_TRAN_EMI_2_DSP_LOOP:
183 res = script_info.mcu_interrupt_only_addr;
184 break;
185 default:
186 break;
187 }
188 break;
189#endif
190
191#if 0 /* Not using this */
192 case SDMA_PER_FIRI:
193 switch (transfer_type)
194 {
195 case SDMA_TRAN_PER_2_INT:
196 res = script_info.firi_2_per_addr;
197 break;
198 case SDMA_TRAN_PER_2_EMI:
199 res = script_info.firi_2_mcu_addr;
200 break;
201 case SDMA_TRAN_INT_2_PER:
202 res = script_info.per_2_firi_addr;
203 break;
204 case SDMA_TRAN_EMI_2_PER:
205 res = script_info.mcu_2_firi_addr;
206 break;
207 default:
208 break;
209 }
210 break;
211#endif
212
213#if 0 /* Not using this */
214 case SDMA_PER_UART:
215 switch (transfer_type)
216 {
217 case SDMA_TRAN_PER_2_INT:
218 res = script_info.uart_2_per_addr;
219 break;
220 case SDMA_TRAN_PER_2_EMI:
221 res = script_info.uart_2_mcu_addr;
222 break;
223 case SDMA_TRAN_INT_2_PER:
224 res = script_info.per_2_app_addr;
225 break;
226 case SDMA_TRAN_EMI_2_PER:
227 res = script_info.mcu_2_app_addr;
228 break;
229 default:
230 break;
231 }
232 break;
233#endif
234
235#if 0 /* Not using this */
236 case SDMA_PER_UART_SP:
237 switch (transfer_type)
238 {
239 case SDMA_TRAN_PER_2_INT:
240 res = script_info.uartsh_2_per_addr;
241 break;
242 case SDMA_TRAN_PER_2_EMI:
243 res = script_info.uartsh_2_mcu_addr;
244 break;
245 case SDMA_TRAN_INT_2_PER:
246 res = script_info.per_2_shp_addr;
247 break;
248 case SDMA_TRAN_EMI_2_PER:
249 res = script_info.mcu_2_shp_addr;
250 break;
251 default:
252 break;
253 }
254 break;
255#endif
256
257 case SDMA_PER_ATA:
258 switch (transfer_type)
259 {
260 case SDMA_TRAN_PER_2_EMI:
261 res = script_info.ata_2_mcu_addr;
262 break;
263 case SDMA_TRAN_EMI_2_PER:
264 res = script_info.mcu_2_ata_addr;
265 break;
266 default:
267 break;
268 }
269 break;
270
271 case SDMA_PER_CSPI:
272 case SDMA_PER_EXT:
273 case SDMA_PER_SSI:
274 switch (transfer_type)
275 {
276 case SDMA_TRAN_PER_2_INT:
277 res = script_info.app_2_per_addr;
278 break;
279 case SDMA_TRAN_PER_2_EMI:
280 res = script_info.app_2_mcu_addr;
281 break;
282 case SDMA_TRAN_INT_2_PER:
283 res = script_info.per_2_app_addr;
284 break;
285 case SDMA_TRAN_EMI_2_PER:
286 res = script_info.mcu_2_app_addr;
287 break;
288 default:
289 break;
290 }
291 break;
292
293#if 0 /* Not using this */
294 case SDMA_PER_MMC:
295 case SDMA_PER_SDHC:
296#endif
297 case SDMA_PER_SSI_SP:
298 case SDMA_PER_CSPI_SP:
299 switch (transfer_type)
300 {
301 case SDMA_TRAN_PER_2_INT:
302 res = script_info.shp_2_per_addr;
303 break;
304 case SDMA_TRAN_PER_2_EMI:
305 res = script_info.shp_2_mcu_addr;
306 break;
307 case SDMA_TRAN_INT_2_PER:
308 res = script_info.per_2_shp_addr;
309 break;
310 case SDMA_TRAN_EMI_2_PER:
311 res = script_info.mcu_2_shp_addr;
312 break;
313 default:
314 break;
315 }
316
317 case SDMA_PER_MSHC:
318 switch (transfer_type)
319 {
320 case SDMA_TRAN_PER_2_EMI:
321 res = script_info.mshc_2_mcu_addr;
322 break;
323 case SDMA_TRAN_EMI_2_PER:
324 res = script_info.mcu_2_mshc_addr;
325 break;
326 default:
327 break;
328 }
329
330 case SDMA_PER_CCM:
331 switch (transfer_type)
332 {
333 case SDMA_TRAN_PER_2_EMI:
334 res = script_info.dptc_dvfs_addr;
335 break;
336 default:
337 break;
338 }
339 }
340
341 if (res == (unsigned short)-1)
342 {
343 logf("SDMA script not found\n");
344 }
345
346 return res;
347}
348
349static unsigned int get_config(unsigned int transfer_type)
350{
351 unsigned int res = -1;
352
353 switch (transfer_type)
354 {
355 case SDMA_TRAN_PER_2_INT:
356 case SDMA_TRAN_PER_2_EMI:
357 case SDMA_TRAN_INT_2_PER:
358 case SDMA_TRAN_EMI_2_PER:
359 /*
360 * Peripheral <------> Memory
361 * evtOvr = 0 mcuOvr = 0 dspOvr = 1
362 */
363 res = CH_OWNSHP_MCU | CH_OWNSHP_EVT;
364 break;
365
366#if 0 /* Not using this */
367 case SDMA_TRAN_DSP_2_PER:
368 res = 0;
369 break;
370 case SDMA_TRAN_EMI_2_DSP:
371 case SDMA_TRAN_INT_2_DSP:
372 case SDMA_TRAN_DSP_2_INT:
373 case SDMA_TRAN_DSP_2_EMI:
374 case SDMA_TRAN_DSP_2_DSP:
375 /*
376 * DSP <-----------> Memory
377 * evtOvr = 1 mcuOvr = 0 dspOvr = 0
378 */
379 res = CH_OWNSHP_MCU | CH_OWNSHP_DSP;
380 break;
381#endif
382
383 case SDMA_TRAN_EMI_2_INT:
384 case SDMA_TRAN_EMI_2_EMI:
385 case SDMA_TRAN_INT_2_INT:
386 case SDMA_TRAN_INT_2_EMI:
387#if 0 /* Not using this */
388 case SDMA_TRAN_DSP_2_EMI_LOOP:
389 case SDMA_TRAN_EMI_2_DSP_LOOP:
390#endif
391 /* evtOvr = 1 mcuOvr = 0 dspOvr = 1 */
392 res = CH_OWNSHP_MCU;
393 break;
394
395#if 0 /* Not using this */
396 case SDMA_TRAN_PER_2_DSP:
397 /* evtOvr = 0 mcuOvr = 1 dspOvr = 0 */
398 res = CH_OWNSHP_DSP | CH_OWNSHP_EVT;
399 break;
400#endif
401
402 default:
403 break;
404 }
405
406 return res;
407}
408
409/* Fill the buffer descriptor with the values given in parameter.
410 * Expects physical addresses. */
411static inline void set_buffer_descriptor(
412 struct buffer_descriptor *bd_p,
413 unsigned int command, /* C0_* command or transfer size */
414 unsigned int status, /* BD_* flags */
415 unsigned int count, /* Size of buffer to transfer */
416 void *buf_addr, /* Buffer to transfer */
417 void *buf_addr_ext)
418{
419 bd_p->mode.command = command;
420 bd_p->mode.status = status;
421 bd_p->mode.count = count;
422 bd_p->buf_addr = buf_addr;
423 if (status & BD_EXTD)
424 ((struct buffer_descriptor_extd *)bd_p)->buf_addr_ext = buf_addr_ext;
425}
426
427/* Configure channel ownership */
428static void set_channel_ownership(unsigned int channel, unsigned int config)
429{
430 unsigned long bit = 1ul << channel;
431
432 /* DSP side */
433#if 0 /* Not using this */
434 imx31_regmod32(&SDMA_DSPOVR, (config & CH_OWNSHP_DSP) ? 0 : bit, bit);
435#endif
436 /* Event */
437 imx31_regmod32(&SDMA_EVTOVR, (config & CH_OWNSHP_EVT) ? 0 : bit, bit);
438 /* MCU side */
439 imx31_regmod32(&SDMA_HOSTOVR, (config & CH_OWNSHP_MCU) ? 0 : bit, bit);
440}
441
442static bool setup_channel(struct channel_control_block *ccb_p)
443{
444 static struct context_data context_buffer DEVBSS_ATTR;
445 struct channel_descriptor *cd_p;
446 unsigned int channel_cfg;
447 unsigned int channel;
448 unsigned long pc;
449
450 memset(&context_buffer, 0x00, sizeof (context_buffer));
451
452 channel = ccb_p - ccb_array;
453 cd_p = ccb_p->channel_desc;
454
455 /* Obtain script start address for perihperal and transfer type */
456 pc = get_script_pc(cd_p->per_type, cd_p->tran_type);
457
458 if (pc == (unsigned short)-1)
459 return false; /* Failed to find a script */
460
461 context_buffer.channel_state.pc = pc;
462
463 if (cd_p->per_type != SDMA_PER_MEMORY && cd_p->per_type != SDMA_PER_DSP)
464 {
465 /* Set peripheral DMA request mask for this channel */
466 context_buffer.event_mask1 = 1ul << cd_p->event_id1;
467
468 if (cd_p->per_type == SDMA_PER_ATA)
469 {
470 /* ATA has two */
471 context_buffer.event_mask2 = 1ul << cd_p->event_id2;
472 }
473
474 context_buffer.shp_addr = cd_p->shp_addr;
475 context_buffer.wml = cd_p->wml;
476 }
477 else
478 {
479 context_buffer.wml = SDMA_PER_ADDR_SDRAM;
480 }
481
482 /* Send channel context to SDMA core */
483 clean_dcache_range(&context_buffer, sizeof (context_buffer));
484 sdma_write_words((unsigned long *)&context_buffer,
485 CHANNEL_CONTEXT_ADDR(channel),
486 sizeof (context_buffer)/4);
487
488 if (cd_p->is_setup != 0)
489 return true; /* No more to do */
490
491 /* Obtain channel ownership configuration */
492 channel_cfg = get_config(cd_p->tran_type);
493
494 if (channel_cfg == (unsigned int)-1)
495 return false;
496
497 /* Set who owns it and thus can activate it */
498 set_channel_ownership(channel, channel_cfg);
499
500 if (channel_cfg & CH_OWNSHP_EVT)
501 {
502 /* Set event ID to channel activation bitmapping */
503 imx31_regset32(&SDMA_CHNENBL(cd_p->event_id1), 1ul << channel);
504
505 if (cd_p->per_type == SDMA_PER_ATA)
506 {
507 /* ATA has two */
508 imx31_regset32(&SDMA_CHNENBL(cd_p->event_id2), 1ul << channel);
509 }
510 }
511
512 cd_p->is_setup = 1;
513
514 return true;
515}
516
517/** Public routines **/
518void sdma_init(void)
519{
520 imx31_clkctl_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT);
521 int i;
522 unsigned long acr;
523
524 /* Reset the controller */
525 SDMA_RESET |= SDMA_RESET_RESET;
526 while (SDMA_RESET & SDMA_RESET_RESET);
527
528 init_script_info();
529
530 /* No channel enabled, all priorities 0 */
531 for (i = 0; i < CH_NUM; i++)
532 {
533 SDMA_CHNENBL(i) = 0;
534 SDMA_CHNPRI(i) = 0;
535 }
536
537 /* Ensure no ints pending */
538 SDMA_INTR = 0xffffffff;
539
540 /* Nobody owns any channel (yet) */
541 SDMA_HOSTOVR = 0xffffffff;
542 SDMA_DSPOVR = 0xffffffff;
543 SDMA_EVTOVR = 0xffffffff;
544
545 SDMA_MC0PTR = 0x00000000;
546
547 /* 32-word channel contexts, use default bootscript address */
548 SDMA_CHN0ADDR = SDMA_CHN0ADDR_SMSZ | 0x0050;
549
550 avic_enable_int(SDMA, IRQ, 8, SDMA_HANDLER);
551
552 /* SDMA core must run at the proper frequency based upon the AHB/IPG ratio */
553 acr = (imx31_clkctl_get_ahb_clk() / imx31_clkctl_get_ipg_clk()) < 2 ?
554 SDMA_CONFIG_ACR : 0;
555
556 /* No dsp, no debug
557 * Static context switching - TLSbo86520L SW Workaround for SDMA Chnl0
558 * access issue */
559 SDMA_CONFIG = acr;
560
561 /* Tell SDMA where the host channel table is */
562 SDMA_MC0PTR = (unsigned long)ccb_array;
563
564 ccb_array[0].status.opened_init = 1;
565 ccb_array[0].curr_bd_ptr = &c0_buffer_desc.bd;
566 ccb_array[0].base_bd_ptr = &c0_buffer_desc.bd;
567 ccb_array[0].channel_desc = NULL; /* No channel descriptor */
568
569 /* Command channel owned by AP */
570 set_channel_ownership(0, CH_OWNSHP_MCU);
571
572 sdma_channel_set_priority(0, 1);
573
574 /* Load SDMA script code */
575 set_buffer_descriptor(&c0_buffer_desc.bd,
576 C0_SETPM,
577 BD_DONE | BD_WRAP | BD_EXTD,
578 script_info.ram_code_size,
579 (void *)addr_virt_to_phys(script_info.mcu_start_addr),
580 (void *)(unsigned long)script_info.ram_code_start_addr);
581
582 SDMA_HSTART = 1ul;
583 sdma_channel_wait_nonblocking(0);
584
585 /* No dsp, no debug, dynamic context switching */
586 SDMA_CONFIG = acr | SDMA_CONFIG_CSM_DYNAMIC;
587}
588
589/* Busy wait for a channel to complete */
590void sdma_channel_wait_nonblocking(unsigned int channel)
591{
592 unsigned long mask;
593
594 if (channel >= CH_NUM)
595 return;
596
597 if (ccb_array[channel].status.opened_init == 0)
598 return;
599
600 mask = 1ul << channel;
601 while (SDMA_STOP_STAT & mask);
602}
603
604/* Set a new channel priority */
605void sdma_channel_set_priority(unsigned int channel, unsigned int priority)
606{
607 if (channel >= CH_NUM || priority > MAX_CH_PRIORITY)
608 return;
609
610 if (ccb_array[channel].status.opened_init == 0)
611 return;
612
613 SDMA_CHNPRI(channel) = priority;
614}
615
616/* Start a channel cold - resets execution to start of script */
617void sdma_channel_start(unsigned int channel)
618{
619 struct channel_control_block *ccb_p;
620
621 if (channel == 0 || channel >= CH_NUM)
622 return;
623
624 ccb_p = &ccb_array[channel];
625
626 if (ccb_p->status.opened_init == 0)
627 return;
628
629 if (!setup_channel(ccb_p))
630 return;
631
632 SDMA_HSTART = 1ul << channel;
633}
634
635/* Resume or start execution on a channel */
636void sdma_channel_run(unsigned int channel)
637{
638 if (channel == 0 || channel >= CH_NUM)
639 return;
640
641 if (ccb_array[channel].status.opened_init == 0)
642 return;
643
644 SDMA_HSTART = 1ul << channel;
645}
646
647/* Pause a running channel - can be resumed */
648void sdma_channel_pause(unsigned int channel)
649{
650 if (channel == 0 || channel >= CH_NUM)
651 return;
652
653 if (ccb_array[channel].status.opened_init == 0)
654 return;
655
656 SDMA_STOP_STAT = 1ul << channel;
657}
658
659/* Stop a channel from executing - cannot be resumed */
660void sdma_channel_stop(unsigned int channel)
661{
662 struct channel_control_block *ccb_p;
663 unsigned long chmsk;
664 unsigned long intmsk;
665 int oldstatus;
666 int i;
667
668 if (channel == 0 || channel >= CH_NUM)
669 return;
670
671 ccb_p = &ccb_array[channel];
672
673 if (ccb_p->status.opened_init == 0)
674 return;
675
676 chmsk = 1ul << channel;
677
678 /* Lock callback */
679 oldstatus = disable_irq_save();
680 intmsk = sdma_enabled_ints;
681 sdma_enabled_ints &= ~chmsk;
682 restore_irq(oldstatus);
683
684 /* Stop execution */
685 for (i = ccb_p->channel_desc->bd_count - 1; i >= 0; i--)
686 ccb_p->base_bd_ptr[i].mode.status &= ~BD_DONE;
687
688 SDMA_STOP_STAT = chmsk;
689 while (SDMA_STOP_STAT & chmsk);
690
691 /* Unlock callback if it was set */
692 if (intmsk & chmsk)
693 imx31_regset32(&sdma_enabled_ints, chmsk);
694
695 logf("SDMA ch closed: %d", channel);
696}
697
698bool sdma_channel_init(unsigned int channel,
699 struct channel_descriptor *cd_p,
700 struct buffer_descriptor *base_bd_p)
701{
702 struct channel_control_block *ccb_p;
703
704 if (channel == 0 || channel >= CH_NUM ||
705 cd_p == NULL || base_bd_p == NULL)
706 return false;
707
708 ccb_p = &ccb_array[channel];
709
710 /* If initialized already, should close first then init. */
711 if (ccb_p->status.opened_init != 0)
712 return false;
713
714 /* Initialize channel control block. */
715 ccb_p->curr_bd_ptr = base_bd_p;
716 ccb_p->base_bd_ptr = base_bd_p;
717 ccb_p->channel_desc = cd_p;
718 ccb_p->status.error = 0;
719 ccb_p->status.opened_init = 1;
720 ccb_p->status.state_direction = 0;
721 ccb_p->status.execute = 0;
722
723 /* Finish any channel descriptor inits. */
724 cd_p->ccb_ptr = ccb_p;
725 cd_p->is_setup = 0;
726
727 /* Do an initial setup now. */
728 if (!setup_channel(ccb_p))
729 {
730 logf("SDMA ch init failed: %d", channel);
731 cd_p->ccb_ptr = NULL;
732 memset(ccb_p, 0x00, sizeof (struct channel_control_block));
733 return false;
734 }
735
736 /* Enable interrupt if a callback is specified. */
737 if (cd_p->callback != NULL)
738 imx31_regset32(&sdma_enabled_ints, 1ul << channel);
739
740 /* Minimum schedulable = 1 */
741 sdma_channel_set_priority(channel, 1);
742
743 logf("SDMA ch initialized: %d", channel);
744 return true;
745}
746
747void sdma_channel_close(unsigned int channel)
748{
749 struct channel_control_block *ccb_p;
750 int i;
751
752 if (channel == 0 || channel >= CH_NUM)
753 return;
754
755 ccb_p = &ccb_array[channel];
756
757 /* Block callbacks (if not initialized, it won't be set). */
758 imx31_regclr32(&sdma_enabled_ints, 1ul << channel);
759
760 if (ccb_p->status.opened_init == 0)
761 return;
762
763 /* Stop the channel if running */
764 for (i = ccb_p->channel_desc->bd_count - 1; i >= 0; i--)
765 ccb_p->base_bd_ptr[i].mode.status &= ~BD_DONE;
766
767 sdma_channel_stop(channel);
768
769 /* No ownership */
770 set_channel_ownership(channel, 0);
771
772 /* Cannot schedule it again */
773 sdma_channel_set_priority(channel, 0);
774
775 /* Reset channel control block entry */
776 memset(ccb_p, 0x00, sizeof (struct channel_control_block));
777}
778
779/* Write 32-bit words to SDMA core memory. Host endian->SDMA endian. */
780void sdma_write_words(const unsigned long *buf, unsigned long start, int count)
781{
782 /* Setup buffer descriptor with channel 0 command */
783 set_buffer_descriptor(&c0_buffer_desc.bd,
784 C0_SETDM,
785 BD_DONE | BD_WRAP | BD_EXTD,
786 count,
787 (void *)addr_virt_to_phys((unsigned long)buf),
788 (void *)start);
789
790 SDMA_HSTART = 1ul;
791 sdma_channel_wait_nonblocking(0);
792}
793
794/* Read 32-bit words from SDMA core memory. SDMA endian->host endian. */
795void sdma_read_words(unsigned long *buf, unsigned long start, int count)
796{
797 /* Setup buffer descriptor with channel 0 command */
798 set_buffer_descriptor(&c0_buffer_desc.bd,
799 C0_GETDM,
800 BD_DONE | BD_WRAP | BD_EXTD,
801 count,
802 (void *)addr_virt_to_phys((unsigned long)buf),
803 (void *)start);
804
805 SDMA_HSTART = 1ul;
806 sdma_channel_wait_nonblocking(0);
807}
diff --git a/firmware/target/arm/imx31/sdma-imx31.h b/firmware/target/arm/imx31/sdma-imx31.h
new file mode 100644
index 0000000000..fa8195198b
--- /dev/null
+++ b/firmware/target/arm/imx31/sdma-imx31.h
@@ -0,0 +1,225 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Michael Sevakis
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef SDMA_IMX31_H
22#define SDMA_IMX31_H
23
24/* Much of the code in here is based upon the Linux BSP provided by Freescale
25 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. */
26
27/* Peripheral and transfer type - used to select the proper SDMA channel
28 * script to execute. */
29enum SDMA_PERIPHERAL_TYPE
30{
31 __SDMA_PER_FIRST = -1,
32 SDMA_PER_MEMORY,
33 SDMA_PER_DSP,
34 SDMA_PER_FIRI,
35 SDMA_PER_UART,
36 SDMA_PER_UART_SP, /* Shared */
37 SDMA_PER_ATA,
38 SDMA_PER_CSPI,
39 SDMA_PER_EXT,
40 SDMA_PER_SSI,
41 SDMA_PER_SSI_SP, /* Shared */
42 SDMA_PER_MMC,
43 SDMA_PER_SDHC,
44 SDMA_PER_CSPI_SP, /* Shared */
45 SDMA_PER_MSHC,
46 SDMA_PER_MSHC_SP, /* Shared */
47 SDMA_PER_CCM,
48 SDMA_PER_ASRC,
49 SDMA_PER_ESAI,
50 SDMA_PER_SIM,
51 SDMA_PER_SPDIF,
52 SDMA_PER_IPU_MEMORY,
53};
54
55enum SDMA_TRANSFER_TYPE
56{
57 __SDMA_TRAN_FIRST = -1,
58 SDMA_TRAN_INT_2_INT,
59 SDMA_TRAN_EMI_2_INT,
60 SDMA_TRAN_EMI_2_EMI,
61 SDMA_TRAN_INT_2_EMI,
62
63 SDMA_TRAN_INT_2_DSP,
64 SDMA_TRAN_DSP_2_INT,
65 SDMA_TRAN_DSP_2_DSP,
66 SDMA_TRAN_DSP_2_PER,
67 SDMA_TRAN_PER_2_DSP,
68 SDMA_TRAN_EMI_2_DSP,
69 SDMA_TRAN_DSP_2_EMI,
70 SDMA_TRAN_DSP_2_EMI_LOOP,
71 SDMA_TRAN_EMI_2_DSP_LOOP,
72
73 SDMA_TRAN_PER_2_INT,
74 SDMA_TRAN_PER_2_EMI,
75 SDMA_TRAN_INT_2_PER,
76 SDMA_TRAN_EMI_2_PER,
77};
78
79/* 2.3 - Smart Direct Memory Access (SDMA) Events, Table 2-5 */
80/* These are indexes into the SDMA_CHNENBL register array (each a bitmask
81 * determining which channels are triggered by requests). */
82enum SDMA_REQUEST_TYPE
83{
84 SDMA_REQ_EXT0 = 0, /* Extern DMA request from MCU1_0 */
85 SDMA_REQ_CCM = 1, /* DVFS/DPTC event (ccm_dvfs_sdma_int) */
86 SDMA_REQ_ATA_TX_END = 2, /* ata_txfer_end_alarm (event_id) */
87 SDMA_REQ_ATA_TX = 3, /* ata_tx_fifo_alarm (event_id2) */
88 SDMA_REQ_ATA_RX = 4, /* ata_rcv_fifo_alarm (event_id2) */
89 SDMA_REQ_SIM = 5, /* */
90 SDMA_REQ_CSPI2_RX = 6, /* DMA Rx request */
91 SDMA_REQ_CSPI2_TX = 7, /* DMA Tx request */
92 SDMA_REQ_CSPI1_RX = 8, /* DMA Rx request of CSPI */
93 SDMA_REQ_UART3_RX = 8, /* DMA Rx request RxFIFO of UART3 */
94 SDMA_REQ_CSPI1_TX = 9, /* DMA Tx request of CSPI */
95 SDMA_REQ_UART3_TX = 9, /* DMA Tx request TxFIFO of UART3 */
96 SDMA_REQ_CSPI3_RX = 10, /* RxFIFO or CSPI3 Rx request */
97 SDMA_REQ_UART5_RX = 10, /* RxFIFO or CSPI3 Rx request */
98 SDMA_REQ_CSPI3_TX = 11, /* TxFIFO or CSPI3 Tx request */
99 SDMA_REQ_UART5_TX = 11, /* TxFIFO or CSPI3 Tx request */
100 SDMA_REQ_UART4_RX = 12, /* RxFIFO */
101 SDMA_REQ_UART4_TX = 13, /* TxFIFO */
102 SDMA_REQ_EXT2 = 14, /* External DMA request from MCU1_2 or from
103 MBX (Graphic accelerator) */
104 SDMA_REQ_EXT1 = 15, /* External request from MCU1_1 */
105 SDMA_REQ_FIRI_RX = 16, /* DMA request of FIR's receiver FIFO
106 controlled by the pgp_firi signal
107 from the IOMUXC PGP register */
108 SDMA_REQ_UART2_RX = 16, /* RxFIFO of UART2 */
109 SDMA_REQ_FIRI_TX = 17, /* DMA request of FIR's transmitter
110 FIFO controled by the pgp_firi signal
111 the IOMUXC PGP register */
112 SDMA_REQ_UART2_TX = 17, /* TxFIFO of UART2 */
113 SDMA_REQ_UART1_RX = 18, /* RxFIFO */
114 SDMA_REQ_UART1_TX = 19, /* TxFIFO */
115 SDMA_REQ_MMC1 = 20, /* MMC DMA request */
116 SDMA_REQ_SDHC1 = 20, /* SDHC1 DMA request */
117 SDMA_REQ_MSHC1 = 20, /* MSHC1 DMA request */
118 SDMA_REQ_MMC2 = 21, /* MMC DMA request */
119 SDMA_REQ_SDHC2 = 21, /* SDHC2 DMA request */
120 SDMA_REQ_MSHC2 = 21, /* MSHC2 DMA request */
121 SDMA_REQ_SSI2_RX2 = 22, /* SSI #2 receive 2 DMA request (SRX1_2) */
122 SDMA_REQ_SSI2_TX2 = 23, /* SSI #2 transmit 2 DMA request (STX1_2) */
123 SDMA_REQ_SSI2_RX1 = 24, /* SSI #2 receive 1 DMA request (SRX0_2) */
124 SDMA_REQ_SSI2_TX1 = 25, /* SSI #2 transmit 1 DMA request (STX0_2) */
125 SDMA_REQ_SSI1_RX2 = 26, /* SSI #1 receive 2 DMA request (SRX1_1) */
126 SDMA_REQ_SSI1_TX2 = 27, /* SSI #1 transmit 2 DMA request (STX1_1) */
127 SDMA_REQ_SSI1_RX1 = 28, /* SSI #1 receive 1 DMA request (SRX1_0) */
128 SDMA_REQ_SSI1_TX1 = 29, /* SSI #1 transmit 1 DMA request (STX1_0) */
129 SDMA_REQ_NFC = 30, /* NAND-flash controller */
130 SDMA_REQ_IPU = 31, /* IPU source (defaults to IPU at reset) */
131 SDMA_REQ_ECT = 31, /* ECT source */
132};
133
134/* Addresses for peripheral DMA transfers */
135enum SDMA_PER_ADDR
136{
137 SDMA_PER_ADDR_SDRAM = SDRAM_BASE_ADDR, /* memory */
138 SDMA_PER_ADDR_CCM = CCM_BASE_ADDR+0x00, /* CCMR */
139 /* ATA */
140 SDMA_PER_ADDR_ATA_TX = ATA_DMA_BASE_ADDR+0x18,
141 SDMA_PER_ADDR_ATA_RX = ATA_DMA_BASE_ADDR,
142#if 0
143 SDMA_PER_ADDR_ATA_TX16 =
144 SDMA_PER_ADDR_ATA_RX16 =
145#endif
146#if 0
147 SDMA_PER_ADDR_SIM =
148#endif
149 /* CSPI2 */
150 SDMA_PER_ADDR_CSPI2_RX = CSPI2_BASE_ADDR+0x00, /* RXDATA2 */
151 SDMA_PER_ADDR_CSPI2_TX = CSPI2_BASE_ADDR+0x04, /* TXDATA2 */
152 /* CSPI1 */
153 SDMA_PER_ADDR_CSPI1_RX = CSPI1_BASE_ADDR+0x00, /* RXDATA1 */
154 SDMA_PER_ADDR_CSPI1_TX = CSPI1_BASE_ADDR+0x04, /* TXDATA1 */
155 /* UART3 */
156 SDMA_PER_ADDR_UART3_RX = UART3_BASE_ADDR+0x00, /* URXD3 */
157 SDMA_PER_ADDR_UART3_TX = UART3_BASE_ADDR+0x40, /* UTXD3 */
158 /* CSPI3 */
159 SDMA_PER_ADDR_CSPI3_RX = CSPI3_BASE_ADDR+0x00, /* RXDATA3 */
160 SDMA_PER_ADDR_CSPI3_TX = CSPI3_BASE_ADDR+0x04, /* TXDATA3 */
161 /* UART5 */
162 SDMA_PER_ADDR_UART5_RX = UART5_BASE_ADDR+0x00, /* URXD5 */
163 SDMA_PER_ADDR_UART5_TX = UART5_BASE_ADDR+0x40, /* UTXD5 */
164 /* UART4 */
165 SDMA_PER_ADDR_UART4_RX = UART4_BASE_ADDR+0x00, /* URXD4 */
166 SDMA_PER_ADDR_UART4_TX = UART4_BASE_ADDR+0x40, /* UTXD4 */
167 /* FIRI */
168 SDMA_PER_ADDR_FIRI_RX = FIRI_BASE_ADDR+0x18, /* Receiver FIFO */
169 SDMA_PER_ADDR_FIRI_TX = FIRI_BASE_ADDR+0x14, /* Transmitter FIFO */
170 /* UART2 */
171 SDMA_PER_ADDR_UART2_RX = UART2_BASE_ADDR+0x00, /* URXD2 */
172 SDMA_PER_ADDR_UART2_TX = UART2_BASE_ADDR+0x40, /* UTXD2 */
173 /* UART1 */
174 SDMA_PER_ADDR_UART1_RX = UART1_BASE_ADDR+0x00, /* URXD1 */
175 SDMA_PER_ADDR_UART1_TX = UART1_BASE_ADDR+0x40, /* UTXD1 */
176 SDMA_PER_ADDR_MMC_SDHC1 = MMC_SDHC1_BASE_ADDR+0x38, /* BUFFER_ACCESS */
177 SDMA_PER_ADDR_MMC_SDHC2 = MMC_SDHC2_BASE_ADDR+0x38, /* BUFFER_ACCESS */
178#if 0
179 SDMA_PER_ADDR_MSHC1 =
180 SDMA_PER_ADDR_MSHC2 =
181#endif
182 /* SSI2 */
183 SDMA_PER_ADDR_SSI2_RX2 = SSI2_BASE_ADDR+0x0C, /* SRX1_2 */
184 SDMA_PER_ADDR_SSI2_TX2 = SSI2_BASE_ADDR+0x04, /* STX1_2 */
185 SDMA_PER_ADDR_SSI2_RX1 = SSI2_BASE_ADDR+0x08, /* SRX0_2 */
186 SDMA_PER_ADDR_SSI2_TX1 = SSI2_BASE_ADDR+0x00, /* STX0_2 */
187 /* SSI1 */
188 SDMA_PER_ADDR_SSI1_RX2 = SSI1_BASE_ADDR+0x0C, /* SRX1_1 */
189 SDMA_PER_ADDR_SSI1_TX2 = SSI1_BASE_ADDR+0x04, /* STX1_1 */
190 SDMA_PER_ADDR_SSI1_RX1 = SSI1_BASE_ADDR+0x08, /* SRX0_1 */
191 SDMA_PER_ADDR_SSI1_TX1 = SSI1_BASE_ADDR+0x00, /* STX0_1 */
192#if 0
193 SDMA_PER_ADDR_NFC =
194 SDMA_PER_ADDR_IPU =
195 SDMA_PER_ADDR_ECT =
196#endif
197};
198
199/* DMA driver defines */
200#define SDMA_SDHC_MMC_WML 16
201#define SDMA_SDHC_SD_WML 64
202#define SDMA_SSI_TXFIFO_WML 4 /* Four samples written per channel activation */
203#define SDMA_SSI_RXFIFO_WML 6 /* Six samples read per channel activation */
204#define SDMA_FIRI_WML 16
205
206#define SDMA_ATA_WML 32 /* DMA watermark level in bytes */
207#define SDMA_ATA_BD_NR (512/3/4) /* Number of BDs per channel */
208
209#include "sdma_struct.h"
210
211void sdma_init(void);
212void sdma_read_words(unsigned long *buf, unsigned long start, int count);
213void sdma_write_words(const unsigned long *buf, unsigned long start, int count);
214void sdma_channel_set_priority(unsigned int channel, unsigned int priority);
215void sdma_channel_start(unsigned int channel);
216void sdma_channel_run(unsigned int channel);
217void sdma_channel_pause(unsigned int channel);
218void sdma_channel_stop(unsigned int channel);
219void sdma_channel_wait_nonblocking(unsigned int channel);
220bool sdma_channel_init(unsigned int channel,
221 struct channel_descriptor *cd_p,
222 struct buffer_descriptor *base_bd_p);
223void sdma_channel_close(unsigned int channel);
224
225#endif /* SDMA_IMX31_H */
diff --git a/firmware/target/arm/imx31/sdma_script_code.h b/firmware/target/arm/imx31/sdma_script_code.h
new file mode 100644
index 0000000000..b80c39534b
--- /dev/null
+++ b/firmware/target/arm/imx31/sdma_script_code.h
@@ -0,0 +1,1060 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Michael Sevakis
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22/*
23 * Taken from from the Linux BSP provided by Freescale.
24 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
25 */
26
27/* This header contains both versions 1 and 2 of SDMA code */
28
29#ifndef __SDMA_SCRIPT_CODE_H__
30#define __SDMA_SCRIPT_CODE_H__
31/*!
32* Following define start address of start script
33*/
34#define start_ADDR_1 0
35/*!
36* Following define size of start script
37*/
38#define start_SIZE_1 21
39
40/*!
41* Following define start address of core script
42*/
43#define core_ADDR_1 80
44/*!
45* Following define size of core script
46*/
47#define core_SIZE_1 152
48
49/*!
50* Following define start address of common script
51*/
52#define common_ADDR_1 232
53/*!
54* Following define size of common script
55*/
56#define common_SIZE_1 191
57
58/*!
59* Following define start address of burst_copy script
60*/
61#define burst_copy_ADDR_1 423
62/*!
63* Following define size of burst_copy script
64*/
65#define burst_copy_SIZE_1 87
66
67/*!
68* Following define start address of dsp_2_burst script
69*/
70#define dsp_2_burst_ADDR_1 510
71/*!
72* Following define size of dsp_2_burst script
73*/
74#define dsp_2_burst_SIZE_1 24
75
76/*!
77* Following define start address of burst_2_dsp script
78*/
79#define burst_2_dsp_ADDR_1 534
80/*!
81* Following define size of burst_2_dsp script
82*/
83#define burst_2_dsp_SIZE_1 24
84
85/*!
86* Following define start address of dsp_copy script
87*/
88#define dsp_copy_ADDR_1 558
89/*!
90* Following define size of dsp_copy script
91*/
92#define dsp_copy_SIZE_1 86
93
94/*!
95* Following define start address of mcu_2_mcu script
96*/
97#define mcu_2_mcu_ADDR_1 644
98/*!
99* Following define size of mcu_2_mcu script
100*/
101#define mcu_2_mcu_SIZE_1 79
102
103/*!
104* Following define start address of mcu_2_per script
105*/
106#define mcu_2_per_ADDR_1 723
107/*!
108* Following define size of mcu_2_per script
109*/
110#define mcu_2_per_SIZE_1 88
111
112/*!
113* Following define start address of test script
114*/
115#define test_ADDR_1 811
116/*!
117* Following define size of test script
118*/
119#define test_SIZE_1 63
120
121/*!
122* Following define start address of mcu_2_dsp script
123*/
124#define mcu_2_dsp_ADDR_1 874
125/*!
126* Following define size of mcu_2_dsp script
127*/
128#define mcu_2_dsp_SIZE_1 30
129
130/*!
131* Following define start address of mcu_2_dsp_2buf script
132*/
133#define mcu_2_dsp_2buf_ADDR_1 904
134/*!
135* Following define size of mcu_2_dsp_2buf script
136*/
137#define mcu_2_dsp_2buf_SIZE_1 113
138
139/*!
140* Following define start address of dsp_2_mcu script
141*/
142#define dsp_2_mcu_ADDR_1 1017
143/*!
144* Following define size of dsp_2_mcu script
145*/
146#define dsp_2_mcu_SIZE_1 30
147
148/*!
149* Following define start address of dsp_2_mcu_2buf script
150*/
151#define dsp_2_mcu_2buf_ADDR_1 1047
152/*!
153* Following define size of dsp_2_mcu_2buf script
154*/
155#define dsp_2_mcu_2buf_SIZE_1 113
156
157/*!
158* Following define start address of dsp_2_dsp script
159*/
160#define dsp_2_dsp_ADDR_1 1160
161/*!
162* Following define size of dsp_2_dsp script
163*/
164#define dsp_2_dsp_SIZE_1 64
165
166/*!
167* Following define start address of per_2_mcu script
168*/
169#define per_2_mcu_ADDR_1 1224
170/*!
171* Following define size of per_2_mcu script
172*/
173#define per_2_mcu_SIZE_1 121
174
175/*!
176* Following define start address of dsp_2_per_2buf script
177*/
178#define dsp_2_per_2buf_ADDR_1 1345
179/*!
180* Following define size of dsp_2_per_2buf script
181*/
182#define dsp_2_per_2buf_SIZE_1 164
183
184/*!
185* Following define start address of per_2_dsp_2buf script
186*/
187#define per_2_dsp_2buf_ADDR_1 1509
188/*!
189* Following define size of per_2_dsp_2buf script
190*/
191#define per_2_dsp_2buf_SIZE_1 168
192
193/*!
194* Following define start address of per_2_per script
195*/
196#define per_2_per_ADDR_1 1677
197/*!
198* Following define size of per_2_per script
199*/
200#define per_2_per_SIZE_1 67
201
202/*!
203* Following define start address of error_dsp script
204*/
205#define error_dsp_ADDR_1 1744
206/*!
207* Following define size of error_dsp script
208*/
209#define error_dsp_SIZE_1 34
210
211/*!
212* Following define start address of ap_2_ap script
213*/
214#define ap_2_ap_ADDR_1 6144
215/*!
216* Following define size of ap_2_ap script
217*/
218#define ap_2_ap_SIZE_1 294
219
220/*!
221* Following define start address of app_2_mcu script
222*/
223#define app_2_mcu_ADDR_1 6438
224/*!
225* Following define size of app_2_mcu script
226*/
227#define app_2_mcu_SIZE_1 101
228
229/*!
230* Following define start address of ata_2_mcu script
231*/
232#define ata_2_mcu_ADDR_1 6539
233/*!
234* Following define size of ata_2_mcu script
235*/
236#define ata_2_mcu_SIZE_1 110
237
238/*!
239* Following define start address of dptc_dvfs script
240*/
241#define dptc_dvfs_ADDR_1 6649
242/*!
243* Following define size of dptc_dvfs script
244*/
245#define dptc_dvfs_SIZE_1 274
246
247/*!
248* Following define start address of error script
249*/
250#define error_ADDR_1 6923
251/*!
252* Following define size of error script
253*/
254#define error_SIZE_1 73
255
256/*!
257* Following define start address of firi_2_mcu script
258*/
259#define firi_2_mcu_ADDR_1 6996
260/*!
261* Following define size of firi_2_mcu script
262*/
263#define firi_2_mcu_SIZE_1 114
264
265/*!
266* Following define start address of mcu_2_app script
267*/
268#define mcu_2_app_ADDR_1 7110
269/*!
270* Following define size of mcu_2_app script
271*/
272#define mcu_2_app_SIZE_1 127
273
274/*!
275* Following define start address of mcu_2_ata script
276*/
277#define mcu_2_ata_ADDR_1 7237
278/*!
279* Following define size of mcu_2_ata script
280*/
281#define mcu_2_ata_SIZE_1 87
282
283/*!
284* Following define start address of mcu_2_firi script
285*/
286#define mcu_2_firi_ADDR_1 7324
287/*!
288* Following define size of mcu_2_firi script
289*/
290#define mcu_2_firi_SIZE_1 77
291
292/*!
293* Following define start address of mcu_2_mshc script
294*/
295#define mcu_2_mshc_ADDR_1 7401
296/*!
297* Following define size of mcu_2_mshc script
298*/
299#define mcu_2_mshc_SIZE_1 48
300
301/*!
302* Following define start address of mcu_2_shp script
303*/
304#define mcu_2_shp_ADDR_1 7449
305/*!
306* Following define size of mcu_2_shp script
307*/
308#define mcu_2_shp_SIZE_1 123
309
310/*!
311* Following define start address of mshc_2_mcu script
312*/
313#define mshc_2_mcu_ADDR_1 7572
314/*!
315* Following define size of mshc_2_mcu script
316*/
317#define mshc_2_mcu_SIZE_1 60
318
319/*!
320* Following define start address of shp_2_mcu script
321*/
322#define shp_2_mcu_ADDR_1 7632
323/*!
324* Following define size of shp_2_mcu script
325*/
326#define shp_2_mcu_SIZE_1 101
327
328/*!
329* Following define start address of uart_2_mcu script
330*/
331#define uart_2_mcu_ADDR_1 7733
332/*!
333* Following define size of uart_2_mcu script
334*/
335#define uart_2_mcu_SIZE_1 105
336
337/*!
338* Following define start address of uartsh_2_mcu script
339*/
340#define uartsh_2_mcu_ADDR_1 7838
341/*!
342* Following define size of uartsh_2_mcu script
343*/
344#define uartsh_2_mcu_SIZE_1 98
345
346/*!
347* Following define the start address of sdma ram
348*/
349
350#define RAM_CODE_START_ADDR_1 6144
351/*!
352* Following define the size of sdma ram
353*/
354#define RAM_CODE_SIZE_1 1792
355
356/*!
357 * Code download for i.MX system revision = 1.0
358 */
359static __attribute__((aligned(4))) const short sdma_code_1[RAM_CODE_SIZE_1] =
360{
361 0xc0ec, 0x7d59, 0x0970, 0x0111, 0x5111, 0x5ad1, 0x5bd9, 0xc0fe,
362 0x5ce1, 0x7d02, 0x0200, 0x9806, 0x08ff, 0x0011, 0x28ff, 0x00bc,
363 0x05df, 0x7d4b, 0x06df, 0x7d2f, 0x6dc5, 0x6ed5, 0x5ef1, 0x0288,
364 0xd81a, 0x9854, 0x0b04, 0x00d3, 0x7d20, 0x06a5, 0x3e03, 0x3d03,
365 0x03a5, 0x3b03, 0x008b, 0x058b, 0x7802, 0x63d8, 0x0000, 0x7e72,
366 0x63ff, 0x7e70, 0x02a5, 0x008a, 0x4e00, 0x7d01, 0x983d, 0x6dcf,
367 0x6edf, 0x0015, 0x0015, 0x7802, 0x63d8, 0x0000, 0x7e63, 0x63ff,
368 0x7e61, 0x3a03, 0x008a, 0x6dcd, 0x6edd, 0x7801, 0x63d8, 0x7e5a,
369 0x63ff, 0x7e58, 0x0006, 0x6dc5, 0x6e07, 0x5ef1, 0x0288, 0xd8f7,
370 0x7e02, 0x7f04, 0x9854, 0x0007, 0x68cc, 0x6b28, 0x54e1, 0x0089,
371 0xdb13, 0x0188, 0x5ce1, 0x9854, 0x52d1, 0x53d9, 0x54e1, 0xc10d,
372 0x7dad, 0x0200, 0x9800, 0x0200, 0x9800, 0x06df, 0x7d06, 0x6d23,
373 0x6ed5, 0x5ef1, 0x0288, 0xd8cd, 0x9854, 0x5ef1, 0x6e07, 0x6d03,
374 0x0b04, 0x00d3, 0x7d59, 0x06a5, 0x3e03, 0x3d03, 0x4d00, 0x7d09,
375 0x03a5, 0x00a3, 0x0588, 0x008b, 0xd8c9, 0x7ed8, 0x620c, 0x7ed6,
376 0x008d, 0x4e00, 0x7c25, 0x0a20, 0x00da, 0x7c22, 0x6503, 0x3d1f,
377 0x02a5, 0x00a2, 0x0215, 0x0215, 0x6a18, 0x6a28, 0x7fc7, 0x0a20,
378 0x0b08, 0x00da, 0x7c06, 0x6b18, 0x6b28, 0x7fc0, 0x0000, 0x2020,
379 0x9889, 0x0688, 0x0015, 0x0015, 0x6818, 0x6828, 0x7fb7, 0x98c2,
380 0x0007, 0x6a0c, 0x54e1, 0x0089, 0xdb0f, 0x0188, 0x5ce1, 0x9854,
381 0x0b04, 0x00d3, 0x7d21, 0x0389, 0x1b12, 0x048b, 0x0688, 0x0015,
382 0x0015, 0x0588, 0x038c, 0x0a08, 0x05da, 0x008d, 0x7c01, 0x008a,
383 0x05a0, 0x7803, 0x620b, 0x5a03, 0x1b01, 0x7e98, 0x008b, 0x00a4,
384 0x038c, 0x7803, 0x5203, 0x6a0b, 0x1b01, 0x6a28, 0x7f8f, 0x0000,
385 0x4d00, 0x7ce8, 0x008e, 0x3803, 0xd8c9, 0x7e88, 0x620c, 0x7e86,
386 0x9854, 0x7802, 0x6209, 0x6a29, 0x0006, 0x3e03, 0x4e00, 0x7d11,
387 0x0b04, 0x03a6, 0x02db, 0x7d01, 0x038a, 0x02a3, 0x048a, 0x008b,
388 0x7802, 0x6329, 0x6bc8, 0x7ebc, 0x63c8, 0x7ebc, 0x008c, 0x4800,
389 0x7d15, 0x0488, 0x0015, 0x0015, 0x6edf, 0x7803, 0x632b, 0x6bc8,
390 0x0000, 0x7eae, 0x63c8, 0x7eae, 0x008c, 0x3803, 0x6edd, 0x7803,
391 0x6329, 0x6bc8, 0x0000, 0x7ea4, 0x63c8, 0x7ea4, 0x0006, 0x3d03,
392 0x4d00, 0x7d0e, 0x0b04, 0x03a5, 0x02db, 0x7d01, 0x038a, 0x02a3,
393 0x048a, 0x008b, 0x7802, 0x63c8, 0x6b09, 0x7e1e, 0x7f1e, 0x008c,
394 0x0488, 0x0015, 0x0015, 0x6dcf, 0x0288, 0x008a, 0x0d08, 0x02dd,
395 0x7c01, 0x008d, 0x7802, 0x63c8, 0x6b0b, 0x7e0e, 0x6b28, 0x7f0d,
396 0x0000, 0x02dd, 0x7c02, 0x2208, 0x990d, 0x008c, 0x3803, 0x65c0,
397 0x6dc5, 0x7802, 0x63c8, 0x6b09, 0x6b28, 0x0006, 0x0870, 0x0011,
398 0x5010, 0xc0ec, 0x7d5e, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8,
399 0x7d02, 0x0200, 0x992c, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, 0x0511,
400 0x1dff, 0x05bc, 0x4d00, 0x7d44, 0x0b70, 0x0311, 0x522b, 0x5313,
401 0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f3a, 0x0400, 0x993c, 0x008f,
402 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210,
403 0x4a00, 0x7d1c, 0x4a02, 0x7d20, 0x4a01, 0x7d23, 0x0b70, 0x0311,
404 0x53eb, 0x62c8, 0x7e24, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6a09,
405 0x7f1e, 0x0212, 0x6a09, 0x7f1b, 0x0212, 0x6a09, 0x7f18, 0x2003,
406 0x4800, 0x7cef, 0x0b70, 0x0311, 0x5313, 0x997d, 0x0015, 0x0015,
407 0x7802, 0x62c8, 0x6a0b, 0x997c, 0x0015, 0x7802, 0x62c8, 0x6a0a,
408 0x997c, 0x7802, 0x62c8, 0x6a09, 0x7c02, 0x0000, 0x993a, 0xdb13,
409 0x6a28, 0x7ffd, 0x008b, 0x52c3, 0x53cb, 0xc10d, 0x7da5, 0x0200,
410 0x992c, 0x0200, 0x9929, 0xc19d, 0xc0ec, 0x7d69, 0x0c70, 0x0411,
411 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe, 0x56fa, 0x7d02,
412 0x0200, 0x9994, 0x6d07, 0x5bca, 0x5cd2, 0x0bff, 0x0311, 0x1bff,
413 0x04bb, 0x0415, 0x53da, 0x4c00, 0x7d47, 0x0a70, 0x0211, 0x552a,
414 0x5212, 0x008d, 0x00bb, 0x4800, 0x7c07, 0x05b9, 0x4d00, 0x7c13,
415 0x6928, 0x7f2d, 0x0400, 0x99a5, 0x008f, 0x0015, 0x04d8, 0x7d01,
416 0x008c, 0x04a0, 0x0015, 0x7802, 0x55c6, 0x6d0b, 0x7e29, 0x6d28,
417 0x7f1e, 0x0000, 0x99a3, 0x1e20, 0x5506, 0x2620, 0x008d, 0x0560,
418 0x7c08, 0x065f, 0x55c6, 0x063f, 0x7e1b, 0x6d0a, 0x7f10, 0x4c00,
419 0x7d1b, 0x04d8, 0x7d02, 0x008c, 0x0020, 0x04a0, 0x0015, 0x7802,
420 0x55c6, 0x6d0b, 0x7e0d, 0x6d28, 0x7f02, 0x0000, 0x99ec, 0x0007,
421 0x680c, 0x6d0c, 0x6507, 0x6d07, 0x6d2b, 0x6d28, 0x0007, 0x680c,
422 0x0007, 0x54d2, 0x0454, 0x99ef, 0x6928, 0x7ff1, 0x54d2, 0x008a,
423 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7d9f, 0x0200, 0x9994, 0x0200,
424 0x998c, 0xc0ec, 0x7d72, 0x0800, 0x0970, 0x0111, 0x5111, 0x5ac1,
425 0x5bc9, 0x028e, 0xc0fe, 0x068a, 0x7c6a, 0x5dd9, 0x5ce1, 0x0bff,
426 0x0311, 0x1bff, 0x03bc, 0x5bd1, 0x1a5c, 0x6ac3, 0x63c8, 0x0363,
427 0x7c05, 0x036f, 0x7d27, 0x0374, 0x7c7a, 0x9a71, 0xdb04, 0x3c06,
428 0x4c00, 0x7df7, 0x028f, 0x1a04, 0x6a23, 0x620b, 0x6f23, 0x301f,
429 0x00aa, 0x0462, 0x7c04, 0x4a00, 0x7d0b, 0x2001, 0x9a30, 0x048a,
430 0x620b, 0x2201, 0x1c01, 0x1801, 0x02dc, 0x7d02, 0x301f, 0x00aa,
431 0x048f, 0x1c04, 0x6c07, 0x0488, 0x3c1f, 0x6c2b, 0x0045, 0x028e,
432 0x1a5c, 0x9a11, 0x058f, 0x1d0c, 0x6d23, 0x650b, 0x007d, 0x7c01,
433 0x1d08, 0x007c, 0x7c01, 0x1d04, 0x6d23, 0x650b, 0x0488, 0x3c1f,
434 0x0417, 0x0417, 0x0417, 0x0417, 0x059c, 0x6d23, 0x028e, 0x1a34,
435 0x6ad7, 0x0488, 0x0804, 0x7802, 0x650b, 0x6dc8, 0x008c, 0x1a28,
436 0x6ad7, 0x63c8, 0x034c, 0x6bc8, 0x54d1, 0x4c00, 0x7d06, 0x0065,
437 0x7c02, 0x0101, 0x0025, 0x0400, 0x9a0d, 0x52c1, 0x53c9, 0x54e1,
438 0x0453, 0xc10d, 0x7d95, 0x0200, 0x9a00, 0x0200, 0x99f9, 0x0200,
439 0x9a00, 0x55d9, 0x6d07, 0x54d1, 0x058a, 0x2508, 0x6dc7, 0x0373,
440 0x7c03, 0x65c8, 0x6d0b, 0x2408, 0x0372, 0x7c04, 0x65c8, 0x6d0b,
441 0x2408, 0x9a86, 0x6cce, 0x65c8, 0x6d0a, 0x2404, 0x6d28, 0x6507,
442 0x5dd9, 0x5cd1, 0x6ad7, 0x6ae3, 0x63c8, 0x0334, 0x6bc8, 0x0370,
443 0x7ca9, 0x0c60, 0x0411, 0x04bb, 0x4c00, 0x7da4, 0x0410, 0x1c30,
444 0x0410, 0x04bb, 0x046d, 0x7d0a, 0x047d, 0x7c03, 0x047c, 0x7c01,
445 0x9a3a, 0x003b, 0x003a, 0x0039, 0x0058, 0x9ab5, 0x047d, 0x7d03,
446 0x047c, 0x7d01, 0x9a3a, 0x005b, 0xdaf9, 0x1d18, 0x6d23, 0x650b,
447 0x0510, 0x003a, 0x0039, 0x0038, 0x00ad, 0xdb04, 0x0c30, 0x0410,
448 0x04bb, 0x003c, 0x003d, 0x00ac, 0xdaf9, 0x007b, 0x7c04, 0x003d,
449 0x003c, 0x1d0c, 0x9ad6, 0x048f, 0x1c14, 0x6c23, 0x640b, 0x4401,
450 0x7d04, 0x005d, 0x005c, 0x1d0c, 0x9ad6, 0x0310, 0x3b30, 0x4b30,
451 0x7d01, 0x1b10, 0x0310, 0x003d, 0x003c, 0x00ab, 0x6ad7, 0x63c8,
452 0x6d23, 0x650b, 0x0560, 0x7d03, 0x005e, 0xdaed, 0x9a3a, 0x003e,
453 0x0c80, 0x0410, 0x0394, 0xdaed, 0x640b, 0x037f, 0x7d02, 0x1a14,
454 0x9aea, 0x1a0c, 0x6ad7, 0x6cc8, 0x9a3a, 0x0c7f, 0x0410, 0x03b4,
455 0x04b8, 0x03ac, 0x640b, 0x6bc8, 0x028e, 0x1a04, 0x6ad7, 0x6cc8,
456 0x0006, 0x058f, 0x1d08, 0x6d23, 0x650b, 0x007d, 0x7c01, 0x1d38,
457 0x007c, 0x7c01, 0x1d1c, 0x0006, 0x048b, 0x042c, 0x0454, 0x042b,
458 0x6ad7, 0x6cc8, 0x0006, 0x0007, 0x684c, 0x6144, 0x9b1c, 0x0007,
459 0x68cc, 0x61d0, 0x9b1c, 0x0007, 0x680c, 0x680c, 0x6107, 0x6907,
460 0x692b, 0x6928, 0x0007, 0x680c, 0x0d70, 0x0511, 0x5515, 0x55f5,
461 0x01a5, 0x0dff, 0x0512, 0x1dff, 0x0512, 0x04bd, 0x0499, 0x0454,
462 0x0006, 0x08ff, 0x0011, 0x28ff, 0x0006, 0x038c, 0x0eff, 0x0611,
463 0x2eff, 0x03b6, 0x0006, 0x53d6, 0x0398, 0x5bd6, 0x53ee, 0x0398,
464 0x5bee, 0x0006, 0x52de, 0x53e6, 0x54ee, 0x0498, 0x0454, 0x0006,
465 0x50f6, 0x52c6, 0x53ce, 0x54d6, 0x0498, 0x0454, 0x0006, 0x6207,
466 0x0b70, 0x0311, 0x5013, 0x55f0, 0x02a5, 0x0bff, 0x0312, 0x1bff,
467 0x0312, 0x04bb, 0x049a, 0x0006, 0x1e10, 0x0870, 0x0011, 0x5010,
468 0xc0ec, 0x7d39, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02,
469 0x0200, 0x9b5b, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc,
470 0x4d00, 0x7d17, 0x6ec3, 0x62c8, 0x7e28, 0x0264, 0x7d08, 0x0b70,
471 0x0311, 0x522b, 0x02b9, 0x4a00, 0x7c18, 0x0400, 0x9b6a, 0x0212,
472 0x3aff, 0x008a, 0x05d8, 0x7d01, 0x008d, 0x0a10, 0x6ed3, 0x6ac8,
473 0xdba5, 0x6a28, 0x7f17, 0x0b70, 0x0311, 0x5013, 0xdbbd, 0x52c0,
474 0x53c8, 0xc10d, 0x7dd0, 0x0200, 0x9b5b, 0x008f, 0x00d5, 0x7d01,
475 0x008d, 0xdba5, 0x9b68, 0x0200, 0x9b58, 0x0007, 0x68cc, 0x6a28,
476 0x7f01, 0x9ba3, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07, 0x6a2b,
477 0x6a28, 0x0007, 0x680c, 0x0454, 0x9b81, 0x05a0, 0x1e08, 0x6ec3,
478 0x0388, 0x3b03, 0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b, 0x7ee5,
479 0x6a28, 0x7fe8, 0x0000, 0x6ec1, 0x008b, 0x7802, 0x62c8, 0x6a09,
480 0x7edc, 0x6a28, 0x7fdf, 0x2608, 0x0006, 0x55f0, 0x6207, 0x02a5,
481 0x0dff, 0x0511, 0x1dff, 0x04b5, 0x049a, 0x0006, 0x0870, 0x0011,
482 0x5010, 0xc0ec, 0x7d78, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8,
483 0x7d02, 0x0200, 0x9bcc, 0x6d03, 0x6ed3, 0x0dff, 0x0511, 0x1dff,
484 0x05bc, 0x5df8, 0x4d00, 0x7d5e, 0x0b70, 0x0311, 0x522b, 0x5313,
485 0x02b9, 0x4a00, 0x7c04, 0x62ff, 0x7e3f, 0x0400, 0x9bdc, 0x008f,
486 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5ddb, 0x0d03, 0x0512, 0x05bc,
487 0x0510, 0x5dd3, 0x4d00, 0x7d27, 0x4d02, 0x7d20, 0x4d01, 0x7d1a,
488 0x0b70, 0x0311, 0x53eb, 0x0360, 0x7d05, 0x6509, 0x7e25, 0x620a,
489 0x7e23, 0x9c06, 0x620a, 0x7e20, 0x6509, 0x7e1e, 0x0512, 0x0512,
490 0x02ad, 0x6ac8, 0x7f19, 0x2003, 0x4800, 0x7ced, 0x0b70, 0x0311,
491 0x5313, 0x9c21, 0x7802, 0x6209, 0x6ac8, 0x9c20, 0x0015, 0x7802,
492 0x620a, 0x6ac8, 0x9c20, 0x0015, 0x0015, 0x7802, 0x620b, 0x6ac8,
493 0x7c03, 0x0000, 0x55db, 0x9bda, 0x0007, 0x68cc, 0x680c, 0x55d3,
494 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9c2f, 0x0017, 0x0017, 0x55db,
495 0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8,
496 0x04ad, 0x0454, 0x62ff, 0x7ee8, 0x008b, 0x52c0, 0x53c8, 0xc10d,
497 0x7d8b, 0x0200, 0x9bcc, 0x0200, 0x9bc9, 0xc19d, 0xc0ec, 0x7d52,
498 0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe,
499 0x56fa, 0x7d02, 0x0200, 0x9c4e, 0x6d03, 0x5bca, 0x5cd2, 0x0bff,
500 0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da, 0x0a70, 0x0211, 0x4c00,
501 0x7d28, 0x552a, 0x05bb, 0x4d00, 0x7c02, 0x0400, 0x9c61, 0x4c01,
502 0x7d0f, 0x008f, 0x0015, 0x04d8, 0x7d01, 0x008c, 0x0020, 0x04a0,
503 0x0015, 0x7802, 0x650b, 0x5d06, 0x0000, 0x7e0c, 0x7f0d, 0x9c5f,
504 0x650a, 0x7e08, 0x008d, 0x0011, 0x0010, 0x05a8, 0x065f, 0x5d06,
505 0x063f, 0x7f02, 0x0007, 0x680c, 0x0007, 0x5012, 0x54d0, 0x0454,
506 0x9c8b, 0x5012, 0x54d0, 0x0473, 0x7c06, 0x552a, 0x05b9, 0x4d00,
507 0x7c02, 0x0400, 0x9c8d, 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7db6,
508 0x0200, 0x9c4e, 0x0200, 0x9c46, 0x0870, 0x0011, 0x5010, 0xc0ec,
509 0x7d46, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
510 0x9ca2, 0x0b70, 0x0311, 0x6ed3, 0x6d03, 0x0dff, 0x0511, 0x1dff,
511 0x05bc, 0x4d00, 0x7d2b, 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x62c8,
512 0x7e1f, 0x0400, 0x9cb3, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0,
513 0x0060, 0x7c05, 0x6edd, 0x6209, 0x7e16, 0x6ac8, 0x7f11, 0x0015,
514 0x0060, 0x7c05, 0x6ede, 0x620a, 0x7e0e, 0x6ac8, 0x7f09, 0x6edf,
515 0x0015, 0x7802, 0x620b, 0x6ac8, 0x0000, 0x7e05, 0x7f01, 0x9cb1,
516 0x0007, 0x68cc, 0x9cdd, 0x0007, 0x6a0c, 0x0454, 0x62c8, 0x7ef8,
517 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7dbd, 0x0200, 0x9ca2, 0x0200,
518 0x9c9f, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d29, 0x5010, 0x5ac0,
519 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9cf0, 0x0870, 0x0011,
520 0x6d03, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d12, 0x5228,
521 0x02b9, 0x4a00, 0x7c02, 0x0400, 0x9cff, 0x620b, 0x7e06, 0x5a06,
522 0x7f06, 0x0000, 0x2504, 0x7d05, 0x9cff, 0x0007, 0x680c, 0x0007,
523 0x0454, 0x5010, 0x52c0, 0xc10d, 0x7ddb, 0x0200, 0x9cf0, 0x0200,
524 0x9cec, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d74, 0x5010, 0x5ac0,
525 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9d20, 0x6d03,
526 0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd0, 0x0dff, 0x0511, 0x1dff,
527 0x05bc, 0x5df8, 0x4d00, 0x7d57, 0x0a70, 0x0211, 0x532a, 0x5212,
528 0x03b9, 0x4b00, 0x7c02, 0x0400, 0x9d34, 0x008f, 0x05d8, 0x7d01,
529 0x008d, 0x05a0, 0x5dda, 0x55d2, 0x4d00, 0x7d27, 0x4d02, 0x7d20,
530 0x4d01, 0x7d1a, 0x0a70, 0x0211, 0x52ea, 0x0260, 0x7d05, 0x6509,
531 0x7e25, 0x630a, 0x7e23, 0x9d58, 0x630a, 0x7e20, 0x6509, 0x7e1e,
532 0x0512, 0x0512, 0x03ad, 0x5b06, 0x7f19, 0x2003, 0x4800, 0x7ced,
533 0x0a70, 0x0211, 0x5212, 0x9d73, 0x7802, 0x6309, 0x5b06, 0x9d72,
534 0x0015, 0x7802, 0x630a, 0x5b06, 0x9d72, 0x0015, 0x0015, 0x7802,
535 0x630b, 0x5b06, 0x7c03, 0x55da, 0x0000, 0x9d32, 0x0007, 0x680c,
536 0x55d2, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9d80, 0x0017, 0x0017,
537 0x55da, 0x009d, 0x55fa, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010,
538 0x04b8, 0x04ad, 0x0454, 0x008a, 0x52c0, 0x53c8, 0xc10d, 0x7d90,
539 0x0200, 0x9d20, 0x0200, 0x9d1c, 0xc19d, 0x0870, 0x0011, 0xc0ec,
540 0x7d35, 0x5010, 0x5ac0, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200,
541 0x9d9b, 0x0870, 0x0011, 0x6d07, 0x0dff, 0x0511, 0x1dff, 0x05bc,
542 0x4d00, 0x7d1c, 0x5228, 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f0b,
543 0x0400, 0x9daa, 0x5206, 0x7e10, 0x6a0b, 0x6928, 0x7f04, 0x0000,
544 0x2504, 0x7d0c, 0x9daa, 0x0007, 0x680c, 0x680c, 0x6207, 0x6a07,
545 0x6a2b, 0x6a28, 0x0007, 0x680c, 0x0007, 0x0454, 0x6928, 0x7ff3,
546 0x5010, 0x52c0, 0xc10d, 0x7dcf, 0x0200, 0x9d9b, 0x0200, 0x9d97,
547 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d5e, 0x5010, 0x5ac0, 0x5bc8,
548 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9dd7, 0x6d07, 0x5df0,
549 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d44, 0x0a70, 0x0211,
550 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c04, 0x6a28, 0x7f3a, 0x0400,
551 0x9de6, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x0b03, 0x0312,
552 0x03bc, 0x0310, 0x4b00, 0x7d1c, 0x4b02, 0x7d20, 0x4b01, 0x7d23,
553 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e24, 0x0260, 0x7d02, 0x0310,
554 0x0312, 0x6b09, 0x7f1e, 0x0312, 0x6b09, 0x7f1b, 0x0312, 0x6b09,
555 0x7f18, 0x2003, 0x4800, 0x7cef, 0x0a70, 0x0211, 0x5212, 0x9e27,
556 0x0015, 0x0015, 0x7802, 0x5306, 0x6b0b, 0x9e26, 0x0015, 0x7802,
557 0x5306, 0x6b0a, 0x9e26, 0x7802, 0x5306, 0x6b09, 0x7c02, 0x0000,
558 0x9de4, 0xdb13, 0x6928, 0x7ffd, 0x008a, 0x52c0, 0x53c8, 0xc10d,
559 0x7da6, 0x0200, 0x9dd7, 0x0200, 0x9dd3, 0x0870, 0x0011, 0x5010,
560 0xc0ec, 0x7d5b, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02,
561 0x0200, 0x9e3b, 0x0b70, 0x0311, 0x6ec3, 0x6d07, 0x5df0, 0x0dff,
562 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d3d, 0x522b, 0x02b9, 0x4a00,
563 0x7c04, 0x6a28, 0x7f33, 0x0400, 0x9e4d, 0x028e, 0x1a94, 0x6ac3,
564 0x62c8, 0x0269, 0x7d1b, 0x1e94, 0x6ec3, 0x6ed3, 0x62c8, 0x0248,
565 0x6ac8, 0x2694, 0x6ec3, 0x62c8, 0x026e, 0x7d31, 0x6a09, 0x7f1e,
566 0x2501, 0x4d00, 0x7d1f, 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3,
567 0x0260, 0x7df1, 0x6a28, 0x7f12, 0xdb47, 0x9e8c, 0x6ee3, 0x008f,
568 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d17,
569 0x6a09, 0x7f04, 0x2001, 0x7cf9, 0x0000, 0x9e4b, 0x0289, 0xdb13,
570 0x018a, 0x9e9b, 0x6a28, 0x7ffa, 0x0b70, 0x0311, 0x5013, 0x52c0,
571 0x53c8, 0xc10d, 0x7da8, 0x0200, 0x9e3b, 0x0200, 0x9e38, 0x6a28,
572 0x7fed, 0xdb47, 0x9e9b, 0x0458, 0x0454, 0x9e8c, 0xc19d, 0x0870,
573 0x0011, 0xc0ec, 0x7d54, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe,
574 0x56f8, 0x7d02, 0x0200, 0x9ea5, 0x0b70, 0x0311, 0x6d07, 0x5df0,
575 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d36, 0x522b, 0x02b9,
576 0x4a00, 0x7c04, 0x6928, 0x7f2c, 0x0400, 0x9eb6, 0x028e, 0x1a94,
577 0x5202, 0x0269, 0x7d16, 0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694,
578 0x5206, 0x026e, 0x7d2e, 0x6a09, 0x7f1b, 0x2501, 0x4d00, 0x7d1c,
579 0x028e, 0x1a98, 0x5202, 0x0260, 0x7df3, 0x6a28, 0x7f11, 0xdb47,
580 0x9eee, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206,
581 0x026e, 0x7d17, 0x6a09, 0x7f04, 0x2001, 0x7cf9, 0x0000, 0x9eb4,
582 0x0289, 0xdb13, 0x018a, 0x9efd, 0x6928, 0x7ffa, 0x0b70, 0x0311,
583 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7db0, 0x0200, 0x9ea5, 0x0200,
584 0x9ea1, 0x6a28, 0x7fed, 0xdb47, 0x9efd, 0x0458, 0x0454, 0x9eee
585};
586
587/* REV 2 */
588/*!
589* Following define start address of signature script
590*/
591#define signature_ADDR_2 1023
592/*!
593* Following define size of signature script
594*/
595#define signature_SIZE_2 1
596
597/*!
598* Following define start address of start script
599*/
600#define start_ADDR_2 0
601/*!
602* Following define size of start script
603*/
604#define start_SIZE_2 20
605
606/*!
607* Following define start address of core script
608*/
609#define core_ADDR_2 80
610/*!
611* Following define size of core script
612*/
613#define core_SIZE_2 152
614
615/*!
616* Following define start address of common script
617*/
618#define common_ADDR_2 232
619/*!
620* Following define size of common script
621*/
622#define common_SIZE_2 191
623
624/*!
625* Following define start address of ap_2_ap script
626*/
627#define ap_2_ap_ADDR_2 423
628/*!
629* Following define size of ap_2_ap script
630*/
631#define ap_2_ap_SIZE_2 294
632
633/*!
634* Following define start address of bp_2_bp script
635*/
636#define bp_2_bp_ADDR_2 717
637/*!
638* Following define size of bp_2_bp script
639*/
640#define bp_2_bp_SIZE_2 112
641
642/*!
643* Following define start address of ap_2_bp script
644*/
645#define ap_2_bp_ADDR_2 829
646/*!
647* Following define size of ap_2_bp script
648*/
649#define ap_2_bp_SIZE_2 200
650
651/*!
652* Following define start address of bp_2_ap script
653*/
654#define bp_2_ap_ADDR_2 1029
655/*!
656* Following define size of bp_2_ap script
657*/
658#define bp_2_ap_SIZE_2 223
659
660/*!
661* Following define start address of app_2_mcu script
662*/
663#define app_2_mcu_ADDR_2 1252
664/*!
665* Following define size of app_2_mcu script
666*/
667#define app_2_mcu_SIZE_2 101
668
669/*!
670* Following define start address of mcu_2_app script
671*/
672#define mcu_2_app_ADDR_2 1353
673/*!
674* Following define size of mcu_2_app script
675*/
676#define mcu_2_app_SIZE_2 127
677
678/*!
679* Following define start address of uart_2_mcu script
680*/
681#define uart_2_mcu_ADDR_2 1480
682/*!
683* Following define size of uart_2_mcu script
684*/
685#define uart_2_mcu_SIZE_2 105
686
687/*!
688* Following define start address of uartsh_2_mcu script
689*/
690#define uartsh_2_mcu_ADDR_2 1585
691/*!
692* Following define size of uartsh_2_mcu script
693*/
694#define uartsh_2_mcu_SIZE_2 98
695
696/*!
697* Following define start address of mcu_2_shp script
698*/
699#define mcu_2_shp_ADDR_2 1683
700/*!
701* Following define size of mcu_2_shp script
702*/
703#define mcu_2_shp_SIZE_2 123
704
705/*!
706* Following define start address of shp_2_mcu script
707*/
708#define shp_2_mcu_ADDR_2 1806
709/*!
710* Following define size of shp_2_mcu script
711*/
712#define shp_2_mcu_SIZE_2 101
713
714/*!
715* Following define start address of error script
716*/
717#define error_ADDR_2 1907
718/*!
719* Following define size of error script
720*/
721#define error_SIZE_2 73
722
723/*!
724* Following define start address of test script
725*/
726#define test_ADDR_2 1980
727/*!
728* Following define size of test script
729*/
730#define test_SIZE_2 63
731
732/*!
733* SDMA RAM scripts start addresses and sizes
734*/
735
736/*!
737* Following define start address of app_2_mcu_patched script
738*/
739#define app_2_mcu_patched_ADDR_2 6144
740/*!
741* Following define size of app_2_mcu_patched script
742*/
743#define app_2_mcu_patched_SIZE_2 104
744
745/*!
746* Following define start address of ata_2_mcu script
747*/
748#define ata_2_mcu_ADDR_2 6248
749/*!
750* Following define size of ata_2_mcu script
751*/
752#define ata_2_mcu_SIZE_2 110
753
754/*!
755* Following define start address of firi_2_mcu script
756*/
757#define firi_2_mcu_ADDR_2 6358
758/*!
759* Following define size of firi_2_mcu script
760*/
761#define firi_2_mcu_SIZE_2 114
762
763/*!
764* Following define start address of mcu_2_app_patched script
765*/
766#define mcu_2_app_patched_ADDR_2 6472
767/*!
768* Following define size of mcu_2_app_patched script
769*/
770#define mcu_2_app_patched_SIZE_2 129
771
772/*!
773* Following define start address of mcu_2_ata script
774*/
775#define mcu_2_ata_ADDR_2 6601
776/*!
777* Following define size of mcu_2_ata script
778*/
779#define mcu_2_ata_SIZE_2 87
780/*!
781* Following define start address of mcu_2_firi script
782*/
783#define mcu_2_firi_ADDR_2 6688
784/*!
785* Following define size of mcu_2_firi script
786*/
787#define mcu_2_firi_SIZE_2 77
788/*!
789* Following define start address of mcu_2_shp_patched script
790*/
791#define mcu_2_shp_patched_ADDR_2 6765
792/*!
793* Following define size of mcu_2_shp_patched script
794*/
795#define mcu_2_shp_patched_SIZE_2 125
796
797/*!
798* Following define start address of per_2_shp script
799*/
800#define per_2_shp_ADDR_2 6890
801/*!
802* Following define size of per_2_shp script
803*/
804#define per_2_shp_SIZE_2 131
805
806/*!
807* Following define start address of shp_2_mcu_patched script
808*/
809#define shp_2_mcu_patched_ADDR_2 7021
810/*!
811* Following define size of shp_2_mcu_patched script
812*/
813#define shp_2_mcu_patched_SIZE_2 104
814
815/*!
816* Following define start address of shp_2_per script
817*/
818#define shp_2_per_ADDR_2 7125
819/*!
820* Following define size of shp_2_per script
821*/
822#define shp_2_per_SIZE_2 106
823/*!
824* Following define start address of uart_2_mcu_patched script
825*/
826#define uart_2_mcu_patched_ADDR_2 7231
827/*!
828* Following define size of uart_2_mcu_patched script
829*/
830#define uart_2_mcu_patched_SIZE_2 106
831
832/*!
833* Following define start address of uartsh_2_mcu_patched script
834*/
835#define uartsh_2_mcu_patched_ADDR_2 7337
836/*!
837* Following define size of uartsh_2_mcu_patched script
838*/
839#define uartsh_2_mcu_patched_SIZE_2 99
840
841/*!
842* Following define the start address of sdma ram
843*/
844
845#define RAM_CODE_START_ADDR_2 6144
846/*!
847* Following define the size of sdma ram
848*/
849#define RAM_CODE_SIZE_2 1292
850
851/*!
852 * Code download for i.MX system revision > 1.0
853 */
854static __attribute__((aligned(4))) const short sdma_code_2[RAM_CODE_SIZE_2] =
855{
856 0x0870, 0x0011, 0x5010, 0xc0ec, 0x7d61, 0x5ac0, 0x5bc8, 0x5ef8,
857 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9806, 0x6ec3, 0x6d07, 0x5df0,
858 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d45, 0x0b70, 0x0311,
859 0x522b, 0x5313, 0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f3b, 0x0400,
860 0x9816, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x0a03, 0x0212,
861 0x02bc, 0x0210, 0x4a00, 0x7d1c, 0x4a02, 0x7d20, 0x4a01, 0x7d23,
862 0x0b70, 0x0311, 0x53eb, 0x62c8, 0x7e25, 0x0360, 0x7d02, 0x0210,
863 0x0212, 0x6a09, 0x7f1f, 0x0212, 0x6a09, 0x7f1c, 0x0212, 0x6a09,
864 0x7f19, 0x2003, 0x4800, 0x7cef, 0x0b70, 0x0311, 0x5313, 0x9857,
865 0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b, 0x9856, 0x0015, 0x7802,
866 0x62c8, 0x6a0a, 0x9856, 0x7802, 0x62c8, 0x6a09, 0x7c03, 0x6a28,
867 0x0000, 0x9814, 0xc77b, 0x6a28, 0x7ffd, 0x0870, 0x0011, 0x5010,
868 0x52c0, 0x53c8, 0xc10d, 0x7da2, 0x0200, 0x9806, 0x0200, 0x9803,
869 0xc19d, 0xc0ec, 0x7d69, 0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c,
870 0x58da, 0x5efa, 0xc0fe, 0x56fa, 0x7d02, 0x0200, 0x9871, 0x6d07,
871 0x5bca, 0x5cd2, 0x0bff, 0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da,
872 0x4c00, 0x7d47, 0x0a70, 0x0211, 0x552a, 0x5212, 0x008d, 0x00bb,
873 0x4800, 0x7c07, 0x05b9, 0x4d00, 0x7c13, 0x6928, 0x7f2d, 0x0400,
874 0x9882, 0x008f, 0x0015, 0x04d8, 0x7d01, 0x008c, 0x04a0, 0x0015,
875 0x7802, 0x55c6, 0x6d0b, 0x7e29, 0x6d28, 0x7f1e, 0x0000, 0x9880,
876 0x1e20, 0x5506, 0x2620, 0x008d, 0x0560, 0x7c08, 0x065f, 0x55c6,
877 0x063f, 0x7e1b, 0x6d0a, 0x7f10, 0x4c00, 0x7d1b, 0x04d8, 0x7d02,
878 0x008c, 0x0020, 0x04a0, 0x0015, 0x7802, 0x55c6, 0x6d0b, 0x7e0d,
879 0x6d28, 0x7f02, 0x0000, 0x98c9, 0x0007, 0x680c, 0x6d0c, 0x6507,
880 0x6d07, 0x6d2b, 0x6d28, 0x0007, 0x680c, 0x0007, 0x54d2, 0x0454,
881 0x98cc, 0x6928, 0x7ff1, 0x54d2, 0x008a, 0x52c0, 0x53c8, 0xc10d,
882 0x0288, 0x7d9f, 0x0200, 0x9871, 0x0200, 0x9869, 0x1e10, 0x0870,
883 0x0011, 0x5010, 0xc0ec, 0x7d39, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe,
884 0x56f8, 0x7d02, 0x0200, 0x98dd, 0x6d07, 0x5df0, 0x0dff, 0x0511,
885 0x1dff, 0x05bc, 0x4d00, 0x7d17, 0x6ec3, 0x62c8, 0x7e28, 0x0264,
886 0x7d08, 0x0b70, 0x0311, 0x522b, 0x02b9, 0x4a00, 0x7c18, 0x0400,
887 0x98ec, 0x0212, 0x3aff, 0x008a, 0x05d8, 0x7d01, 0x008d, 0x0a10,
888 0x6ed3, 0x6ac8, 0xd927, 0x6a28, 0x7f17, 0x0b70, 0x0311, 0x5013,
889 0xd93f, 0x52c0, 0x53c8, 0xc10d, 0x7dd0, 0x0200, 0x98dd, 0x008f,
890 0x00d5, 0x7d01, 0x008d, 0xd927, 0x98ea, 0x0200, 0x98da, 0x0007,
891 0x68cc, 0x6a28, 0x7f01, 0x9925, 0x0007, 0x6a0c, 0x6a0c, 0x6207,
892 0x6a07, 0x6a2b, 0x6a28, 0x0007, 0x680c, 0x0454, 0x9903, 0x05a0,
893 0x1e08, 0x6ec3, 0x0388, 0x3b03, 0x0015, 0x0015, 0x7802, 0x62c8,
894 0x6a0b, 0x7ee5, 0x6a28, 0x7fe8, 0x0000, 0x6ec1, 0x008b, 0x7802,
895 0x62c8, 0x6a09, 0x7edc, 0x6a28, 0x7fdf, 0x2608, 0x0006, 0x55f0,
896 0x6207, 0x02a5, 0x0dff, 0x0511, 0x1dff, 0x04b5, 0x049a, 0x0006,
897 0x0870, 0x0011, 0x5010, 0xc0ec, 0x7d7a, 0x5ac0, 0x5bc8, 0x5ef8,
898 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x994e, 0x6d03, 0x6ed3, 0x0dff,
899 0x0511, 0x1dff, 0x05bc, 0x5df8, 0x4d00, 0x7d5e, 0x0b70, 0x0311,
900 0x522b, 0x5313, 0x02b9, 0x4a00, 0x7c04, 0x62ff, 0x7e3f, 0x0400,
901 0x995e, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5ddb, 0x0d03,
902 0x0512, 0x05bc, 0x0510, 0x5dd3, 0x4d00, 0x7d27, 0x4d02, 0x7d20,
903 0x4d01, 0x7d1a, 0x0b70, 0x0311, 0x53eb, 0x0360, 0x7d05, 0x6509,
904 0x7e25, 0x620a, 0x7e23, 0x9988, 0x620a, 0x7e20, 0x6509, 0x7e1e,
905 0x0512, 0x0512, 0x02ad, 0x6ac8, 0x7f19, 0x2003, 0x4800, 0x7ced,
906 0x0b70, 0x0311, 0x5313, 0x99a3, 0x7802, 0x6209, 0x6ac8, 0x99a2,
907 0x0015, 0x7802, 0x620a, 0x6ac8, 0x99a2, 0x0015, 0x0015, 0x7802,
908 0x620b, 0x6ac8, 0x7c03, 0x0000, 0x55db, 0x995c, 0x0007, 0x68cc,
909 0x680c, 0x55d3, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x99b1, 0x0017,
910 0x0017, 0x55db, 0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff,
911 0x0010, 0x04b8, 0x04ad, 0x0454, 0x62ff, 0x7ee8, 0x0870, 0x0011,
912 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7d89, 0x0200, 0x994e, 0x0200,
913 0x994b, 0xc19d, 0xc0ec, 0x7d52, 0x0c70, 0x0411, 0x5414, 0x5ac4,
914 0x028c, 0x58da, 0x5efa, 0xc0fe, 0x56fa, 0x7d02, 0x0200, 0x99d2,
915 0x6d03, 0x5bca, 0x5cd2, 0x0bff, 0x0311, 0x1bff, 0x04bb, 0x0415,
916 0x53da, 0x0a70, 0x0211, 0x4c00, 0x7d28, 0x552a, 0x05bb, 0x4d00,
917 0x7c02, 0x0400, 0x99e5, 0x4c01, 0x7d0f, 0x008f, 0x0015, 0x04d8,
918 0x7d01, 0x008c, 0x0020, 0x04a0, 0x0015, 0x7802, 0x650b, 0x5d06,
919 0x0000, 0x7e0c, 0x7f0d, 0x99e3, 0x650a, 0x7e08, 0x008d, 0x0011,
920 0x0010, 0x05a8, 0x065f, 0x5d06, 0x063f, 0x7f02, 0x0007, 0x680c,
921 0x0007, 0x5012, 0x54d0, 0x0454, 0x9a0f, 0x5012, 0x54d0, 0x0473,
922 0x7c06, 0x552a, 0x05b9, 0x4d00, 0x7c02, 0x0400, 0x9a11, 0x52c0,
923 0x53c8, 0xc10d, 0x0288, 0x7db6, 0x0200, 0x99d2, 0x0200, 0x99ca,
924 0x0870, 0x0011, 0x5010, 0xc0ec, 0x7d46, 0x5ac0, 0x5bc8, 0x5ef8,
925 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9a26, 0x0b70, 0x0311, 0x6ed3,
926 0x6d03, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d2b, 0x522b,
927 0x02b9, 0x4a00, 0x7c04, 0x62c8, 0x7e1f, 0x0400, 0x9a37, 0x008f,
928 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x0060, 0x7c05, 0x6edd, 0x6209,
929 0x7e16, 0x6ac8, 0x7f11, 0x0015, 0x0060, 0x7c05, 0x6ede, 0x620a,
930 0x7e0e, 0x6ac8, 0x7f09, 0x6edf, 0x0015, 0x7802, 0x620b, 0x6ac8,
931 0x0000, 0x7e05, 0x7f01, 0x9a35, 0x0007, 0x68cc, 0x9a61, 0x0007,
932 0x6a0c, 0x0454, 0x62c8, 0x7ef8, 0x5013, 0x52c0, 0x53c8, 0xc10d,
933 0x7dbd, 0x0200, 0x9a26, 0x0200, 0x9a23, 0xc19d, 0x0870, 0x0011,
934 0xc0ec, 0x7d76, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8,
935 0x7d02, 0x0200, 0x9a74, 0x6d03, 0x0d03, 0x0512, 0x05bc, 0x0510,
936 0x5dd0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x5df8, 0x4d00, 0x7d57,
937 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c02, 0x0400,
938 0x9a88, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x5dda, 0x55d2,
939 0x4d00, 0x7d27, 0x4d02, 0x7d20, 0x4d01, 0x7d1a, 0x0a70, 0x0211,
940 0x52ea, 0x0260, 0x7d05, 0x6509, 0x7e25, 0x630a, 0x7e23, 0x9aac,
941 0x630a, 0x7e20, 0x6509, 0x7e1e, 0x0512, 0x0512, 0x03ad, 0x5b06,
942 0x7f19, 0x2003, 0x4800, 0x7ced, 0x0a70, 0x0211, 0x5212, 0x9ac7,
943 0x7802, 0x6309, 0x5b06, 0x9ac6, 0x0015, 0x7802, 0x630a, 0x5b06,
944 0x9ac6, 0x0015, 0x0015, 0x7802, 0x630b, 0x5b06, 0x7c03, 0x55da,
945 0x0000, 0x9a86, 0x0007, 0x680c, 0x55d2, 0x4d00, 0x7d03, 0x4d02,
946 0x7d02, 0x9ad4, 0x0017, 0x0017, 0x55da, 0x009d, 0x55fa, 0x05a0,
947 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8, 0x04ad, 0x0454, 0x0870,
948 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7d8e, 0x0200, 0x9a74,
949 0x0200, 0x9a70, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d7c, 0x5010,
950 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9af1,
951 0x6dc5, 0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd0, 0x0dff, 0x0511,
952 0x1dff, 0x05bc, 0x5df8, 0x4d00, 0x7d5d, 0x0a70, 0x0211, 0x532a,
953 0x5212, 0x03b9, 0x4b00, 0x7c02, 0x0400, 0x9b05, 0x008f, 0x05d8,
954 0x7d01, 0x008d, 0x05a0, 0x5dda, 0x55d2, 0x4d00, 0x7d2c, 0x4d02,
955 0x7d24, 0x4d01, 0x7d1e, 0x59e2, 0x0a70, 0x0211, 0x52ea, 0x61c8,
956 0x7e2c, 0x63c8, 0x7e2a, 0x65c8, 0x7e28, 0x0260, 0x7d03, 0x0112,
957 0x0112, 0x9b2c, 0x0512, 0x0512, 0x0311, 0x03a9, 0x03ad, 0x5b06,
958 0x7f1c, 0x2003, 0x4800, 0x7ceb, 0x0a70, 0x0211, 0x5212, 0x51e2,
959 0x9b4a, 0x7802, 0x63c8, 0x5b06, 0x9b49, 0x6dce, 0x0015, 0x7802,
960 0x63c8, 0x5b06, 0x9b49, 0x6dcf, 0x0015, 0x0015, 0x7802, 0x63c8,
961 0x5b06, 0x7c03, 0x55da, 0x0000, 0x9b03, 0x0007, 0x68ff, 0x55d2,
962 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9b57, 0x0017, 0x0017, 0x55da,
963 0x009d, 0x55fa, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8,
964 0x04ad, 0x0454, 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d,
965 0x7d88, 0x0200, 0x9af1, 0x0200, 0x9aed, 0xc19d, 0x0870, 0x0011,
966 0xc0ec, 0x7d61, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8,
967 0x7d02, 0x0200, 0x9b74, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff,
968 0x05bc, 0x4d00, 0x7d45, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9,
969 0x4b00, 0x7c04, 0x6a28, 0x7f3b, 0x0400, 0x9b83, 0x008f, 0x05d8,
970 0x7d01, 0x008d, 0x05a0, 0x0b03, 0x0312, 0x03bc, 0x0310, 0x4b00,
971 0x7d1c, 0x4b02, 0x7d20, 0x4b01, 0x7d23, 0x0a70, 0x0211, 0x52ea,
972 0x5306, 0x7e25, 0x0260, 0x7d02, 0x0310, 0x0312, 0x6b09, 0x7f1f,
973 0x0312, 0x6b09, 0x7f1c, 0x0312, 0x6b09, 0x7f19, 0x2003, 0x4800,
974 0x7cef, 0x0a70, 0x0211, 0x5212, 0x9bc4, 0x0015, 0x0015, 0x7802,
975 0x5306, 0x6b0b, 0x9bc3, 0x0015, 0x7802, 0x5306, 0x6b0a, 0x9bc3,
976 0x7802, 0x5306, 0x6b09, 0x7c03, 0x6b28, 0x0000, 0x9b81, 0xc77b,
977 0x6928, 0x7ffd, 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d,
978 0x7da3, 0x0200, 0x9b74, 0x0200, 0x9b70, 0xc19d, 0x0870, 0x0011,
979 0xc0ec, 0x7d63, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8,
980 0x7d02, 0x0200, 0x9bdc, 0x6dd7, 0x5df0, 0x0dff, 0x0511, 0x1dff,
981 0x05bc, 0x4d00, 0x7d47, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9,
982 0x4b00, 0x7c04, 0x63c8, 0x7e3d, 0x0400, 0x9beb, 0x008f, 0x05d8,
983 0x7d01, 0x008d, 0x05a0, 0x0b03, 0x0312, 0x03bc, 0x0310, 0x4b00,
984 0x7d28, 0x4b02, 0x7d20, 0x4b01, 0x7d19, 0x6ddd, 0x0a70, 0x0211,
985 0x52ea, 0x5306, 0x7e26, 0x0260, 0x7d02, 0x0310, 0x0312, 0x6bc8,
986 0x7f20, 0x0312, 0x6bc8, 0x7f1d, 0x0312, 0x6bc8, 0x7f1a, 0x2003,
987 0x4800, 0x7cef, 0x0a70, 0x0211, 0x5212, 0x9c2f, 0x6ddd, 0x7802,
988 0x5306, 0x6bc8, 0x9c2e, 0x6dde, 0x0015, 0x7802, 0x5306, 0x6bc8,
989 0x9c2e, 0x0015, 0x0015, 0x7802, 0x5306, 0x6bc8, 0x7c02, 0x0000,
990 0x9be9, 0xc777, 0x63c8, 0x7efd, 0x0870, 0x0011, 0x5010, 0x52c0,
991 0x53c8, 0xc10d, 0x7da1, 0x0200, 0x9bdc, 0x0200, 0x9bd8, 0x0870,
992 0x0011, 0x5010, 0xc0ec, 0x7d5c, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe,
993 0x56f8, 0x7d02, 0x0200, 0x9c45, 0x0b70, 0x0311, 0x6ec3, 0x6d07,
994 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d3e, 0x522b,
995 0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f34, 0x0400, 0x9c57, 0x028e,
996 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1b, 0x1e94, 0x6ec3, 0x6ed3,
997 0x62c8, 0x0248, 0x6ac8, 0x2694, 0x6ec3, 0x62c8, 0x026e, 0x7d32,
998 0x6a09, 0x7f1f, 0x2501, 0x4d00, 0x7d20, 0x028e, 0x1a98, 0x6ac3,
999 0x62c8, 0x6ec3, 0x0260, 0x7df1, 0x6a28, 0x7f13, 0xc7af, 0x9c97,
1000 0x6ee3, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8,
1001 0x026e, 0x7d18, 0x6a09, 0x7f05, 0x2001, 0x7cf9, 0x6a28, 0x0000,
1002 0x9c55, 0x0289, 0xc77b, 0x018a, 0x9ca6, 0x6a28, 0x7ffa, 0x0b70,
1003 0x0311, 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7da7, 0x0200, 0x9c45,
1004 0x0200, 0x9c42, 0x6a28, 0x7fed, 0xc7af, 0x9ca6, 0x0458, 0x0454,
1005 0x9c97, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d55, 0x5010, 0x5ac0,
1006 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9cb0, 0x0b70,
1007 0x0311, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00,
1008 0x7d37, 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f2d, 0x0400,
1009 0x9cc1, 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d16, 0x1e94, 0x5206,
1010 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d2f, 0x6a09, 0x7f1c,
1011 0x2501, 0x4d00, 0x7d1d, 0x028e, 0x1a98, 0x5202, 0x0260, 0x7df3,
1012 0x6a28, 0x7f12, 0xc7af, 0x9cfa, 0x008f, 0x2001, 0x00d5, 0x7d01,
1013 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d18, 0x6a09, 0x7f05, 0x2001,
1014 0x7cf9, 0x6a28, 0x0000, 0x9cbf, 0x0289, 0xc77b, 0x018a, 0x9d09,
1015 0x6928, 0x7ffa, 0x0b70, 0x0311, 0x5013, 0x52c0, 0x53c8, 0xc10d,
1016 0x7daf, 0x0200, 0x9cb0, 0x0200, 0x9cac, 0x6a28, 0x7fed, 0xc7af,
1017 0x9d09, 0x0458, 0x0454, 0x9cfa
1018};
1019
1020/*!
1021 * Structure containing script addresses.
1022 */
1023struct sdma_script_start_addrs
1024{
1025 /* SDMA code script info - in halfword SDMA memory space */
1026 unsigned short ap_2_ap_addr;
1027 unsigned short ap_2_bp_addr;
1028 unsigned short bp_2_ap_addr;
1029 unsigned short loopback_on_dsp_side_addr;
1030 unsigned short mcu_interrupt_only_addr;
1031 unsigned short firi_2_per_addr;
1032 unsigned short firi_2_mcu_addr;
1033 unsigned short per_2_firi_addr;
1034 unsigned short mcu_2_firi_addr;
1035 unsigned short uart_2_per_addr;
1036 unsigned short uart_2_mcu_addr;
1037 unsigned short per_2_app_addr;
1038 unsigned short mcu_2_app_addr;
1039 unsigned short uartsh_2_per_addr;
1040 unsigned short uartsh_2_mcu_addr;
1041 unsigned short per_2_shp_addr;
1042 unsigned short mcu_2_shp_addr;
1043 unsigned short ata_2_mcu_addr;
1044 unsigned short mcu_2_ata_addr;
1045 unsigned short app_2_per_addr;
1046 unsigned short app_2_mcu_addr;
1047 unsigned short shp_2_per_addr;
1048 unsigned short shp_2_mcu_addr;
1049 unsigned short mshc_2_mcu_addr;
1050 unsigned short mcu_2_mshc_addr;
1051 unsigned short dptc_dvfs_addr;
1052 /* SDMA script code info */
1053 /* address where ram code starts (in SDMA halfword space) */
1054 unsigned short ram_code_start_addr;
1055 /* size of the ram code (in halfwords) */
1056 unsigned short ram_code_size;
1057 /* RAM image address on AP */
1058 unsigned long mcu_start_addr;
1059};
1060#endif /*__SDMA_SCRIPT_CODE_H__ */
diff --git a/firmware/target/arm/imx31/sdma_struct.h b/firmware/target/arm/imx31/sdma_struct.h
new file mode 100644
index 0000000000..22aabcbdb4
--- /dev/null
+++ b/firmware/target/arm/imx31/sdma_struct.h
@@ -0,0 +1,426 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Michael Sevakis
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22/* Largely taken from sdmaStruct.h from the Linux BSP provided by Freescale.
23 * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
24 */
25
26/* Other information gleaned from RE-ing the BSP and SDMA code */
27
28#ifndef SDMA_STRUCT_H
29#define SDMA_STRUCT_H
30
31/**
32 * Number of channels
33 */
34#define CH_NUM 32
35
36/**
37 * Ownership
38 */
39#define CH_OWNSHP_EVT (1 << 0)
40#define CH_OWNSHP_MCU (1 << 1)
41#if 0
42#define CH_OWNSHP_DSP (1 << 2)
43#endif
44
45/**
46 * Channel contexts management
47 */
48
49/* Contexts for each channel begin here within SDMA core */
50#define CHANNEL_CONTEXT_BASE_ADDR 0x800
51/* Compute SDMA address where context for a channel is stored */
52#define CHANNEL_CONTEXT_ADDR(channel) \
53 (CHANNEL_CONTEXT_BASE_ADDR+sizeof(struct context_data)/4*(channel))
54
55/**
56 * Error bit set in the CCB status field by the SDMA,
57 * in setbd routine, in case of a transfer error
58 */
59#define DATA_ERROR (1 << 28) /* BD_RROR set on last buffer descriptor */
60#define DATA_FAULT (1 << 29) /* A source or destination fault occured */
61
62/**
63 * Buffer descriptor status values.
64 */
65#define BD_DONE 0x01 /* Set by host, cleared when SDMA has finished with
66 this BD */
67#define BD_WRAP 0x02 /* If set in last descriptor, allows circular buffer
68 * structure. curr_bd_ptr will be reset to base_bd_ptr
69 */
70#define BD_CONT 0x04 /* If set, more descriptors follow (multi-buffer) */
71#define BD_INTR 0x08 /* Interrupt when transfer complete */
72#define BD_RROR 0x10 /* Error during BD processing (set by SDMA) */
73#define BD_LAST 0x20 /* Set by SDMA ap_2_bp and bp_2_ap scripts.
74 TODO: determine function */
75#define BD_EXTD 0x80 /* Use extended buffer address (indicates BD is 12
76 bytes instead of 8) */
77
78/**
79 * Buffer descriptor channel 0 commands.
80 */
81#define C0_SETCTX 0x07 /* Write context for a channel (ch# = BD command [7:3]) */
82#define C0_GETCTX 0x03 /* Read context for a channel (ch# = BD command [7:3]) */
83#define C0_SETDM 0x01 /* Write 32-bit words to SDMA memory */
84#define C0_GETDM 0x02 /* Read 32-bit words from SDMA memory */
85#define C0_SETPM 0x04 /* Write 16-bit halfwords to SDMA memory */
86#define C0_GETPM 0x08 /* Read 16-bit halfwords from SDMA memory */
87
88/* Treated the same as those above */
89#define C0_ADDR 0x01
90#define C0_LOAD 0x02
91#define C0_DUMP 0x03
92
93/**
94 * Transfer sizes, encoded in the BD command field (when not a C0_ command).
95 */
96#define TRANSFER_32BIT 0x00
97#define TRANSFER_8BIT 0x01
98#define TRANSFER_16BIT 0x02
99#define TRANSFER_24BIT 0x03
100
101/**
102 * Change endianness indicator in the BD command field
103 */
104#define CHANGE_ENDIANNESS 0x80
105
106/**
107 * Size in bytes of struct buffer_descriptor
108 */
109#define SDMA_BD_SIZE 8
110#define SDMA_EXTENDED_BD_SIZE 12
111#define BD_NUMBER 4
112
113/**
114 * Channel interrupt policy
115 */
116#define DEFAULT_POLL 0
117#define CALLBACK_ISR 1
118/**
119 * Channel status
120 */
121#define UNINITIALIZED 0
122#define INITIALIZED 1
123
124/**
125 * IoCtl particular values
126 */
127#define SET_BIT_ALL 0xFFFFFFFF
128#define BD_NUM_OFFSET 16
129#define BD_NUM_MASK 0xFFFF0000
130
131/**
132 * Maximum values for IoCtl calls, used in high or middle level calls
133 */
134#define MAX_BD_NUM 256
135#define MAX_BD_SIZE 65536
136#define MAX_BLOCKING 2
137#define MAX_SYNCH 2
138#define MAX_OWNERSHIP 8
139#define MAX_CH_PRIORITY 8
140#define MAX_TRUST 2
141#define MAX_WML 256
142
143
144/**
145 * Default values for channel descriptor - nobody owns the channel
146 */
147#define CD_DEFAULT_OWNERSHIP 7
148
149#if 0 /* IPC not used */
150/**
151 * Data Node descriptor status values.
152 */
153#define DND_END_OF_FRAME 0x80
154#define DND_END_OF_XFER 0x40
155#define DND_DONE 0x20
156#define DND_UNUSED 0x01
157
158/**
159 * IPCV2 descriptor status values.
160 */
161#define BD_IPCV2_END_OF_FRAME 0x40
162
163#define IPCV2_MAX_NODES 50
164
165/**
166 * User Type Section
167 */
168
169/**
170 * Command/Mode/Count of buffer descriptors
171 */
172struct mode_count_ipcv2
173{
174 unsigned long count : 16; /* size of the buffer pointed by this BD */
175 unsigned long reserved : 8; /* reserved */
176 unsigned long status : 8; /* L, E, D bits stored here */
177};
178
179/**
180 * Data Node descriptor - IPCv2
181 * (differentiated between evolutions of SDMA)
182 */
183struct data_node_descriptor
184{
185 struct mode_count_ipcv2 mode; /* command, status and count */
186 void* buffer_addr; /* address of the buffer described */
187};
188
189struct mode_count_ipcv1_v2
190{
191 unsigned long count : 16; /* size of the buffer pointed by this BD */
192 unsigned long status : 8; /* E,R,I,C,W,D status bits stored here */
193 unsigned long reserved : 7;
194 unsigned long endianness : 1;
195};
196
197/**
198 * Buffer descriptor
199 * (differentiated between evolutions of SDMA)
200 */
201struct buffer_descriptor_ipcv1_v2
202{
203 struct mode_count_ipcv1_v2 mode; /* command, status and count */
204 void *buffer_addr; /* address of the buffer described */
205 void *ext_buffer_addr; /* extended buffer address */
206};
207#endif /* No IPC */
208
209/**
210 * Mode/Count of data node descriptors - IPCv2
211 */
212struct mode_count
213{
214 unsigned long count : 16; /* size of the buffer pointed by this BD */
215 unsigned long status : 8; /* E,R,I,C,W,D status bits stored here:
216 * SDMA r/w */
217 unsigned long command : 8; /* channel 0 command or transfer size */
218};
219
220
221/**
222 * Buffer descriptor - describes each buffer in a DMA transfer.
223 * (differentiated between evolutions of SDMA)
224 */
225/* (mode.status & BD_EXTD) == 0 (8 bytes) */
226struct buffer_descriptor
227{
228 volatile struct mode_count mode; /* command, status and count: SDMA r/w */
229 void *buf_addr; /* address of the buffer described: SDMA r */
230};
231
232/* (mode.status & BD_EXTD) != 0 (12 bytes) */
233struct buffer_descriptor_extd
234{
235 struct buffer_descriptor bd;
236 void *buf_addr_ext; /* extended buffer address described (r6): SDMA r */
237};
238
239#if 0 /* A different one is defined for Rockbox use - this has too much.
240 * See below. */
241struct channel_control_block;
242struct channel_descriptor;
243/**
244 * Channel Descriptor
245 */
246struct channel_descriptor
247{
248 unsigned char channel_number; /* stores the channel number */
249 unsigned char buffer_desc_count; /* number of BD's allocated
250 for this channel */
251 unsigned short buffer_per_desc_size; /* size (in bytes) of buffer
252 descriptors' data buffers */
253 unsigned long blocking : 3; /* polling/ callback method
254 selection */
255 unsigned long callback_synch : 1; /* (iapi) blocking / non blocking
256 feature selection */
257 unsigned long ownership : 3; /* ownership of the channel
258 (host+dedicated+event) */
259 unsigned long priority : 3; /* reflects the SDMA channel
260 priority register */
261 unsigned long trust : 1; /* trusted buffers or kernel
262 allocated */
263 unsigned long use_data_size : 1; /* (iapi) indicates if the dataSize
264 field is meaningfull */
265 unsigned long data_size : 2; /* (iapi->BD) data transfer
266 size - 8,16,24 or 32 bits*/
267 unsigned long force_close : 1; /* If TRUE, close channel even
268 with BD owned by SDMA*/
269 unsigned long script_id : 7; /* number of the script */
270 unsigned long watermark_level : 10; /* (greg) Watermark level for the
271 peripheral access */
272 unsigned long event_mask1; /* (greg) First Event mask */
273 unsigned long event_mask2; /* (greg) Second Event mask */
274 unsigned long shp_addr; /* (greg) Address of the peripheral
275 or its fifo when needed */
276 void (* callback)(struct channel_descriptor *); /* pointer to the
277 callback function (or NULL) */
278 struct channel_control_block *ccb_ptr; /* pointer to the channel control
279 block associated to this
280 channel */
281};
282#endif
283
284/* Only what we need, members sorted by size, no code-bloating bitfields */
285struct channel_descriptor
286{
287 unsigned int bd_count; /* number of BD's allocated
288 for this channel */
289 struct channel_control_block *ccb_ptr; /* pointer to the channel control
290 block associated to this
291 channel */
292 void (* callback)(void); /* pointer to the
293 callback function (or NULL) */
294 unsigned long shp_addr; /* (greg) Address of the peripheral
295 or its fifo when needed */
296 unsigned short wml; /* (greg) Watermark level for the
297 peripheral access */
298 unsigned char per_type; /* Peripheral type */
299 unsigned char tran_type; /* Transfer type */
300 unsigned char event_id1; /* DMA request ID */
301 unsigned char event_id2; /* DMA request ID 2 */
302 unsigned char is_setup; /* Channel setup has been done */
303};
304
305/**
306 * Channel Status
307 */
308struct channel_status
309{
310 unsigned long unused : 28;
311 unsigned long error : 1; /* Last BD triggered an error:
312 SDMA r/w */
313 unsigned long opened_init : 1; /* Channel is initialized:
314 SDMA r/w */
315 unsigned long state_direction : 1; /* SDMA is reading/writing (as seen
316 from channel owner core) */
317 unsigned long execute : 1; /* Channel is being processed
318 (started) or not */
319};
320
321/**
322 * Channel control Block
323 * SDMA ROM code expects these are 16-bytes each in an array
324 * (MC0PTR + 16*CCR)
325 */
326struct channel_control_block
327{
328 /* current buffer descriptor processed: SDMA r/w */
329 struct buffer_descriptor * volatile curr_bd_ptr;
330 /* first element of buffer descriptor array: SDMA r */
331 struct buffer_descriptor *base_bd_ptr;
332 /* pointer to the channel descriptor: SDMA ignored */
333 struct channel_descriptor *channel_desc;
334 /* open/close ; started/stopped ; read/write: SDMA r/w */
335 volatile struct channel_status status;
336};
337
338/**
339 * Channel context structure.
340 */
341
342/* Channel state bits on SDMA core side */
343struct state_registers
344{
345 /* Offset 0 */
346 unsigned long pc : 14; /* program counter */
347 unsigned long unused0 : 1;
348 unsigned long t : 1; /* test bit: status of arithmetic & test
349 instruction */
350 unsigned long rpc : 14; /* return program counter */
351 unsigned long unused1 : 1;
352 unsigned long sf : 1; /* source fault while loading data */
353 /* Offset 1 */
354 unsigned long spc : 14; /* loop start program counter */
355 unsigned long unused2 : 1;
356 unsigned long df : 1; /* destination falut while storing data */
357 unsigned long epc : 14; /* loop end program counter */
358 unsigned long lm : 2; /* loop mode */
359};
360
361/* Context data saved for every channel on the SDMA core. This is 32 words
362 * long which is specified in the SDMA initialization on the AP side. The
363 * SDMA scripts utilize the scratch space. */
364struct context_data
365{
366 struct state_registers channel_state; /* channel state bits */
367 union
368 {
369 unsigned long r[8]; /* general registers (r0-r7) */
370 struct /* script usage of said when
371 setting contexts */
372 {
373 unsigned long event_mask2; /* 08h */
374 unsigned long event_mask1; /* 0Ch */
375 unsigned long r2; /* 10h */
376 unsigned long r3; /* 14h */
377 unsigned long r4; /* 18h */
378 unsigned long r5; /* 1Ch */
379 unsigned long shp_addr; /* 20h */
380 unsigned long wml; /* 24h */
381 };
382 };
383 unsigned long mda; /* burst dma destination address register */
384 unsigned long msa; /* burst dma source address register */
385 unsigned long ms; /* burst dma status register */
386 unsigned long md; /* burst dma data register */
387 unsigned long pda; /* peripheral dma destination address register */
388 unsigned long psa; /* peripheral dma source address register */
389 unsigned long ps; /* peripheral dma status register */
390 unsigned long pd; /* peripheral dma data register */
391 unsigned long ca; /* CRC polynomial register */
392 unsigned long cs; /* CRC accumulator register */
393 unsigned long dda; /* dedicated core destination address register */
394 unsigned long dsa; /* dedicated core source address register */
395 unsigned long ds; /* dedicated core status register */
396 unsigned long dd; /* dedicated core data register */
397 unsigned long scratch[8]; /* channel context scratch RAM */
398};
399
400/**
401 * This structure holds the necessary data for the assignment in the
402 * dynamic channel-script association
403 */
404struct script_data
405{
406 unsigned long load_address; /* start address of the script */
407 unsigned long wml; /* parameters for the channel descriptor */
408 unsigned long shp_addr; /* shared peripheral base address */
409 unsigned long event_mask1; /* first event mask */
410 unsigned long event_mask2; /* second event mask */
411};
412
413/**
414 * This structure holds the the useful bits of the CONFIG register
415 */
416struct configs_data
417{
418 unsigned long dspdma : 1; /* indicates if the DSPDMA is used */
419 unsigned long rtdobs : 1; /* indicates if Real-Time Debug pins are
420 enabled */
421 unsigned long acr : 1; /* indicates if AHB freq /core freq = 2 or 1 */
422 unsigned long csm : 2; /* indicates which context switch mode is
423 selected */
424};
425
426#endif /* SDMA_STRUCT_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-04 23:55:47 +0000