diff options
Diffstat (limited to 'firmware/export/imx31l.h')
-rwxr-xr-x | firmware/export/imx31l.h | 151 |
1 files changed, 151 insertions, 0 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index e31f30f1b0..cdae29f158 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -118,6 +118,22 @@ | |||
118 | #define WDOG1_BASE_ADDR WDOG_BASE_ADDR | 118 | #define WDOG1_BASE_ADDR WDOG_BASE_ADDR |
119 | #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR | 119 | #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR |
120 | 120 | ||
121 | /* IIM */ | ||
122 | #define IIM_PREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x20)) | ||
123 | #define IIM_PREV_SIG (0x1f << 3) | ||
124 | #define IIM_PREV_SIG_IMX31 (0x01 << 3) /* i.MX31 */ | ||
125 | #define IIM_SREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x24)) | ||
126 | #define IIM_SREV_SREV (0xff << 0) | ||
127 | #define IIM_SREV_1_0 0x00 /* i.MX31/L 1.0, L38W */ | ||
128 | #define IIM_SREV_1_1 0x10 /* i.MX31 1.1, 2L38W */ | ||
129 | #define IIM_SREV_1_1L 0x11 /* i.MX31L 1.1, 2L38W */ | ||
130 | #define IIM_SREV_1_15 0x12 /* i.MX31 1.15, 2L38W/3L38W */ | ||
131 | #define IIM_SREV_1_15L 0x13 /* i.MX31L 1.15, 2L38W/3L38W */ | ||
132 | #define IIM_SREV_1_2 0x14 /* i.MX31 1.2, 3L38W, M45G */ | ||
133 | #define IIM_SREV_1_2L 0x15 /* i.MX31L 1.2, 3L38W, M45G */ | ||
134 | #define IIM_SREV_2_0_1 0x28 /* i.MX31 2.0/2.0.1, M91E */ | ||
135 | #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */ | ||
136 | |||
121 | /* IOMUXC */ | 137 | /* IOMUXC */ |
122 | #define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o))) | 138 | #define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o))) |
123 | 139 | ||
@@ -1618,6 +1634,141 @@ | |||
1618 | #define EUARTUTS_RXFULL (1 << 3) // RxFIFO full | 1634 | #define EUARTUTS_RXFULL (1 << 3) // RxFIFO full |
1619 | #define EUARTUTS_SOFTRST (1 << 0) // Software reset | 1635 | #define EUARTUTS_SOFTRST (1 << 0) // Software reset |
1620 | 1636 | ||
1637 | /* SDMA */ | ||
1638 | #define SDMA_MC0PTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x000)) | ||
1639 | #define SDMA_INTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x004)) | ||
1640 | #define SDMA_STOP_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x008)) | ||
1641 | #define SDMA_HSTART (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x00C)) | ||
1642 | #define SDMA_EVTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x010)) | ||
1643 | #define SDMA_DSPOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x014)) | ||
1644 | #define SDMA_HOSTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x018)) | ||
1645 | #define SDMA_EVTPEND (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x01C)) | ||
1646 | #define SDMA_DSPENBL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x020)) | ||
1647 | #define SDMA_RESET (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x024)) | ||
1648 | #define SDMA_EVTERR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x028)) | ||
1649 | #define SDMA_INTRMSK (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x02C)) | ||
1650 | #define SDMA_PSW (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x030)) | ||
1651 | #define SDMA_EVTERRDBG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x034)) | ||
1652 | #define SDMA_CONFIG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x038)) | ||
1653 | #define SDMA_ONCE_ENB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x040)) | ||
1654 | #define SDMA_ONCE_DATA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x044)) | ||
1655 | #define SDMA_ONCE_INSTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x048)) | ||
1656 | #define SDMA_ONCE_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x04C)) | ||
1657 | #define SDMA_ONCE_CMD (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x050)) | ||
1658 | #define SDMA_EVT_MIRROR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x054)) | ||
1659 | #define SDMA_ILLINSTADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x058)) | ||
1660 | #define SDMA_CHN0ADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x05C)) | ||
1661 | #define SDMA_ONCE_RTB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x060)) | ||
1662 | #define SDMA_XTRIG_CONF1 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x070)) | ||
1663 | #define SDMA_XTRIG_CONF2 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x074)) | ||
1664 | |||
1665 | /* SDMA_CHNENBL: 0x080 - 0x0FC */ | ||
1666 | #define SDMA_CHNENBL(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x080))[n]) /* 0..31 */ | ||
1667 | |||
1668 | /* SDMA_CHNPRI: 0x100 - 0x17C */ | ||
1669 | #define SDMA_CHNPRI(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x100))[n]) /* 0..31 */ | ||
1670 | |||
1671 | #define SDMA_ONCE_COUNT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x200)) | ||
1672 | #define SDMA_ONCE_ECTL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x204)) | ||
1673 | #define SDMA_ONCE_EAA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x208)) | ||
1674 | #define SDMA_ONCE_EAB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x20C)) | ||
1675 | #define SDMA_ONCE_EAM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x210)) | ||
1676 | #define SDMA_ONCE_ED (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x214)) | ||
1677 | #define SDMA_ONCE_EDM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x218)) | ||
1678 | #define SDMA_ONCE_PCMATCH (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x21C)) | ||
1679 | |||
1680 | /* SDMA_RESET */ | ||
1681 | #define SDMA_RESET_RESCHED (0x1 << 1) | ||
1682 | #define SDMA_RESET_RESET (0x1 << 0) | ||
1683 | |||
1684 | /* SDMA_PSW */ | ||
1685 | #define SDMA_PSW_NCP (0x7 << 13) | ||
1686 | #define SDMA_PSW_NCR (0x1f << 8) | ||
1687 | #define SDMA_PSW_CCP (0x7 << 5) | ||
1688 | #define SDMA_PSW_CCR (0x1f << 0) | ||
1689 | |||
1690 | /* SDMA_CONFIG */ | ||
1691 | #define SDMA_CONFIG_DSPDMA (0x1 << 12) | ||
1692 | #define SDMA_CONFIG_RTDOBS (0x1 << 11) | ||
1693 | #define SDMA_CONFIG_ACR (0x1 << 4) | ||
1694 | #define SDMA_CONFIG_CSM (0x3 << 0) | ||
1695 | #define SDMA_CONFIG_CSM_STATIC (0x0 << 0) | ||
1696 | #define SDMA_CONFIG_CSM_DYNAMIC_LOW_POWER (0x1 << 0) | ||
1697 | #define SDMA_CONFIG_CSM_DYNAMIC_NO_LOOP (0x2 << 0) | ||
1698 | #define SDMA_CONFIG_CSM_DYNAMIC (0x3 << 0) | ||
1699 | |||
1700 | /* SDMA_ONCE_ENB */ | ||
1701 | #define SDMA_ONCE_ENB_ENB (0x1 << 0) | ||
1702 | |||
1703 | /* SDMA_ONCE_STAT */ | ||
1704 | #define SDMA_ONCE_STAT_PST (0xf << 12) | ||
1705 | #define SDMA_ONCE_STAT_PST_PROGRAM (0x0 << 12) | ||
1706 | #define SDMA_ONCE_STAT_PST_DATA (0x1 << 12) | ||
1707 | #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW (0x2 << 12) | ||
1708 | #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP (0x3 << 12) | ||
1709 | #define SDMA_ONCE_STAT_PST_DEBUG (0x4 << 12) | ||
1710 | #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT (0x5 << 12) | ||
1711 | #define SDMA_ONCE_STAT_PST_SLEEP (0x6 << 12) | ||
1712 | #define SDMA_ONCE_STAT_PST_SAVE (0x7 << 12) | ||
1713 | #define SDMA_ONCE_STAT_PST_PROGRAM_IN_SLEEP (0x8 << 12) | ||
1714 | #define SDMA_ONCE_STAT_PST_DATA_IN_SLEEP (0x9 << 12) | ||
1715 | #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_SLEEP (0xa << 12) | ||
1716 | #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP_IN_SLEEP (0xb << 12) | ||
1717 | #define SDMA_ONCE_STAT_PST_DEBUG_IN_SLEEP (0xc << 12) | ||
1718 | #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT_IN_SLEEP (0xd << 12) | ||
1719 | #define SDMA_ONCE_STAT_PST_SLEEP_AFTER_RESET (0xe << 12) | ||
1720 | #define SDMA_ONCE_STAT_PST_RESTORE (0xf << 12) | ||
1721 | #define SDMA_ONCE_STAT_RCV (0x1 << 11) | ||
1722 | #define SDMA_ONCE_STAT_EDR (0x1 << 10) | ||
1723 | #define SDMA_ONCE_STAT_ODR (0x1 << 9) | ||
1724 | #define SDMA_ONCE_STAT_SWB (0x1 << 8) | ||
1725 | #define SDMA_ONCE_STAT_MST (0x1 << 7) | ||
1726 | #define SDMA_ONCE_STAT_ECDR (0x7 << 0) | ||
1727 | #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRA_COND (0x1 << 0) | ||
1728 | #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRB_COND (0x1 << 1) | ||
1729 | #define SDMA_ONCE_STAT_ECDR_MATCHED_DATA_COND (0x1 << 2) | ||
1730 | |||
1731 | /* SDMA_ONCE_CMD */ | ||
1732 | #define SDMA_ONCE_CMD_RSTATUS 0x0 | ||
1733 | #define SDMA_ONCE_CMD_DMOV 0x1 | ||
1734 | #define SDMA_ONCE_CMD_EXEC_ONCE 0x2 | ||
1735 | #define SDMA_ONCE_CMD_RUN_CORE 0x3 | ||
1736 | #define SDMA_ONCE_CMD_EXEC_CORE 0x4 | ||
1737 | #define SDMA_ONCE_CMD_DEBUG_RQST 0x5 | ||
1738 | #define SDMA_ONCE_CMD_RBUFFER 0x6 | ||
1739 | /* 7-15 reserved */ | ||
1740 | |||
1741 | /* SDMA_CHN0ADDR */ | ||
1742 | #define SDMA_CHN0ADDR_SMSZ (0x1 << 14) | ||
1743 | /* 13:0 = 0x0050 by default (std. boot code) */ | ||
1744 | |||
1745 | /* SDMA_EVT_MIRROR */ | ||
1746 | #define SDMA_EVT_MIRROR_EVENTS(n) (0x1 << (n)) | ||
1747 | |||
1748 | /* SDMA_XTRIG_CONF1 */ | ||
1749 | #define SDMA_XTRIG_CONF1_CNF3 (0x1 << 30) | ||
1750 | #define SDMA_XTRIG_CONF1_NUM3 (0x1f << 24) | ||
1751 | #define SDMA_XTRIG_CONF1_CNF2 (0x1 << 22) | ||
1752 | #define SDMA_XTRIG_CONF1_NUM2 (0x1f << 16) | ||
1753 | #define SDMA_XTRIG_CONF1_CNF1 (0x1 << 14) | ||
1754 | #define SDMA_XTRIG_CONF1_NUM1 (0x1f << 8) | ||
1755 | #define SDMA_XTRIG_CONF1_CNF0 (0x1 << 6) | ||
1756 | #define SDMA_XTRIG_CONF1_NUM0 (0x1f << 0) | ||
1757 | |||
1758 | /* SDMA_XTRIG_CONF2 */ | ||
1759 | #define SDMA_XTRIG_CONF2_CNF7 (0x1 << 30) | ||
1760 | #define SDMA_XTRIG_CONF2_NUM7 (0x1f << 24) | ||
1761 | #define SDMA_XTRIG_CONF2_CNF6 (0x1 << 22) | ||
1762 | #define SDMA_XTRIG_CONF2_NUM6 (0x1f << 16) | ||
1763 | #define SDMA_XTRIG_CONF2_CNF5 (0x1 << 14) | ||
1764 | #define SDMA_XTRIG_CONF2_NUM5 (0x1f << 8) | ||
1765 | #define SDMA_XTRIG_CONF2_CNF4 (0x1 << 6) | ||
1766 | #define SDMA_XTRIG_CONF2_NUM4 (0x1f << 0) | ||
1767 | |||
1768 | /* SDMA_CHNENBL(n) */ | ||
1769 | #define SDMA_CHNENBL_ENBL(n) (0x1 << (n)) | ||
1770 | |||
1771 | |||
1621 | #define L2CC_ENABLED | 1772 | #define L2CC_ENABLED |
1622 | 1773 | ||
1623 | /* Assuming 26MHz input clock */ | 1774 | /* Assuming 26MHz input clock */ |