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authorMarcoen Hirschberg <marcoen@gmail.com>2008-06-27 23:24:34 +0000
committerMarcoen Hirschberg <marcoen@gmail.com>2008-06-27 23:24:34 +0000
commit7b10ef9a7c55764d1b6815fd0871cb51ff0205f9 (patch)
tree0b2056ef0334e45107b02118040baae49d51b142
parent5c763f4001c1634ea62ded26339df52494e6c718 (diff)
downloadrockbox-7b10ef9a7c55764d1b6815fd0871cb51ff0205f9.tar.gz
rockbox-7b10ef9a7c55764d1b6815fd0871cb51ff0205f9.zip
initial Meizu M6SL port (take 2)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17819 a1c6a512-1295-4272-9138-f99709370657
Diffstat
-rw-r--r--apps/SOURCES2
-rw-r--r--apps/keymaps/keymap-meizu-m6sl.c303
-rw-r--r--bootloader/SOURCES2
-rw-r--r--bootloader/meizu_m6sl.c84
-rw-r--r--firmware/SOURCES12
-rw-r--r--firmware/drivers/tuner/tea5760uk.c135
-rw-r--r--firmware/export/config-meizu-m6sl.h173
-rw-r--r--firmware/export/config.h15
-rw-r--r--firmware/export/cpu.h3
-rw-r--r--firmware/export/s5l8700.h567
-rw-r--r--firmware/export/system.h2
-rw-r--r--firmware/system.c6
-rw-r--r--firmware/target/arm/s5l8700/ata-nand-s5l8700.c94
-rw-r--r--firmware/target/arm/s5l8700/boot.lds54
-rw-r--r--firmware/target/arm/s5l8700/crt0.S117
-rw-r--r--firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h33
-rw-r--r--firmware/target/arm/s5l8700/meizu-m6sl/backlight-target.h27
-rw-r--r--firmware/target/arm/s5l8700/meizu-m6sl/button-target.h52
-rw-r--r--firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c133
-rw-r--r--firmware/target/arm/s5l8700/system-s5l8700.c168
-rw-r--r--firmware/target/arm/s5l8700/system-target.h35
-rwxr-xr-xtools/configure35
-rw-r--r--tools/makesrc.inc3
-rwxr-xr-xtools/rockboxdev.sh4
-rw-r--r--uisimulator/sdl/button.c29
-rw-r--r--uisimulator/sdl/uisdl.h13
26 files changed, 2092 insertions, 9 deletions
diff --git a/apps/SOURCES b/apps/SOURCES
index 01d31210e6..e70e32b73d 100644
--- a/apps/SOURCES
+++ b/apps/SOURCES
@@ -187,6 +187,8 @@ keymaps/keymap-mr500.c
187keymaps/keymap-mr100.c 187keymaps/keymap-mr100.c
188#elif CONFIG_KEYPAD == COWOND2_PAD 188#elif CONFIG_KEYPAD == COWOND2_PAD
189keymaps/keymap-cowond2.c 189keymaps/keymap-cowond2.c
190#elif CONFIG_KEYPAD == MEIZU_M6SL_PAD
191keymaps/keymap-meizu-m6sl.c
190#elif CONFIG_KEYPAD == CREATIVEZVM_PAD 192#elif CONFIG_KEYPAD == CREATIVEZVM_PAD
191keymaps/keymap-creativezvm.c 193keymaps/keymap-creativezvm.c
192#elif CONFIG_KEYPAD == CREATIVEZV_PAD 194#elif CONFIG_KEYPAD == CREATIVEZV_PAD
diff --git a/apps/keymaps/keymap-meizu-m6sl.c b/apps/keymaps/keymap-meizu-m6sl.c
new file mode 100644
index 0000000000..a473c88311
--- /dev/null
+++ b/apps/keymaps/keymap-meizu-m6sl.c
@@ -0,0 +1,303 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 Jonathan Gordon
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20/* Button Code Definitions for the toshiba gigabeat target */
21#include <stdio.h>
22#include <string.h>
23#include <stdlib.h>
24
25#include "config.h"
26#include "action.h"
27#include "button.h"
28#include "settings.h"
29
30/*
31 * The format of the list is as follows
32 * { Action Code, Button code, Prereq button code }
33 * if there's no need to check the previous button's value, use BUTTON_NONE
34 * Insert LAST_ITEM_IN_LIST at the end of each mapping
35 */
36
37/* CONTEXT_CUSTOM's used in this file...
38
39CONTEXT_CUSTOM|CONTEXT_TREE = the standard list/tree defines (without directions)
40CONTEXT_CUSTOM|CONTEXT_SETTINGS = the direction keys for the eq/col picker screens
41 i.e where up/down is inc/dec
42 CONTEXT_SETTINGS = up/down is prev/next, l/r is inc/dec
43
44*/
45
46
47static const struct button_mapping button_context_standard[] = {
48 { ACTION_STD_PREV, BUTTON_UP, BUTTON_NONE },
49 { ACTION_STD_PREVREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
50 { ACTION_STD_NEXT, BUTTON_DOWN, BUTTON_NONE },
51 { ACTION_STD_NEXTREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
52
53 { ACTION_STD_CANCEL, BUTTON_LEFT, BUTTON_NONE },
54
55 { ACTION_STD_CONTEXT, BUTTON_SELECT|BUTTON_REPEAT,BUTTON_SELECT },
56
57 { ACTION_STD_QUICKSCREEN, BUTTON_MENU|BUTTON_REPEAT, BUTTON_MENU },
58 { ACTION_STD_MENU, BUTTON_MENU|BUTTON_REL, BUTTON_MENU },
59
60 { ACTION_STD_OK, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT },
61 { ACTION_STD_OK, BUTTON_RIGHT, BUTTON_NONE },
62
63 LAST_ITEM_IN_LIST
64}; /* button_context_standard */
65
66
67static const struct button_mapping button_context_wps[] = {
68 { ACTION_WPS_PLAY, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY },
69 { ACTION_WPS_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE },
70
71 { ACTION_WPS_SKIPNEXT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT },
72 { ACTION_WPS_SKIPPREV, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT },
73
74 { ACTION_WPS_SEEKBACK, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
75 { ACTION_WPS_SEEKFWD, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
76 { ACTION_WPS_STOPSEEK, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT|BUTTON_REPEAT },
77 { ACTION_WPS_STOPSEEK, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT|BUTTON_REPEAT },
78
79 { ACTION_WPS_ABSETB_NEXTDIR, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_NONE },
80 { ACTION_WPS_ABSETA_PREVDIR, BUTTON_PLAY|BUTTON_LEFT, BUTTON_NONE },
81 { ACTION_WPS_ABRESET, BUTTON_PLAY|BUTTON_SELECT, BUTTON_NONE },
82
83 { ACTION_WPS_VOLDOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
84 { ACTION_WPS_VOLDOWN, BUTTON_DOWN, BUTTON_NONE },
85 { ACTION_WPS_VOLUP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
86 { ACTION_WPS_VOLUP, BUTTON_UP, BUTTON_NONE },
87
88 { ACTION_WPS_PITCHSCREEN, BUTTON_PLAY|BUTTON_UP, BUTTON_PLAY },
89 { ACTION_WPS_PITCHSCREEN, BUTTON_PLAY|BUTTON_DOWN, BUTTON_PLAY },
90
91 { ACTION_WPS_QUICKSCREEN, BUTTON_MENU|BUTTON_REPEAT, BUTTON_MENU },
92 { ACTION_WPS_MENU, BUTTON_MENU|BUTTON_REL, BUTTON_MENU },
93 { ACTION_WPS_CONTEXT, BUTTON_SELECT|BUTTON_REPEAT, BUTTON_SELECT },
94
95 { ACTION_WPS_ID3SCREEN, BUTTON_PLAY|BUTTON_MENU, BUTTON_NONE },
96 { ACTION_WPS_BROWSE, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT },
97
98 LAST_ITEM_IN_LIST
99}; /* button_context_wps */
100
101static const struct button_mapping button_context_list[] = {
102 { ACTION_LISTTREE_PGUP, BUTTON_PLAY|BUTTON_UP, BUTTON_PLAY },
103 { ACTION_LISTTREE_PGUP, BUTTON_UP|BUTTON_REL, BUTTON_PLAY|BUTTON_UP },
104 { ACTION_LISTTREE_PGUP, BUTTON_PLAY|BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
105 { ACTION_LISTTREE_PGDOWN, BUTTON_PLAY|BUTTON_DOWN, BUTTON_PLAY },
106 { ACTION_LISTTREE_PGDOWN, BUTTON_DOWN|BUTTON_REL, BUTTON_PLAY|BUTTON_DOWN },
107 { ACTION_LISTTREE_PGDOWN, BUTTON_PLAY|BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
108
109 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
110}; /* button_context_list */
111
112static const struct button_mapping button_context_tree[] = {
113 { ACTION_TREE_WPS, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY },
114 { ACTION_TREE_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE },
115
116 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST)
117}; /* button_context_tree */
118
119static const struct button_mapping button_context_listtree_scroll_with_combo[] = {
120 { ACTION_NONE, BUTTON_PLAY, BUTTON_NONE },
121 { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_PLAY },
122 { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REL, BUTTON_PLAY|BUTTON_LEFT },
123 { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_LEFT|BUTTON_REL },
124 { ACTION_TREE_ROOT_INIT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_PLAY|BUTTON_LEFT },
125 { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
126 { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_PLAY },
127 { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REL, BUTTON_PLAY|BUTTON_RIGHT },
128 { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_RIGHT|BUTTON_REL },
129 { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
130 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE),
131};
132
133static const struct button_mapping button_context_listtree_scroll_without_combo[] = {
134 { ACTION_NONE, BUTTON_LEFT, BUTTON_NONE },
135 { ACTION_STD_CANCEL, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT },
136 { ACTION_TREE_ROOT_INIT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_LEFT },
137 { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
138 { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT|BUTTON_REPEAT },
139 { ACTION_NONE, BUTTON_RIGHT, BUTTON_NONE },
140 { ACTION_STD_OK, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT },
141 { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
142 { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT|BUTTON_REPEAT },
143 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE),
144};
145
146static const struct button_mapping button_context_settings[] = {
147 { ACTION_SETTINGS_INC, BUTTON_UP, BUTTON_NONE },
148 { ACTION_SETTINGS_INCREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
149 { ACTION_SETTINGS_DEC, BUTTON_DOWN, BUTTON_NONE },
150 { ACTION_SETTINGS_DECREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
151 { ACTION_STD_PREV, BUTTON_LEFT, BUTTON_NONE },
152 { ACTION_STD_PREVREPEAT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
153 { ACTION_STD_NEXT, BUTTON_RIGHT, BUTTON_NONE },
154 { ACTION_STD_NEXTREPEAT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
155 { ACTION_SETTINGS_RESET, BUTTON_PLAY, BUTTON_NONE },
156
157 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
158}; /* button_context_settings */
159
160static const struct button_mapping button_context_settings_right_is_inc[] = {
161 { ACTION_SETTINGS_INC, BUTTON_RIGHT, BUTTON_NONE },
162 { ACTION_SETTINGS_INCREPEAT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
163 { ACTION_SETTINGS_DEC, BUTTON_LEFT, BUTTON_NONE },
164 { ACTION_SETTINGS_DECREPEAT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
165 { ACTION_STD_PREV, BUTTON_UP, BUTTON_NONE },
166 { ACTION_STD_PREVREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
167 { ACTION_STD_NEXT, BUTTON_DOWN, BUTTON_NONE },
168 { ACTION_STD_NEXTREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
169 { ACTION_SETTINGS_RESET, BUTTON_PLAY, BUTTON_NONE },
170
171 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
172}; /* button_context_settingsgraphical */
173
174static const struct button_mapping button_context_yesno[] = {
175 { ACTION_YESNO_ACCEPT, BUTTON_SELECT, BUTTON_NONE },
176 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
177}; /* button_context_settings_yesno */
178
179static const struct button_mapping button_context_colorchooser[] = {
180 { ACTION_STD_OK, BUTTON_PLAY|BUTTON_REL, BUTTON_NONE },
181 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS),
182}; /* button_context_colorchooser */
183
184static const struct button_mapping button_context_eq[] = {
185 { ACTION_STD_OK, BUTTON_SELECT|BUTTON_REL, BUTTON_NONE },
186 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS),
187}; /* button_context_eq */
188
189/** Bookmark Screen **/
190static const struct button_mapping button_context_bmark[] = {
191 { ACTION_BMS_DELETE, BUTTON_PLAY, BUTTON_NONE },
192
193 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST),
194}; /* button_context_bmark */
195
196static const struct button_mapping button_context_time[] = {
197 { ACTION_STD_CANCEL, BUTTON_LEFT, BUTTON_NONE },
198 { ACTION_STD_OK, BUTTON_PLAY, BUTTON_NONE },
199 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_SETTINGS),
200}; /* button_context_time */
201
202static const struct button_mapping button_context_quickscreen[] = {
203 { ACTION_QS_DOWNINV, BUTTON_UP, BUTTON_NONE },
204 { ACTION_QS_DOWNINV, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
205 { ACTION_QS_DOWN, BUTTON_DOWN, BUTTON_NONE },
206 { ACTION_QS_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
207 { ACTION_QS_LEFT, BUTTON_LEFT, BUTTON_NONE },
208 { ACTION_QS_LEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
209 { ACTION_QS_RIGHT, BUTTON_RIGHT, BUTTON_NONE },
210 { ACTION_QS_RIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
211 { ACTION_STD_CANCEL, BUTTON_MENU, BUTTON_NONE },
212
213 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
214}; /* button_context_quickscreen */
215
216static const struct button_mapping button_context_pitchscreen[] = {
217 { ACTION_PS_INC_SMALL, BUTTON_UP, BUTTON_NONE },
218 { ACTION_PS_INC_BIG, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
219 { ACTION_PS_DEC_SMALL, BUTTON_DOWN, BUTTON_NONE },
220 { ACTION_PS_DEC_BIG, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
221 { ACTION_PS_NUDGE_LEFT, BUTTON_LEFT, BUTTON_NONE },
222 { ACTION_PS_NUDGE_LEFTOFF, BUTTON_LEFT|BUTTON_REL, BUTTON_NONE },
223 { ACTION_PS_NUDGE_RIGHT, BUTTON_RIGHT, BUTTON_NONE },
224 { ACTION_PS_NUDGE_RIGHTOFF, BUTTON_RIGHT|BUTTON_REL, BUTTON_NONE },
225 { ACTION_PS_TOGGLE_MODE, BUTTON_MENU, BUTTON_NONE },
226 { ACTION_PS_RESET, BUTTON_PLAY, BUTTON_NONE },
227 { ACTION_PS_EXIT, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE },
228
229 LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
230}; /* button_context_pitchcreen */
231
232static const struct button_mapping button_context_keyboard[] = {
233 { ACTION_KBD_LEFT, BUTTON_LEFT, BUTTON_NONE },
234 { ACTION_KBD_LEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
235 { ACTION_KBD_RIGHT, BUTTON_RIGHT, BUTTON_NONE },
236 { ACTION_KBD_RIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
237 { ACTION_KBD_CURSOR_LEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_NONE },
238 { ACTION_KBD_CURSOR_LEFT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
239 { ACTION_KBD_CURSOR_RIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_NONE },
240 { ACTION_KBD_CURSOR_RIGHT, BUTTON_PLAY|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
241 { ACTION_KBD_SELECT, BUTTON_SELECT, BUTTON_NONE },
242 { ACTION_KBD_PAGE_FLIP, BUTTON_PLAY|BUTTON_MENU, BUTTON_NONE },
243 { ACTION_KBD_DONE, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY },
244 { ACTION_KBD_ABORT, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE },
245 { ACTION_KBD_BACKSPACE, BUTTON_MENU, BUTTON_NONE },
246 { ACTION_KBD_BACKSPACE, BUTTON_MENU|BUTTON_REPEAT, BUTTON_NONE },
247 { ACTION_KBD_UP, BUTTON_UP, BUTTON_NONE },
248 { ACTION_KBD_UP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
249 { ACTION_KBD_DOWN, BUTTON_DOWN, BUTTON_NONE },
250 { ACTION_KBD_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
251// { ACTION_KBD_MORSE_INPUT, BUTTON_PLAY|BUTTON_POWER, BUTTON_NONE },
252 { ACTION_KBD_MORSE_SELECT, BUTTON_SELECT|BUTTON_REL, BUTTON_NONE },
253
254 LAST_ITEM_IN_LIST
255}; /* button_context_keyboard */
256
257
258const struct button_mapping* get_context_mapping(int context)
259{
260 switch (context)
261 {
262 case CONTEXT_STD:
263 return button_context_standard;
264 case CONTEXT_WPS:
265 return button_context_wps;
266
267 case CONTEXT_LIST:
268 return button_context_list;
269 case CONTEXT_MAINMENU:
270 case CONTEXT_TREE:
271 if (global_settings.hold_lr_for_scroll_in_list)
272 return button_context_listtree_scroll_without_combo;
273 else
274 return button_context_listtree_scroll_with_combo;
275 case CONTEXT_CUSTOM|CONTEXT_TREE:
276 return button_context_tree;
277
278 case CONTEXT_SETTINGS:
279 return button_context_settings;
280 case CONTEXT_CUSTOM|CONTEXT_SETTINGS:
281 return button_context_settings_right_is_inc;
282
283 case CONTEXT_SETTINGS_COLOURCHOOSER:
284 return button_context_colorchooser;
285 case CONTEXT_SETTINGS_EQ:
286 return button_context_eq;
287
288 case CONTEXT_SETTINGS_TIME:
289 return button_context_time;
290
291 case CONTEXT_YESNOSCREEN:
292 return button_context_yesno;
293 case CONTEXT_BOOKMARKSCREEN:
294 return button_context_bmark;
295 case CONTEXT_QUICKSCREEN:
296 return button_context_quickscreen;
297 case CONTEXT_PITCHSCREEN:
298 return button_context_pitchscreen;
299 case CONTEXT_KEYBOARD:
300 return button_context_keyboard;
301 }
302 return button_context_standard;
303}
diff --git a/bootloader/SOURCES b/bootloader/SOURCES
index 37011dd700..19e40e2fc3 100644
--- a/bootloader/SOURCES
+++ b/bootloader/SOURCES
@@ -29,4 +29,6 @@ iriver_h300.c
29mrobe500.c 29mrobe500.c
30#elif defined(CPU_TCC77X) || defined(CPU_TCC780X) 30#elif defined(CPU_TCC77X) || defined(CPU_TCC780X)
31telechips.c 31telechips.c
32#elif defined(MEIZU_M6SL)
33meizu_m6sl.c
32#endif 34#endif
diff --git a/bootloader/meizu_m6sl.c b/bootloader/meizu_m6sl.c
new file mode 100644
index 0000000000..3bafd79e34
--- /dev/null
+++ b/bootloader/meizu_m6sl.c
@@ -0,0 +1,84 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by Greg White
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#include "config.h"
20
21#include <stdlib.h>
22#include <stdio.h>
23#include "inttypes.h"
24#include "string.h"
25#include "cpu.h"
26#include "system.h"
27#include "lcd.h"
28#include "kernel.h"
29#include "thread.h"
30#include "ata.h"
31#include "fat.h"
32#include "disk.h"
33#include "font.h"
34#include "adc.h"
35#include "backlight.h"
36#include "backlight-target.h"
37#include "button.h"
38#include "panic.h"
39#include "power.h"
40#include "file.h"
41#include "common.h"
42#include "rbunicode.h"
43#include "usb.h"
44
45#include <stdarg.h>
46
47char version[] = APPSVERSION;
48
49void main(void)
50{
51 //Set backlight pin to output and enable
52 int oldval = PCON0;
53 PCON0 = ((oldval & ~(3 << 4)) | (1 << 4));
54 PDAT0 |= (1 << 2);
55
56 //Set PLAY to input
57 oldval = PCON1;
58 PCON1 = ((oldval & ~(0xf << 16)) | (0 << 16));
59
60 //Set the piezo pins to output
61 oldval = PCON5;
62 PCON5 = ((oldval & ~((0xf << 4) | (0xf << 8))) | ((1 << 0) | (1 << 4)));
63 PDAT5 &= ~((1 << 1) | (1 << 2)); //should not be needed
64
65 PDAT5 |= (1 << 1); //Toggle piezo +
66
67 //toggle backlight on PLAY
68 while(true)
69 {
70 // Wait for play to be pressed
71 while(!(PDAT1 & (1 << 4)))
72 {
73 }
74
75 PDAT5 ^= (1 << 1); //Toggle piezo +
76 PDAT0 ^= (1 << 2); //Toggle packlight
77
78 // Wait for play to be released
79 while(PDAT1 & (1 << 4))
80 {
81 }
82 }
83}
84
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 4dca1c1563..60adcbe59c 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -355,6 +355,8 @@ target/arm/tcc77x/crt0.S
355target/arm/tcc780x/crt0.S 355target/arm/tcc780x/crt0.S
356#elif CONFIG_CPU==IMX31L 356#elif CONFIG_CPU==IMX31L
357target/arm/imx31/crt0.S 357target/arm/imx31/crt0.S
358#elif CONFIG_CPU==S5L8700
359target/arm/s5l8700/crt0.S
358#elif defined(CPU_ARM) 360#elif defined(CPU_ARM)
359target/arm/crt0.S 361target/arm/crt0.S
360#endif /* defined(CPU_*) */ 362#endif /* defined(CPU_*) */
@@ -1042,3 +1044,13 @@ target/arm/tcc780x/cowond2/audio-cowond2.c
1042#endif /* BOOTLOADER */ 1044#endif /* BOOTLOADER */
1043#endif /* SIMULATOR */ 1045#endif /* SIMULATOR */
1044#endif /* COWON_D2 */ 1046#endif /* COWON_D2 */
1047
1048#ifdef MEIZU_M6SL
1049target/arm/s5l8700/system-s5l8700.c
1050target/arm/s5l8700/ata-nand-s5l8700.c
1051target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c
1052#ifndef SIMULATOR
1053#ifndef BOOTLOADER
1054#endif /* BOOTLOADER */
1055#endif /* SIMULATOR */
1056#endif /* MEIZU_M6SL */
diff --git a/firmware/drivers/tuner/tea5760uk.c b/firmware/drivers/tuner/tea5760uk.c
new file mode 100644
index 0000000000..8582358114
--- /dev/null
+++ b/firmware/drivers/tuner/tea5760uk.c
@@ -0,0 +1,135 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 * Tuner "middleware" for Philips TEA5760UK chip
10 *
11 * Copyright (C) 2004 Jörg Hohensohn
12 *
13 * All files in this archive are subject to the GNU General Public License.
14 * See the file COPYING in the source tree root for full license agreement.
15 *
16 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
17 * KIND, either express or implied.
18 *
19 ****************************************************************************/
20#include "config.h"
21#include <stdbool.h>
22#include <string.h>
23#include <stdlib.h>
24#include "kernel.h"
25#include "tuner.h" /* tuner abstraction interface */
26#include "fmradio.h"
27#include "fmradio_i2c.h" /* physical interface driver */
28
29#define I2C_ADR 0xC0
30static unsigned char write_bytes[7] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
31
32static void tea5760uk_set_clear(int byte, unsigned char bits, int set)
33{
34 write_bytes[byte] &= ~bits;
35 if (set)
36 write_bytes[byte] |= bits;
37}
38
39/* tuner abstraction layer: set something to the tuner */
40int tea5760uk_set(int setting, int value)
41{
42 switch(setting)
43 {
44 case RADIO_SLEEP:
45 /* init values */
46 write_bytes[0] |= (1<<7); /* mute */
47#if CONFIG_TUNER_XTAL == 32768
48 /* 32.768kHz, soft mute, stereo noise cancelling */
49 write_bytes[3] |= (1<<4) | (1<<3) | (1<<1);
50#else
51 /* soft mute, stereo noise cancelling */
52 write_bytes[3] |= (1<<3) | (1<<1);
53#endif
54 /* sleep / standby mode */
55 tea5760uk_set_clear(3, (1<<6), value);
56 break;
57
58 case RADIO_FREQUENCY:
59 {
60 int n;
61#if CONFIG_TUNER_XTAL == 32768
62 n = (4 * (value - 225000) + 16384) / 32768;
63#else
64 n = (4 * (value - 225000)) / 50000;
65#endif
66 write_bytes[6] = (write_bytes[6] & 0xC0) | (n >> 8);
67 write_bytes[7] = n;
68 }
69 break;
70
71 case RADIO_SCAN_FREQUENCY:
72 tea5760uk_set(RADIO_FREQUENCY, value);
73 sleep(HZ/30);
74 return tea5760uk_get(RADIO_TUNED);
75
76 case RADIO_MUTE:
77 tea5760uk_set_clear(3, (1<<2), value);
78 break;
79
80 case RADIO_REGION:
81 {
82 const struct tea5760uk_region_data *rd =
83 &tea5760uk_region_data[value];
84
85 tea5760uk_set_clear(4, (1<<1), rd->deemphasis);
86 tea5760uk_set_clear(3, (1<<5), rd->band);
87 break;
88 }
89 case RADIO_FORCE_MONO:
90 tea5760uk_set_clear(4, (1<<3), value);
91 break;
92 default:
93 return -1;
94 }
95
96 fmradio_i2c_write(I2C_ADR, write_bytes, sizeof(write_bytes));
97 return 1;
98}
99
100/* tuner abstraction layer: read something from the tuner */
101int tea5760uk_get(int setting)
102{
103 unsigned char read_bytes[16];
104 int val = -1; /* default for unsupported query */
105
106 fmradio_i2c_read(I2C_ADR, read_bytes, sizeof(read_bytes));
107
108 switch(setting)
109 {
110 case RADIO_PRESENT:
111 val = 1; /* true */
112 break;
113
114 case RADIO_TUNED:
115 val = 0;
116 if (read_bytes[0] & (1<<4)) /* IF count correct */
117 {
118 val = read_bytes[8] >> 1; /* IF counter */
119 val = (abs(val - 0x36) < 2); /* close match */
120 }
121 break;
122
123 case RADIO_STEREO:
124 val = read_bytes[9] >> 2;
125 break;
126 }
127
128 return val;
129}
130
131void tea5760uk_dbg_info(struct tea5760uk_dbg_info *info)
132{
133 fmradio_i2c_read(I2C_ADR, info->read_regs, 5);
134 memcpy(info->write_regs, write_bytes, 5);
135}
diff --git a/firmware/export/config-meizu-m6sl.h b/firmware/export/config-meizu-m6sl.h
new file mode 100644
index 0000000000..96c163ce11
--- /dev/null
+++ b/firmware/export/config-meizu-m6sl.h
@@ -0,0 +1,173 @@
1/*
2 * This config file is for iAudio X5
3 */
4#define TARGET_TREE /* this target is using the target tree system */
5
6/* For Rolo and boot loader */
7#define MODEL_NUMBER 1
8
9/* define this if you have recording possibility */
10//#define HAVE_RECORDING
11
12/* Define bitmask of input sources - recordable bitmask can be defined
13 explicitly if different */
14#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_FMRADIO)
15
16/* define the bitmask of hardware sample rates */
17#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
18
19/* define the bitmask of recording sample rates */
20#define REC_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
21
22/* define this if you have a bitmap LCD display */
23#define HAVE_LCD_BITMAP
24
25/* define this if you can flip your LCD */
26//#define HAVE_LCD_FLIP
27
28/* define this if you have a colour LCD */
29#define HAVE_LCD_COLOR
30
31/* define this if you want album art for this target */
32#define HAVE_ALBUMART
33
34/* define this if you can invert the colours on your LCD */
35//#define HAVE_LCD_INVERT
36
37/* define this if you have access to the quickscreen */
38#define HAVE_QUICKSCREEN
39
40/* define this if you have access to the pitchscreen */
41#define HAVE_PITCHSCREEN
42
43/* define this if you would like tagcache to build on this target */
44#define HAVE_TAGCACHE
45
46/* define this if you have a flash memory storage */
47#define HAVE_FLASH_STORAGE
48
49/* LCD dimensions */
50#define LCD_WIDTH 320
51#define LCD_HEIGHT 240
52#define LCD_DEPTH 16 /* pseudo 262.144 colors */
53#define LCD_PIXELFORMAT RGB565 /* rgb565 */
54
55/* Define this if your LCD can be enabled/disabled */
56//#define HAVE_LCD_ENABLE
57
58/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
59 should be defined as well. */
60//#define HAVE_LCD_SLEEP
61
62#define CONFIG_KEYPAD MEIZU_M6SL_PAD
63
64//#define AB_REPEAT_ENABLE 1
65//#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE
66
67/* Define this if you do software codec */
68#define CONFIG_CODEC SWCODEC
69
70/* define this if you have a real-time clock */
71#define CONFIG_RTC RTC_S5L8700
72//#define CONFIG_RTC RTC_S35390A
73
74#define CONFIG_LCD LCD_MEIZUM6
75
76/* Define this if you have the WM8975 audio codec */
77#define HAVE_WM8751 //FIXME
78
79/* Define this for LCD backlight available */
80#define HAVE_BACKLIGHT
81#define HAVE_BACKLIGHT_BRIGHTNESS
82
83/* Define this if you have a software controlled poweroff */
84#define HAVE_SW_POWEROFF
85
86/* The number of bytes reserved for loadable codecs */
87#define CODEC_SIZE 0x80000
88
89/* The number of bytes reserved for loadable plugins */
90#define PLUGIN_BUFFER_SIZE 0x80000
91
92/* FM Tuner */
93#define CONFIG_TUNER TEA5760
94#define CONFIG_TUNER_XTAL 32768
95
96//#define HAVE_TLV320
97
98/* TLV320 has no tone controls, so we use the software ones */
99#define HAVE_SW_TONE_CONTROLS
100
101#define BATTERY_CAPACITY_DEFAULT 700 /* default battery capacity */
102#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */
103#define BATTERY_CAPACITY_MAX 2250 /* max. capacity selectable */
104#define BATTERY_CAPACITY_INC 50 /* capacity increment */
105#define BATTERY_TYPES_COUNT 1 /* only one type */
106
107/* Hardware controlled charging? FIXME */
108#define CONFIG_CHARGING CHARGING_SIMPLE
109
110#ifndef SIMULATOR
111
112/* Define this if your LCD can set contrast */
113//#define HAVE_LCD_CONTRAST
114
115/* Define this if you have a Motorola SCF5250 */
116#define CONFIG_CPU S5L8700
117
118/* Define this if you want to use coldfire's i2c interface */
119#define CONFIG_I2C I2C_S5L8700
120
121/* define this if the hardware can be powered off while charging */
122#define HAVE_POWEROFF_WHILE_CHARGING
123
124/* The size of the flash ROM */
125#define FLASH_SIZE 0x400000
126
127/* Define this to the CPU frequency */
128#define CPU_FREQ 11289600
129
130/* Define this if you have ATA power-off control */
131//#define HAVE_ATA_POWER_OFF
132
133/* Virtual LED (icon) */
134#define CONFIG_LED LED_VIRTUAL
135
136/* Offset ( in the firmware file's header ) to the file CRC */
137#define FIRMWARE_OFFSET_FILE_CRC 0
138
139/* Offset ( in the firmware file's header ) to the real data */
140#define FIRMWARE_OFFSET_FILE_DATA 8
141
142/* USB On-the-go */
143//#define CONFIG_USBOTG USBOTG_M5636
144
145/* Define this if you have adjustable CPU frequency */
146#define HAVE_ADJUSTABLE_CPU_FREQ
147
148#define BOOTFILE_EXT "meizu"
149#define BOOTFILE "rockbox." BOOTFILE_EXT
150#define BOOTDIR "/.rockbox"
151
152#define BOOTLOADER_ENTRYPOINT 0x001F0000
153#define FLASH_ENTRYPOINT 0x00001000
154#define FLASH_MAGIC 0xfbfbfbf1
155
156#endif /* SIMULATOR */
157
158/* Define this for FM radio input available */
159#define HAVE_FMRADIO_IN
160
161/** Port-specific settings **/
162
163/* Main LCD contrast range and defaults */
164#define MIN_CONTRAST_SETTING 1
165#define MAX_CONTRAST_SETTING 30
166#define DEFAULT_CONTRAST_SETTING 19 /* Match boot contrast */
167
168/* Main LCD backlight brightness range and defaults */
169/* PCF50506 can output 0%-100% duty cycle but D305A expects %15-100%. */
170#define MIN_BRIGHTNESS_SETTING 1 /* 15/16 (93.75%) */
171#define MAX_BRIGHTNESS_SETTING 13 /* 3/16 (18.75%) */
172#define DEFAULT_BRIGHTNESS_SETTING 8 /* 8/16 (50.00%) = x5 boot default */
173
diff --git a/firmware/export/config.h b/firmware/export/config.h
index 1a6e5d6894..79d50bf533 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -31,6 +31,8 @@
31#define TEA5767 0x02 /* Philips */ 31#define TEA5767 0x02 /* Philips */
32#define LV24020LP 0x04 /* Sanyo */ 32#define LV24020LP 0x04 /* Sanyo */
33#define SI4700 0x08 /* Silicon Labs */ 33#define SI4700 0x08 /* Silicon Labs */
34#define TEA5760 0x10 /* Philips */
35#define LV240000 0x20 /* Sanyo */
34 36
35/* CONFIG_CODEC */ 37/* CONFIG_CODEC */
36#define MAS3587F 3587 38#define MAS3587F 3587
@@ -55,6 +57,7 @@
55#define TCC771L 771 57#define TCC771L 771
56#define TCC773L 773 58#define TCC773L 773
57#define TCC7801 7801 59#define TCC7801 7801
60#define S5L8700 8700
58 61
59/* CONFIG_KEYPAD */ 62/* CONFIG_KEYPAD */
60#define PLAYER_PAD 1 63#define PLAYER_PAD 1
@@ -86,6 +89,7 @@
86#define PHILIPS_SA9200_PAD 27 89#define PHILIPS_SA9200_PAD 27
87#define SANSA_C100_PAD 28 90#define SANSA_C100_PAD 28
88#define PHILIPS_HDD1630_PAD 29 91#define PHILIPS_HDD1630_PAD 29
92#define MEIZU_M6SL_PAD 30
89 93
90/* CONFIG_REMOTE_KEYPAD */ 94/* CONFIG_REMOTE_KEYPAD */
91#define H100_REMOTE 1 95#define H100_REMOTE 1
@@ -127,6 +131,7 @@
127#define LCD_SA9200 25 /* as used by the Philips SA9200 */ 131#define LCD_SA9200 25 /* as used by the Philips SA9200 */
128#define LCD_S6B33B2 26 /* as used by the Sansa c100 */ 132#define LCD_S6B33B2 26 /* as used by the Sansa c100 */
129#define LCD_HDD1630 27 /* as used by the Philips HDD1630 */ 133#define LCD_HDD1630 27 /* as used by the Philips HDD1630 */
134#define LCD_MEIZUM6 28 /* as used by the Meizu M6SP and M6SL (various models) */
130 135
131/* LCD_PIXELFORMAT */ 136/* LCD_PIXELFORMAT */
132#define HORIZONTAL_PACKING 1 137#define HORIZONTAL_PACKING 1
@@ -154,6 +159,7 @@
154#define I2C_TCC77X 10 159#define I2C_TCC77X 10
155#define I2C_TCC780X 11 160#define I2C_TCC780X 11
156#define I2C_DM320 12 /* DM320 style */ 161#define I2C_DM320 12 /* DM320 style */
162#define I2C_S5L8700 12
157 163
158/* CONFIG_LED */ 164/* CONFIG_LED */
159#define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */ 165#define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */
@@ -177,6 +183,8 @@
177#define RTC_TCC780X 11 183#define RTC_TCC780X 11
178#define RTC_MR100 12 184#define RTC_MR100 12
179#define RTC_MC13783 13 /* Freescale MC13783 PMIC */ 185#define RTC_MC13783 13 /* Freescale MC13783 PMIC */
186#define RTC_S5L8700 14
187#define RTC_S35390A 15
180 188
181/* USB On-the-go */ 189/* USB On-the-go */
182#define USBOTG_ISP1362 1362 /* iriver H300 */ 190#define USBOTG_ISP1362 1362 /* iriver H300 */
@@ -271,6 +279,8 @@
271#include "config-hdd1630.h" 279#include "config-hdd1630.h"
272#elif defined(SANSA_C100) 280#elif defined(SANSA_C100)
273#include "config-c100.h" 281#include "config-c100.h"
282#elif defined(MEIZU_M6SL)
283#include "config-meizu-m6sl.h"
274#else 284#else
275/* no known platform */ 285/* no known platform */
276#endif 286#endif
@@ -426,7 +436,7 @@
426#endif 436#endif
427 437
428#if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \ 438#if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \
429 || (CONFIG_CPU == DSC25) 439 || (CONFIG_CPU == DSC25) || (CONFIG_CPU == S5L8700)
430#define CPU_ARM 440#define CPU_ARM
431#define ARM_ARCH 4 /* ARMv4 */ 441#define ARM_ARCH 4 /* ARMv4 */
432#endif 442#endif
@@ -454,7 +464,8 @@
454 defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \ 464 defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \
455 defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \ 465 defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \
456 defined(CPU_TCC77X) || /* Telechips: core, plugins, codecs */ \ 466 defined(CPU_TCC77X) || /* Telechips: core, plugins, codecs */ \
457 (CONFIG_CPU == PNX0101)) 467 (CONFIG_CPU == PNX0101) || \
468 (CONFIG_CPU == S5L8700)) /* Samsing S5L8700: core, plugins, codecs */
458#define ICODE_ATTR __attribute__ ((section(".icode"))) 469#define ICODE_ATTR __attribute__ ((section(".icode")))
459#define ICONST_ATTR __attribute__ ((section(".irodata"))) 470#define ICONST_ATTR __attribute__ ((section(".irodata")))
460#define IDATA_ATTR __attribute__ ((section(".idata"))) 471#define IDATA_ATTR __attribute__ ((section(".idata")))
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index 08a91a6d10..ec08812404 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -54,3 +54,6 @@
54#ifdef CPU_TCC780X 54#ifdef CPU_TCC780X
55#include "tcc780x.h" 55#include "tcc780x.h"
56#endif 56#endif
57#if CONFIG_CPU == S5L8700
58#include "s5l8700.h"
59#endif
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
new file mode 100644
index 0000000000..211564e153
--- /dev/null
+++ b/firmware/export/s5l8700.h
@@ -0,0 +1,567 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: S5L8700X.h 2008-03-27 Marcoen Hirschberg, Bart van Adrichem $
9 *
10 * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#define REG8_PTR_T volatile uint8_t *
21#define REG16_PTR_T volatile uint16_t *
22#define REG32_PTR_T volatile uint32_t *
23
24/* 04. CALMADM2E */
25
26/* Following registers are mapped on IO Area in data memory area of Calm. */
27#define CONFIG0 (*(REG16_PTR_T)(0x3F000000)) /* configuration/control register 0 */
28#define CONFIG1 (*(REG16_PTR_T)(0x3F000002)) /* configuration/control register 1*/
29#define COMMUN (*(REG16_PTR_T)(0x3F000004)) /* Communication Control Register */
30#define DDATA0 (*(REG16_PTR_T)(0x3F000006)) /* Communication data from host to ADM */
31#define DDATA1 (*(REG16_PTR_T)(0x3F000008)) /* Communication data from host to ADM */
32#define DDATA2 (*(REG16_PTR_T)(0x3F00000A)) /* Communication data from host to ADM */
33#define DDATA3 (*(REG16_PTR_T)(0x3F00000C)) /* Communication data from host to ADM */
34#define DDATA4 (*(REG16_PTR_T)(0x3F00000E)) /* Communication data from host to ADM */
35#define DDATA5 (*(REG16_PTR_T)(0x3F000010)) /* Communication data from host to ADM */
36#define DDATA6 (*(REG16_PTR_T)(0x3F000012)) /* Communication data from host to ADM */
37#define DDATA7 (*(REG16_PTR_T)(0x3F000014)) /* Communication data from host to ADM */
38#define UDATA0 (*(REG16_PTR_T)(0x3F000016)) /* Communication data from ADM to host */
39#define UDATA1 (*(REG16_PTR_T)(0x3F000018)) /* Communication data from ADM to host */
40#define UDATA2 (*(REG16_PTR_T)(0x3F00001A)) /* Communication data from ADM to host */
41#define UDATA3 (*(REG16_PTR_T)(0x3F00001C)) /* Communication data from ADM to host */
42#define UDATA4 (*(REG16_PTR_T)(0x3F00001E)) /* Communication data from ADM to host */
43#define UDATA5 (*(REG16_PTR_T)(0x3F000020)) /* Communication data from ADM to host */
44#define UDATA6 (*(REG16_PTR_T)(0x3F000022)) /* Communication data from ADM to host */
45#define UDATA7 (*(REG16_PTR_T)(0x3F000024)) /* Communication data from ADM to host */
46#define IBASE_H (*(REG16_PTR_T)(0x3F000026)) /* Higher half of start address for ADM instruction area */
47#define IBASE_L (*(REG16_PTR_T)(0x3F000028)) /* Lower half of start address for ADM instruction area */
48#define DBASE_H (*(REG16_PTR_T)(0x3F00002A)) /* Higher half of start address for CalmRISC data area */
49#define DBASE_L (*(REG16_PTR_T)(0x3F00002C)) /* Lower half of start address for CalmRISC data area */
50#define XBASE_H (*(REG16_PTR_T)(0x3F00002E)) /* Higher half of start address for Mac X area */
51#define XBASE_L (*(REG16_PTR_T)(0x3F000030)) /* Lower half of start address for Mac X area */
52#define YBASE_H (*(REG16_PTR_T)(0x3F000032)) /* Higher half of start address for Mac Y area */
53#define YBASE_L (*(REG16_PTR_T)(0x3F000034)) /* Lower half of start address for Mac Y area */
54#define S0BASE_H (*(REG16_PTR_T)(0x3F000036)) /* Higher half of start address for sequential buffer 0 area */
55#define S0BASE_L (*(REG16_PTR_T)(0x3F000038)) /* Lower half of start address for sequential buffer 0 area */
56#define S1BASE_H (*(REG16_PTR_T)(0x3F00003A)) /* Higher half of start address for sequential buffer 1 area */
57#define S1BASE_L (*(REG16_PTR_T)(0x3F00003C)) /* Lower half of start address for sequential buffer 1 area */
58#define CACHECON (*(REG16_PTR_T)(0x3F00003E)) /* Cache Control Register */
59#define CACHESTAT (*(REG16_PTR_T)(0x3F000040)) /* Cache status register */
60#define SBFCON (*(REG16_PTR_T)(0x3F000042)) /* Sequential Buffer Control Register */
61#define SBFSTAT (*(REG16_PTR_T)(0x3F000044)) /* Sequential Buffer Status Register */
62#define SBL0OFF_H (*(REG16_PTR_T)(0x3F000046)) /* Higher bits of Offset register of sequential block 0 area */
63#define SBL0OFF_L (*(REG16_PTR_T)(0x3F000048)) /* Lower bits of Offset register of sequential block 0 area */
64#define SBL1OFF_H (*(REG16_PTR_T)(0x3F00004A)) /* Higher bits of Offset register of sequential block 1 area */
65#define SBL1OFF_L (*(REG16_PTR_T)(0x3F00004C)) /* Lower bits of Offset register of sequential block 1 area */
66#define SBL0BEGIN_H (*(REG16_PTR_T)(0x3F00004E)) /* Higher bits of Begin Offset of sequential block 0 area in ring mode */
67#define SBL0BEGIN_L (*(REG16_PTR_T)(0x3F000050)) /* Lower bits of Begin Offset of sequential block 0 area in ring mode */
68#define SBL1BEGIN_H (*(REG16_PTR_T)(0x3F000052)) /* Higher bits of Begin Offset of sequential block 1 area in ring mode */
69#define SBL1BEGIN_L (*(REG16_PTR_T)(0x3F000054)) /* Lower bits of Begin Offset of sequential block 1 area in ring mode */
70#define SBL0END_H (*(REG16_PTR_T)(0x3F000056)) /* Lower bits of End Offset of sequential block 0 area in ring mode */
71#define SBL0END_L (*(REG16_PTR_T)(0x3F000058)) /* Higher bits of End Offset of sequential block 0 area in ring mode */
72#define SBL1END_H (*(REG16_PTR_T)(0x3F00005A)) /* Lower bits of End Offset of sequential block 1 area in ring mode */
73#define SBL1END_L (*(REG16_PTR_T)(0x3F00005C)) /* Higher bits of End Offset of sequential block 1 area in ring mode */
74
75/* Following registers are components of SFRS of the target system */
76#define ADM_CONFIG (*(REG32_PTR_T)(0x39000000)) /* Configuration/Control Register */
77#define ADM_COMMUN (*(REG32_PTR_T)(0x39000004)) /* Communication Control Register */
78#define ADM_DDATA0 (*(REG32_PTR_T)(0x39000010)) /* Communication data from host to ADM */
79#define ADM_DDATA1 (*(REG32_PTR_T)(0x39000014)) /* Communication data from host to ADM */
80#define ADM_DDATA2 (*(REG32_PTR_T)(0x39000018)) /* Communication data from host to ADM */
81#define ADM_DDATA3 (*(REG32_PTR_T)(0x3900001C)) /* Communication data from host to ADM */
82#define ADM_DDATA4 (*(REG32_PTR_T)(0x39000020)) /* Communication data from host to ADM */
83#define ADM_DDATA5 (*(REG32_PTR_T)(0x39000024)) /* Communication data from host to ADM */
84#define ADM_DDATA6 (*(REG32_PTR_T)(0x39000028)) /* Communication data from host to ADM */
85#define ADM_DDATA7 (*(REG32_PTR_T)(0x3900002C)) /* Communication data from host to ADM */
86#define ADM_UDATA0 (*(REG32_PTR_T)(0x39000030)) /* Communication data from ADM to host */
87#define ADM_UDATA1 (*(REG32_PTR_T)(0x39000034)) /* Communication data from ADM to host */
88#define ADM_UDATA2 (*(REG32_PTR_T)(0x39000038)) /* Communication data from ADM to host */
89#define ADM_UDATA3 (*(REG32_PTR_T)(0x3900003C)) /* Communication data from ADM to host */
90#define ADM_UDATA4 (*(REG32_PTR_T)(0x39000040)) /* Communication data from ADM to host */
91#define ADM_UDATA5 (*(REG32_PTR_T)(0x39000044)) /* Communication data from ADM to host */
92#define ADM_UDATA6 (*(REG32_PTR_T)(0x39000048)) /* Communication data from ADM to host */
93#define ADM_UDATA7 (*(REG32_PTR_T)(0x3900004C)) /* Communication data from ADM to host */
94#define ADM_IBASE (*(REG32_PTR_T)(0x39000050)) /* Start Address for ADM Instruction Area */
95#define ADM_DBASE (*(REG32_PTR_T)(0x39000054)) /* Start Address for CalmRISC Data Area */
96#define ADM_XBASE (*(REG32_PTR_T)(0x39000058)) /* Start Address for Mac X Area */
97#define ADM_YBASE (*(REG32_PTR_T)(0x3900005C)) /* Start Address for Mac Y Area */
98#define ADM_S0BASE (*(REG32_PTR_T)(0x39000060)) /* Start Address for Sequential Block 0 Area */
99#define ADM_S1BASE (*(REG32_PTR_T)(0x39000064)) /* Start Address for Sequential Block 1 Area */
100
101/* 05. CLOCK & POWER MANAGEMENT */
102#define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */
103#define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */
104#define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */
105#define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */
106#define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */
107#define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */
108#define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */
109#define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */
110#define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */
111#define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */
112#define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */
113#define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */
114#define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* clock control register 2 */
115
116/* 06. INTERRUPT CONTROLLER UNIT */
117#define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */
118#define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */
119#define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */
120#define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */
121#define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */
122#define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */
123#define EINTPOL (*(REG32_PTR_T)(0x39C00018)) /* Indicates external interrupt polarity */
124#define EINTPEND (*(REG32_PTR_T)(0x39C0001C)) /* Indicates whether external interrupts are pending. */
125#define EINTMSK (*(REG32_PTR_T)(0x39C00020)) /* Indicates whether external interrupts are masked */
126
127/* 07. MEMORY INTERFACE UNIT (MIU) */
128
129/* SDRAM */
130#define MIUCON (*(REG32_PTR_T)(0x38200000)) /* External Memory configuration register */
131#define MIUCOM (*(REG32_PTR_T)(0x38200004)) /* Command and status register */
132#define MIUAREF (*(REG32_PTR_T)(0x38200008)) /* Auto-refresh control register */
133#define MIUMRS (*(REG32_PTR_T)(0x3820000C)) /* SDRAM Mode Register Set Value Register */
134#define MIUSDPARA (*(REG32_PTR_T)(0x38200010)) /* SDRAM parameter register */
135
136/* DDR */
137#define MEMCONF (*(REG32_PTR_T)(0x38200020)) /* External Memory configuration register */
138#define USRCMD (*(REG32_PTR_T)(0x38200024)) /* Command and Status register */
139#define AREF (*(REG32_PTR_T)(0x38200028)) /* Auto-refresh control register */
140#define MRS (*(REG32_PTR_T)(0x3820002C)) /* DRAM mode register set value register */
141#define DPARAM (*(REG32_PTR_T)(0x38200030)) /* DRAM parameter register (Unit of ‘tXXX’ : tCK */
142#define SMEMCONF (*(REG32_PTR_T)(0x38200034)) /* Static memory mode register set value register */
143#define MIUS01PARA (*(REG32_PTR_T)(0x38200038)) /* SRAM0, SRAM1 static memory parameter register (In S5L8700, SRAM0 is Nor Flash) */
144#define MIUS23PARA (*(REG32_PTR_T)(0x3820003C)) /* SRAM2 and SRAM3 static memory parameter register */
145
146#define MIUORG (*(REG32_PTR_T)(0x38200040)) /* SDR/DDR selection */
147#define MIUDLYDQS (*(REG32_PTR_T)(0x38200044)) /* DQS/DQS-rst delay parameter */
148#define MIUDLYCLK (*(REG32_PTR_T)(0x38200048)) /* SDR/DDR Clock delay parameter */
149#define MIU_DSS_SEL_B (*(REG32_PTR_T)(0x3820004C)) /* SSTL2 Drive Strength parameter for Bi-direction signal */
150#define MIU_DSS_SEL_O (*(REG32_PTR_T)(0x38200050)) /* SSTL2 Drive Strength parameter for Output signal */
151#define MIU_DSS_SEL_C (*(REG32_PTR_T)(0x38200054)) /* SSTL2 Drive Strength parameter for Clock signal */
152#define PAD_DSS_SEL_NOR (*(REG32_PTR_T)(0x38200058)) /* Wide range I/O Drive Strength parameter for NOR interface */
153#define PAD_DSS_SEL_ATA (*(REG32_PTR_T)(0x3820005C)) /* Wide range I/O Drive Strength parameter for ATA interface */
154#define SSTL2_PAD_ON (*(REG32_PTR_T)(0x38200060)) /* SSTL2 pad ON/OFF select */
155
156/* 08. IODMA CONTROLLER */
157#define DMABASE0 (*(REG32_PTR_T)(0x38400000)) /* Base address register for channel 0 */
158#define DMACON0 (*(REG32_PTR_T)(0x38400004)) /* Configuration register for channel 0 */
159#define DMATCNT0 (*(REG32_PTR_T)(0x38400008)) /* Transfer count register for channel 0 */
160#define DMACADDR0 (*(REG32_PTR_T)(0x3840000C)) /* Current memory address register for channel 0 */
161#define DMACTCNT0 (*(REG32_PTR_T)(0x38400010)) /* Current transfer count register for channel 0 */
162#define DMACOM0 (*(REG32_PTR_T)(0x38400014)) /* Channel 0 command register */
163#define DMANOFF0 (*(REG32_PTR_T)(0x38400018)) /* Channel 0 offset2 register */
164#define DMABASE1 (*(REG32_PTR_T)(0x38400020)) /* Base address register for channel 1 */
165#define DMACON1 (*(REG32_PTR_T)(0x38400024)) /* Configuration register for channel 1 */
166#define DMATCNT1 (*(REG32_PTR_T)(0x38400028)) /* Transfer count register for channel 1 */
167#define DMACADDR1 (*(REG32_PTR_T)(0x3840002C)) /* Current memory address register for channel 1 */
168#define DMACTCNT1 (*(REG32_PTR_T)(0x38400030)) /* Current transfer count register for channel 1 */
169#define DMACOM1 (*(REG32_PTR_T)(0x38400034)) /* Channel 1 command register */
170#define DMABASE2 (*(REG32_PTR_T)(0x38400040)) /* Base address register for channel 2 */
171#define DMACON2 (*(REG32_PTR_T)(0x38400044)) /* Configuration register for channel 2 */
172#define DMATCNT2 (*(REG32_PTR_T)(0x38400048)) /* Transfer count register for channel 2 */
173#define DMACADDR2 (*(REG32_PTR_T)(0x3840004C)) /* Current memory address register for channel 2 */
174#define DMACTCNT2 (*(REG32_PTR_T)(0x38400050)) /* Current transfer count register for channel 2 */
175#define DMACOM2 (*(REG32_PTR_T)(0x38400054)) /* Channel 2 command register */
176#define DMABASE3 (*(REG32_PTR_T)(0x38400060)) /* Base address register for channel 3 */
177#define DMACON3 (*(REG32_PTR_T)(0x38400064)) /* Configuration register for channel 3 */
178#define DMATCNT3 (*(REG32_PTR_T)(0x38400068)) /* Transfer count register for channel 3 */
179#define DMACADDR3 (*(REG32_PTR_T)(0x3840006C)) /* Current memory address register for channel 3 */
180#define DMACTCNT3 (*(REG32_PTR_T)(0x38400070)) /* Current transfer count register for channel 3 */
181#define DMACOM3 (*(REG32_PTR_T)(0x38400074)) /* Channel 3 command register */
182#define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */
183
184/* 10. REAL TIMER CLOCK (RTC) */
185#define RTCCON (*(REG32_PTR_T)(0x3D200000)) /* RTC Control Register */
186#define RTCRST (*(REG32_PTR_T)(0x3D200004)) /* RTC Round Reset Register */
187#define RTCALM (*(REG32_PTR_T)(0x3D200008)) /* RTC Alarm Control Register */
188#define ALMSEC (*(REG32_PTR_T)(0x3D20000C)) /* Alarm Second Data Register */
189#define ALMMIN (*(REG32_PTR_T)(0x3D200010)) /* Alarm Minute Data Register */
190#define ALMHOUR (*(REG32_PTR_T)(0x3D200014)) /* Alarm Hour Data Register */
191#define ALMDATE (*(REG32_PTR_T)(0x3D200018)) /* Alarm Date Data Register */
192#define ALMDAY (*(REG32_PTR_T)(0x3D20001C)) /* Alarm Day of Week Data Register */
193#define ALMMON (*(REG32_PTR_T)(0x3D200020)) /* Alarm Month Data Register */
194#define ALMYEAR (*(REG32_PTR_T)(0x3D200024)) /* Alarm Year Data Register */
195#define BCDSEC (*(REG32_PTR_T)(0x3D200028)) /* BCD Second Register */
196#define BCDMIN (*(REG32_PTR_T)(0x3D20002C)) /* BCD Minute Register */
197#define BCDHOUR (*(REG32_PTR_T)(0x3D200030)) /* BCD Hour Register */
198#define BCDDATE (*(REG32_PTR_T)(0x3D200034)) /* BCD Date Register */
199#define BCDDAY (*(REG32_PTR_T)(0x3D200038)) /* BCD Day of Week Register */
200#define BCDMON (*(REG32_PTR_T)(0x3D20003C)) /* BCD Month Register */
201#define BCDYEAR (*(REG32_PTR_T)(0x3D200040)) /* BCD Year Register */
202#define RTCIM (*(REG32_PTR_T)(0x3D200044)) /* RTC Interrupt Mode Register */
203#define RTCPEND (*(REG32_PTR_T)(0x3D200048)) /* RTC Interrupt Pending Register */
204
205/* 09. WATCHDOG TIMER*/
206#define WDTCON (*(REG32_PTR_T)(0x3C800000)) /* Control Register */
207#define WDTCNT (*(REG32_PTR_T)(0x3C800004)) /* 11-bits internal counter */
208
209/* 11. 16 BIT TIMER */
210#define TACON (*(REG32_PTR_T)(0x3C700000)) /* Control Register for timer A */
211#define TACMD (*(REG32_PTR_T)(0x3C700004)) /* Command Register for timer A */
212#define TADATA0 (*(REG32_PTR_T)(0x3C700008)) /* Data0 Register */
213#define TADATA1 (*(REG32_PTR_T)(0x3C70000C)) /* Data1 Register */
214#define TAPRE (*(REG32_PTR_T)(0x3C700010)) /* Pre-scale register */
215#define TACNT (*(REG32_PTR_T)(0x3C700014)) /* Counter register */
216#define TBCON (*(REG32_PTR_T)(0x3C700020)) /* Control Register for timer B */
217#define TBCMD (*(REG32_PTR_T)(0x3C700024)) /* Command Register for timer B */
218#define TBDATA0 (*(REG32_PTR_T)(0x3C700028)) /* Data0 Register */
219#define TBDATA1 (*(REG32_PTR_T)(0x3C70002C)) /* Data1 Register */
220#define TBPRE (*(REG32_PTR_T)(0x3C700030)) /* Pre-scale register */
221#define TBCNT (*(REG32_PTR_T)(0x3C700034)) /* Counter register */
222#define TCCON (*(REG32_PTR_T)(0x3C700040)) /* Control Register for timer C */
223#define TCCMD (*(REG32_PTR_T)(0x3C700044)) /* Command Register for timer C */
224#define TCDATA0 (*(REG32_PTR_T)(0x3C700048)) /* Data0 Register */
225#define TCDATA1 (*(REG32_PTR_T)(0x3C70004C)) /* Data1 Register */
226#define TCPRE (*(REG32_PTR_T)(0x3C700050)) /* Pre-scale register */
227#define TCCNT (*(REG32_PTR_T)(0x3C700054)) /* Counter register */
228#define TDCON (*(REG32_PTR_T)(0x3C700060)) /* Control Register for timer D */
229#define TDCMD (*(REG32_PTR_T)(0x3C700064)) /* Command Register for timer D */
230#define TDDATA0 (*(REG32_PTR_T)(0x3C700068)) /* Data0 Register */
231#define TDDATA1 (*(REG32_PTR_T)(0x3C70006C)) /* Data1 Register */
232#define TDPRE (*(REG32_PTR_T)(0x3C700070)) /* Pre-scale register */
233#define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */
234
235/* 12. NAND FLASH CONTROLER */
236#define FMCTRL0 (*(REG32_PTR_T)(0x3C200000)) /* Control Register0 */
237#define FMCTRL1 (*(REG32_PTR_T)(0x3C200004)) /* Control Register1 */
238#define FMCMD (*(REG32_PTR_T)(0x3C200008)) /* Command Register */
239#define FMADDR0 (*(REG32_PTR_T)(0x3C20000C)) /* Address Register0 */
240#define FMADDR1 (*(REG32_PTR_T)(0x3C200010)) /* Address Register1 */
241#define FMADDR2 (*(REG32_PTR_T)(0x3C200014)) /* Address Register2 */
242#define FMADDR3 (*(REG32_PTR_T)(0x3C200018)) /* Address Register3 */
243#define FMADDR4 (*(REG32_PTR_T)(0x3C20001C)) /* Address Register4 */
244#define FMADDR5 (*(REG32_PTR_T)(0x3C200020)) /* Address Register5 */
245#define FMADDR6 (*(REG32_PTR_T)(0x3C200024)) /* Address Register6 */
246#define FMADDR7 (*(REG32_PTR_T)(0x3C200028)) /* Address Register7 */
247#define FMANUM (*(REG32_PTR_T)(0x3C20002C)) /* Address Counter Register */
248#define FMDNUM (*(REG32_PTR_T)(0x3C200030)) /* Data Counter Register */
249#define FMDATAW0 (*(REG32_PTR_T)(0x3C200034)) /* Write Data Register0 */
250#define FMDATAW1 (*(REG32_PTR_T)(0x3C200038)) /* Write Data Register1 */
251#define FMDATAW2 (*(REG32_PTR_T)(0x3C20003C)) /* Write Data Register2 */
252#define FMDATAW3 (*(REG32_PTR_T)(0x3C200040)) /* Write Data Register3 */
253#define FMCSTAT (*(REG32_PTR_T)(0x3C200048)) /* Status Register */
254#define FMSYND0 (*(REG32_PTR_T)(0x3C20004C)) /* Hamming Syndrome0 */
255#define FMSYND1 (*(REG32_PTR_T)(0x3C200050)) /* Hamming Syndrome1 */
256#define FMSYND2 (*(REG32_PTR_T)(0x3C200054)) /* Hamming Syndrome2 */
257#define FMSYND3 (*(REG32_PTR_T)(0x3C200058)) /* Hamming Syndrome3 */
258#define FMSYND4 (*(REG32_PTR_T)(0x3C20005C)) /* Hamming Syndrome4 */
259#define FMSYND5 (*(REG32_PTR_T)(0x3C200060)) /* Hamming Syndrome5 */
260#define FMSYND6 (*(REG32_PTR_T)(0x3C200064)) /* Hamming Syndrome6 */
261#define FMSYND7 (*(REG32_PTR_T)(0x3C200068)) /* Hamming Syndrome7 */
262#define FMFIFO (*(REG32_PTR_T)(0x3C200080)) /* WRITE/READ FIFO FIXME */
263#define RSCRTL (*(REG32_PTR_T)(0x3C200100)) /* Reed-Solomon Control Register */
264#define RSPaity0_0 (*(REG32_PTR_T)(0x3C200110)) /* On-the-fly Parity Register0[31:0] */
265#define RSPaity0_1 (*(REG32_PTR_T)(0x3C200114)) /* On-the-fly Parity Register0[63:32] */
266#define RSPaity0_2 (*(REG32_PTR_T)(0x3C200118)) /* On-the-fly Parity Register0[71:64] */
267#define RSPaity1_0 (*(REG32_PTR_T)(0x3C200120)) /* On-the-fly Parity Register1[31:0] */
268#define RSPaity1_1 (*(REG32_PTR_T)(0x3C200124)) /* On-the-fly Parity Register1[63:32] */
269#define RSPaity1_2 (*(REG32_PTR_T)(0x3C200128)) /* On-the-fly Parity Register1[71:64] */
270#define RSPaity2_0 (*(REG32_PTR_T)(0x3C200130)) /* On-the-fly Parity Register2[31:0] */
271#define RSPaity2_1 (*(REG32_PTR_T)(0x3C200134)) /* On-the-fly Parity Register2[63:32] */
272#define RSPaity2_2 (*(REG32_PTR_T)(0x3C200138)) /* On-the-fly Parity Register2[71:64] */
273#define RSPaity3_0 (*(REG32_PTR_T)(0x3C200140)) /* On-the-fly Parity Register3[31:0] */
274#define RSPaity3_1 (*(REG32_PTR_T)(0x3C200144)) /* On-the-fly Parity Register3[63:32] */
275#define RSPaity3_2 (*(REG32_PTR_T)(0x3C200148)) /* On-the-fly Parity Register3[71:64] */
276#define RSSynd0_0 (*(REG32_PTR_T)(0x3C200150)) /* On-the-fly Synd Register0[31:0] */
277#define RSSynd0_1 (*(REG32_PTR_T)(0x3C200154)) /* On-the-fly Synd Register0[63:32] */
278#define RSSynd0_2 (*(REG32_PTR_T)(0x3C200158)) /* On-the-fly Synd Register0[71:64] */
279#define RSSynd1_0 (*(REG32_PTR_T)(0x3C200160)) /* On-the-fly Synd Register1[31:0] */
280#define RSSynd1_1 (*(REG32_PTR_T)(0x3C200164)) /* On-the-fly Synd Register1[63:32] */
281#define RSSynd1_2 (*(REG32_PTR_T)(0x3C200168)) /* On-the-fly Synd Register1[71:64] */
282#define RSSynd2_0 (*(REG32_PTR_T)(0x3C200170)) /* On-the-fly Synd Register2[31:0] */
283#define RSSynd2_1 (*(REG32_PTR_T)(0x3C200174)) /* On-the-fly Synd Register2[63:32] */
284#define RSSynd2_2 (*(REG32_PTR_T)(0x3C200178)) /* On-the-fly Synd Register2[71:64] */
285#define RSSynd3_0 (*(REG32_PTR_T)(0x3C200180)) /* On-the-fly Synd Register3[31:0] */
286#define RSSynd3_1 (*(REG32_PTR_T)(0x3C200184)) /* On-the-fly Synd Register3[63:32] */
287#define RSSynd3_2 (*(REG32_PTR_T)(0x3C200188)) /* On-the-fly Synd Register3[71:64] */
288#define FlagSynd (*(REG32_PTR_T)(0x3C200190)) /* On-the-fly ECC Result Flag */
289
290/* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */
291#define SDCI_CTRL (*(REG32_PTR_T)(0x3C300000)) /* Control Register */
292#define SDCI_DCTRL (*(REG32_PTR_T)(0x3C300004)) /* Data Control Register */
293#define SDCI_CMD (*(REG32_PTR_T)(0x3C300008)) /* Command Register */
294#define SDCI_ARGU (*(REG32_PTR_T)(0x3C30000C)) /* Argument Register */
295#define SDCI_STATE (*(REG32_PTR_T)(0x3C300010)) /* State Register */
296#define SDCI_STAC (*(REG32_PTR_T)(0x3C300014)) /* Status Clear Register */
297#define SDCI_DSTA (*(REG32_PTR_T)(0x3C300018)) /* Data Status Register */
298#define SDCI_FSTA (*(REG32_PTR_T)(0x3C30001C)) /* FIFO Status Register */
299#define SDCI_RESP0 (*(REG32_PTR_T)(0x3C300020)) /* Response0 Register */
300#define SDCI_RESP1 (*(REG32_PTR_T)(0x3C300024)) /* Response1 Register */
301#define SDCI_RESP2 (*(REG32_PTR_T)(0x3C300028)) /* Response2 Register */
302#define SDCI_RESP3 (*(REG32_PTR_T)(0x3C30002C)) /* Response3 Register */
303#define SDCI_CLKDIV (*(REG32_PTR_T)(0x3C300030)) /* Clock Divider Register */
304#define SDIO_CSR (*(REG32_PTR_T)(0x3C300034)) /* SDIO Control & Status Register */
305#define SDIO_IRQ (*(REG32_PTR_T)(0x3C300038)) /* Interrupt Source Register */
306
307/* 14. MEMORY STICK HOST CONTROLLER */
308#define MSPRE (*(REG32_PTR_T)(0x3C600000)) /* Prescaler Register */
309#define MSINTEN (*(REG32_PTR_T)(0x3C600004)) /* Interrupt Enable Register */
310#define MSCMD (*(REG32_PTR_T)(0x3C601000)) /* Command Register */
311#define MSFIFO (*(REG32_PTR_T)(0x3C601008)) /* Receive/Transmit Register */
312#define MSPP (*(REG32_PTR_T)(0x3C601010)) /* Parallel Port Control/Data Register */
313#define MSCTRL2 (*(REG32_PTR_T)(0x3C601014)) /* Control Register 2 */
314#define MSACD (*(REG32_PTR_T)(0x3C601018)) /* ACD Command Register */
315
316/* 15. SPDIF TRANSMITTER (SPDIFOUT) */
317#define SPDCLKCON (*(REG32_PTR_T)(0x3CB00000)) /* Clock Control Register */
318#define SPDCON (*(REG32_PTR_T)(0x3CB00004)) /* Control Register 0020 */
319#define SPDBSTAS (*(REG32_PTR_T)(0x3CB00008)) /* Burst Status Register */
320#define SPDCSTAS (*(REG32_PTR_T)(0x3CB0000C)) /* Channel Status Register 0x2000 8000 */
321#define SPDDAT (*(REG32_PTR_T)(0x3CB00010)) /* SPDIFOUT Data Buffer */
322#define SPDCNT (*(REG32_PTR_T)(0x3CB00014)) /* Repetition Count Register */
323
324/* 16. REED-SOLOMON ECC CODEC */
325#define DATA_PTR (*(REG32_PTR_T)(0x39E00004)) /* Data Area Start Pointer */
326#define SPARE_PTR (*(REG32_PTR_T)(0x39E00008)) /* Spare Area Start Pointer */
327#define ECC_CTRL (*(REG32_PTR_T)(0x39E0000C)) /* ECC Control Register */
328#define ECC_RESULT (*(REG32_PTR_T)(0x39E00010)) /* ECC Result */
329#define ECC_EVAL0 (*(REG32_PTR_T)(0x39E00020)) /* Error Eval0 Poly */
330#define ECC_EVAL1 (*(REG32_PTR_T)(0x39E00024)) /* Error Eval1 Poly */
331#define ECC_LOC0 (*(REG32_PTR_T)(0x39E00028)) /* Error Loc0 Poly */
332#define ECC_LOC1 (*(REG32_PTR_T)(0x39E0002C)) /* Error Loc1 Poly */
333#define PARITY0 (*(REG32_PTR_T)(0x39E00030)) /* Encode Parity0 Poly */
334#define PARITY1 (*(REG32_PTR_T)(0x39E00034)) /* Encode Pariyt1 Poly */
335#define PARITY2 (*(REG32_PTR_T)(0x39E00038)) /* Encode Parity2 Poly */
336#define INT_CLR (*(REG32_PTR_T)(0x39E00040)) /* Interrupt Clear Register */
337#define SYND0 (*(REG32_PTR_T)(0x39E00044)) /* Syndrom0 Poly */
338#define SYND1 (*(REG32_PTR_T)(0x39E00048)) /* Syndrom1 Poly */
339#define SYND2 (*(REG32_PTR_T)(0x39E0004C)) /* Syndrom2 Poly */
340
341/* 17. IIS Tx/Rx INTERFACE */
342#define I2SCLKCON (*(REG32_PTR_T)(0x3CA00000)) /* Clock Control Register */
343#define I2STXCON (*(REG32_PTR_T)(0x3CA00004)) /* Tx configuration Register */
344#define I2STXCOM (*(REG32_PTR_T)(0x3CA00008)) /* Tx command Register */
345#define I2STXDB0 (*(REG32_PTR_T)(0x3CA00010)) /* Tx data buffer */
346#define I2SRXCON (*(REG32_PTR_T)(0x3CA00030)) /* Rx configuration Register */
347#define I2SRXCOM (*(REG32_PTR_T)(0x3CA00034)) /* Rx command Register */
348#define I2SRXDB (*(REG32_PTR_T)(0x3CA00038)) /* Rx data buffer */
349#define I2SSTATUS (*(REG32_PTR_T)(0x3CA0003C)) /* status register */
350
351/* 18. IIC BUS INTERFACE */
352#define IICCON (*(REG32_PTR_T)(0x3C900000)) /* Control Register */
353#define IICSTAT (*(REG32_PTR_T)(0x3C900004)) /* Control/Status Register */
354#define IICADD (*(REG32_PTR_T)(0x3C900008)) /* Bus Address Register */
355#define IICDS (*(REG32_PTR_T)(0x3C90000C))
356
357/* 19. SPI (SERIAL PERHIPERAL INTERFACE) */
358#define SPCLKCON (*(REG32_PTR_T)(0x3CD00000)) /* Clock Control Register */
359#define SPCON (*(REG32_PTR_T)(0x3CD00004)) /* Control Register */
360#define SPSTA (*(REG32_PTR_T)(0x3CD00008)) /* Status Register */
361#define SPPIN (*(REG32_PTR_T)(0x3CD0000C)) /* Pin Control Register */
362#define SPTDAT (*(REG32_PTR_T)(0x3CD00010)) /* Tx Data Register */
363#define SPRDAT (*(REG32_PTR_T)(0x3CD00014)) /* Rx Data Register */
364#define SPPRE (*(REG32_PTR_T)(0x3CD00018)) /* Baud Rate Prescaler Register */
365
366/* 20. ADC CONTROLLER */
367#define ADCCON (*(REG32_PTR_T)(0x3CE00000)) /* ADC Control Register */
368#define ADCTSC (*(REG32_PTR_T)(0x3CE00004)) /* ADC Touch Screen Control Register */
369#define ADCDLY (*(REG32_PTR_T)(0x3CE00008)) /* ADC Start or Interval Delay Register */
370#define ADCDAT0 (*(REG32_PTR_T)(0x3CE0000C)) /* ADC Conversion Data Register */
371#define ADCDAT1 (*(REG32_PTR_T)(0x3CE00010)) /* ADC Conversion Data Register */
372#define ADCUPDN (*(REG32_PTR_T)(0x3CE00014)) /* Stylus Up or Down Interrpt Register */
373
374/* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */
375#define IR (*(REG32_PTR_T)(0x38800000)) /* Index Register */
376#define EIR (*(REG32_PTR_T)(0x38800004)) /* Endpoint Interrupt Register */
377#define EIER (*(REG32_PTR_T)(0x38800008)) /* Endpoint Interrupt Enable Register */
378#define FAR (*(REG32_PTR_T)(0x3880000C)) /* Function Address Register */
379#define FNR (*(REG32_PTR_T)(0x38800010)) /* Frame Number Register */
380#define EDR (*(REG32_PTR_T)(0x38800014)) /* Endpoint Direction Register */
381#define TR (*(REG32_PTR_T)(0x38800018)) /* Test Register */
382#define SSR (*(REG32_PTR_T)(0x3880001C)) /* System Status Register */
383#define SCR (*(REG32_PTR_T)(0x38800020)) /* System Control Register */
384#define EP0SR (*(REG32_PTR_T)(0x38800024)) /* EP0 Status Register */
385#define EP0CR (*(REG32_PTR_T)(0x38800028)) /* EP0 Control Register */
386#define ESR (*(REG32_PTR_T)(0x3880002C)) /* Endpoints Status Register */
387#define ECR (*(REG32_PTR_T)(0x38800030)) /* Endpoints Control Register */
388#define BRCR (*(REG32_PTR_T)(0x38800034)) /* Byte Read Count Register */
389#define BWCR (*(REG32_PTR_T)(0x38800038)) /* Byte Write Count Register */
390#define MPR (*(REG32_PTR_T)(0x3880003C)) /* Max Packet Register */
391#define MCR (*(REG32_PTR_T)(0x38800040)) /* Master Control Register */
392#define MTCR (*(REG32_PTR_T)(0x38800044)) /* Master Transfer Counter Register */
393#define MFCR (*(REG32_PTR_T)(0x38800048)) /* Master FIFO Counter Register */
394#define MTTCR1 (*(REG32_PTR_T)(0x3880004C)) /* Master Total Transfer Counter1 Register */
395#define MTTCR2 (*(REG32_PTR_T)(0x38800050)) /* Master Total Transfer Counter2 Register */
396#define EP0BR (*(REG32_PTR_T)(0x38800060)) /* EP0 Buffer Register */
397#define EP1BR (*(REG32_PTR_T)(0x38800064)) /* EP1 Buffer Register */
398#define EP2BR (*(REG32_PTR_T)(0x38800068)) /* EP2 Buffer Register */
399#define EP3BR (*(REG32_PTR_T)(0x3880006C)) /* EP3 Buffer Register */
400#define EP4BR (*(REG32_PTR_T)(0x38800070)) /* EP4 Buffer Register */
401#define EP5BR (*(REG32_PTR_T)(0x38800074)) /* EP5 Buffer Register */
402#define EP6BR (*(REG32_PTR_T)(0x38800078)) /* EP6 Buffer Register */
403#define MICR (*(REG32_PTR_T)(0x38800084)) /* Master Interface Counter Register */
404#define MBAR1 (*(REG32_PTR_T)(0x38800088)) /* Memory Base Address Register1 */
405#define MBAR2 (*(REG32_PTR_T)(0x3880008C)) /* Memory Base Address Register2 */
406#define MCAR1 (*(REG32_PTR_T)(0x38800094)) /* Memory Current Address Register1 */
407#define MCAR2 (*(REG32_PTR_T)(0x38800098)) /* Memory Current Address Register2 */
408
409/* 22. USB 1.1 HOST CONTROLER SPECIAL REGISTER */
410#define HcRevision (*(REG32_PTR_T)(0x38600000))
411#define HcControl (*(REG32_PTR_T)(0x38600004))
412#define HcCommandStatus (*(REG32_PTR_T)(0x38600008))
413#define HcInterruptStatus (*(REG32_PTR_T)(0x3860000C))
414#define HcInterruptEnable (*(REG32_PTR_T)(0x38600010))
415#define HcInterruptDisable (*(REG32_PTR_T)(0x38600014))
416#define HcHCCA (*(REG32_PTR_T)(0x38600018))
417#define HcPeriodCurrentED (*(REG32_PTR_T)(0x3860001C))
418#define HcControlHeadED (*(REG32_PTR_T)(0x38600020))
419#define HcControlCurrentED (*(REG32_PTR_T)(0x38600024))
420#define HcBulkHeadED (*(REG32_PTR_T)(0x38600028))
421#define HcBulkCurrentED (*(REG32_PTR_T)(0x3860002C))
422#define HcDoneHead (*(REG32_PTR_T)(0x38600030))
423#define HcFmInterval (*(REG32_PTR_T)(0x38600034))
424#define HcFmRemaining (*(REG32_PTR_T)(0x38600038))
425#define HcFmNumber (*(REG32_PTR_T)(0x3860003C))
426#define HcPeriodicStart (*(REG32_PTR_T)(0x38600040))
427#define HcLSThreshold (*(REG32_PTR_T)(0x38600044))
428#define HcRhDescriptorA (*(REG32_PTR_T)(0x38600048))
429#define HcRhDescriptorB (*(REG32_PTR_T)(0x3860004C))
430#define HcRhStatus (*(REG32_PTR_T)(0x38600050))
431#define HcRhPortStatus (*(REG32_PTR_T)(0x38600054))
432
433/* 23. USB 2.0 PHY CONTROL */
434#define PHYCTRL (*(REG32_PTR_T)(0x3C400000)) /* USB2.0 PHY Control Register */
435#define PHYPWR (*(REG32_PTR_T)(0x3C400004)) /* USB2.0 PHY Power Control Register */
436#define URSTCON (*(REG32_PTR_T)(0x3C400008)) /* USB Reset Control Register */
437#define UCLKCON (*(REG32_PTR_T)(0x3C400010)) /* USB Clock Control Register */
438
439/* 24. GPIO PORT CONTROLL */
440#define PCON0 (*(REG32_PTR_T)(0x3CF00000)) /* Configures the pins of port 0 */
441#define PDAT0 (*(REG32_PTR_T)(0x3CF00004)) /* The data register for port 0 */
442#define PCON1 (*(REG32_PTR_T)(0x3CF00010)) /* Configures the pins of port 0 */
443#define PDAT1 (*(REG32_PTR_T)(0x3CF00014)) /* The data register for port 0 */
444#define PCON2 (*(REG32_PTR_T)(0x3CF00020)) /* Configures the pins of port 0 */
445#define PDAT2 (*(REG32_PTR_T)(0x3CF00024)) /* The data register for port 0 */
446#define PCON3 (*(REG32_PTR_T)(0x3CF00030)) /* Configures the pins of port 0 */
447#define PDAT3 (*(REG32_PTR_T)(0x3CF00034)) /* The data register for port 0 */
448#define PCON4 (*(REG32_PTR_T)(0x3CF00040)) /* Configures the pins of port 0 */
449#define PDAT4 (*(REG32_PTR_T)(0x3CF00044)) /* The data register for port 0 */
450#define PCON5 (*(REG32_PTR_T)(0x3CF00050)) /* Configures the pins of port 0 */
451#define PDAT5 (*(REG32_PTR_T)(0x3CF00054)) /* The data register for port 0 */
452#define PCON6 (*(REG32_PTR_T)(0x3CF00060)) /* Configures the pins of port 0 */
453#define PDAT6 (*(REG32_PTR_T)(0x3CF00064)) /* The data register for port 0 */
454#define PCON7 (*(REG32_PTR_T)(0x3CF00070)) /* Configures the pins of port 0 */
455#define PDAT7 (*(REG32_PTR_T)(0x3CF00074)) /* The data register for port 0 */
456#define PCON10 (*(REG32_PTR_T)(0x3CF000A0)) /* Configures the pins of port 0 */
457#define PDAT10 (*(REG32_PTR_T)(0x3CF000A4)) /* The data register for port 0 */
458#define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */
459#define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */
460#define PCON11 (*(REG32_PTR_T)(0x3CF000F8)) /* Configures the pins of port 11 */
461#define PDAT11 (*(REG32_PTR_T)(0x3CF000FC)) /* The data register for port 11 */
462
463/* 25. UART */
464
465/* UART 0 */
466#define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */
467#define UCON0 (*(REG32_PTR_T)(0x3CC00004)) /* Control Register */
468#define UFCON0 (*(REG32_PTR_T)(0x3CC00008)) /* FIFO Control Register */
469#define UMCON0 (*(REG32_PTR_T)(0x3CC0000C)) /* Modem Control Register */
470#define UTRSTAT0 (*(REG32_PTR_T)(0x3CC00010)) /* Tx/Rx Status Register */
471#define UERSTAT0 (*(REG32_PTR_T)(0x3CC00014)) /* Rx Error Status Register */
472#define UFSTAT0 (*(REG32_PTR_T)(0x3CC00018)) /* FIFO Status Register */
473#define UMSTAT0 (*(REG32_PTR_T)(0x3CC0001C)) /* Modem Status Register */
474#define UTXH0 (*(REG32_PTR_T)(0x3CC00020)) /* Transmit Buffer Register */
475#define URXH0 (*(REG32_PTR_T)(0x3CC00024)) /* Receive Buffer Register */
476#define UBRDIV0 (*(REG32_PTR_T)(0x3CC00028)) /* Baud Rate Divisor Register */
477
478/* UART 1*/
479#define ULCON1 (*(REG32_PTR_T)(0x3CC08000)) /* Line Control Register */
480#define UCON1 (*(REG32_PTR_T)(0x3CC08004)) /* Control Register */
481#define UFCON1 (*(REG32_PTR_T)(0x3CC08008)) /* FIFO Control Register */
482#define UMCON1 (*(REG32_PTR_T)(0x3CC0800C)) /* Modem Control Register */
483#define UTRSTAT1 (*(REG32_PTR_T)(0x3CC08010)) /* Tx/Rx Status Register */
484#define UERSTAT1 (*(REG32_PTR_T)(0x3CC08014)) /* Rx Error Status Register */
485#define UFSTAT1 (*(REG32_PTR_T)(0x3CC08018)) /* FIFO Status Register */
486#define UMSTAT1 (*(REG32_PTR_T)(0x3CC0801C)) /* Modem Status Register */
487#define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */
488#define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */
489#define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */
490
491/* 26. LCD INTERFACE CONTROLLER */
492#define LCD_CON (*(REG32_PTR_T)(0x3C100000)) /* Control register. */
493#define LCD_WCMD (*(REG32_PTR_T)(0x3C100004)) /* Write command register. */
494#define LCD_RCMD (*(REG32_PTR_T)(0x3C10000C)) /* Read command register. */
495#define LCD_RDATA (*(REG32_PTR_T)(0x3C100010)) /* Read data register. */
496#define LCD_DBUFF (*(REG32_PTR_T)(0x3C100014)) /* Read Data buffer */
497#define LCD_INTCON (*(REG32_PTR_T)(0x3C100018)) /* Interrupt control register */
498#define LCD_STATUS (*(REG32_PTR_T)(0x3C10001C)) /* LCD Interface status 0106 */
499#define LCD_PHTIME (*(REG32_PTR_T)(0x3C100020)) /* Phase time register 0060 */
500#define LCD_RST_TIME (*(REG32_PTR_T)(0x3C100024)) /* Reset active period 07FF */
501#define LCD_DRV_RST (*(REG32_PTR_T)(0x3C100028)) /* Reset drive signal */
502#define LCD_WDATA (*(REG32_PTR_T)(0x3C100040)) /* Write data register FIXME */
503
504/* 27. CLCD CONTROLLER */
505#define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */
506#define LCDCON2 (*(REG32_PTR_T)(0x39200004)) /* LCD control 2 register */
507#define LCDTCON1 (*(REG32_PTR_T)(0x39200008)) /* LCD time control 1 register */
508#define LCDTCON2 (*(REG32_PTR_T)(0x3920000C)) /* LCD time control 2 register */
509#define LCDTCON3 (*(REG32_PTR_T)(0x39200010)) /* LCD time control 3 register */
510#define LCDOSD1 (*(REG32_PTR_T)(0x39200014)) /* LCD OSD control 1 register */
511#define LCDOSD2 (*(REG32_PTR_T)(0x39200018)) /* LCD OSD control 2 register */
512#define LCDOSD3 (*(REG32_PTR_T)(0x3920001C)) /* LCD OSD control 3 register */
513#define LCDB1SADDR1 (*(REG32_PTR_T)(0x39200020)) /* Frame buffer start address register for Back-Ground buffer 1 */
514#define LCDB2SADDR1 (*(REG32_PTR_T)(0x39200024)) /* Frame buffer start address register for Back-Ground buffer 2 */
515#define LCDF1SADDR1 (*(REG32_PTR_T)(0x39200028)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 1 */
516#define LCDF2SADDR1 (*(REG32_PTR_T)(0x3920002C)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 2 */
517#define LCDB1SADDR2 (*(REG32_PTR_T)(0x39200030)) /* Frame buffer end address register for Back-Ground buffer 1 */
518#define LCDB2SADDR2 (*(REG32_PTR_T)(0x39200034)) /* Frame buffer end address register for Back-Ground buffer 2 */
519#define LCDF1SADDR2 (*(REG32_PTR_T)(0x39200038)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 1 */
520#define LCDF2SADDR2 (*(REG32_PTR_T)(0x3920003C)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 2 */
521#define LCDB1SADDR3 (*(REG32_PTR_T)(0x39200040)) /* Virtual screen address set for Back-Ground buffer 1 */
522#define LCDB2SADDR3 (*(REG32_PTR_T)(0x39200044)) /* Virtual screen address set for Back-Ground buffer 2 */
523#define LCDF1SADDR3 (*(REG32_PTR_T)(0x39200048)) /* Virtual screen address set for Fore-Ground(OSD) buffer 1 */
524#define LCDF2SADDR3 (*(REG32_PTR_T)(0x3920004C)) /* Virtual screen address set for Fore-Ground(OSD) buffer 2 */
525#define LCDINTCON (*(REG32_PTR_T)(0x39200050)) /* Indicate the LCD interrupt control register */
526#define KEYCON (*(REG32_PTR_T)(0x39200054)) /* Color key control register */
527#define COLVAL (*(REG32_PTR_T)(0x39200058)) /* Color key value ( transparent value) register */
528#define BGCON (*(REG32_PTR_T)(0x3920005C)) /* Back-Ground color control */
529#define FGCON (*(REG32_PTR_T)(0x39200060)) /* Fore-Ground color control */
530#define DITHMODE (*(REG32_PTR_T)(0x39200064)) /* Dithering mode register. */
531
532/* 28. ATA CONTROLLER */
533#define ATA_CONTROL (*(REG32_PTR_T)(0x38E00000)) /* Enable and clock down status */
534#define ATA_STATUS (*(REG32_PTR_T)(0x38E00004)) /* Status */
535#define ATA_COMMAND (*(REG32_PTR_T)(0x38E00008)) /* Command */
536#define ATA_SWRST (*(REG32_PTR_T)(0x38E0000C)) /* Software reset */
537#define ATA_IRQ (*(REG32_PTR_T)(0x38E00010)) /* Interrupt sources */
538#define ATA_IRQ_MASK (*(REG32_PTR_T)(0x38E00014)) /* Interrupt mask */
539#define ATA_CFG (*(REG32_PTR_T)(0x38E00018)) /* Configuration for ATA interface */
540#define ATA_PIO_TIME (*(REG32_PTR_T)(0x38E0002C)) /* PIO timing */
541#define ATA_UDMA_TIME (*(REG32_PTR_T)(0x38E00030)) /* UDMA timing */
542#define ATA_XFR_NUM (*(REG32_PTR_T)(0x38E00034)) /* Transfer number */
543#define ATA_XFR_CNT (*(REG32_PTR_T)(0x38E00038)) /* Current transfer count */
544#define ATA_TBUF_START (*(REG32_PTR_T)(0x38E0003C)) /* Start address of track buffer */
545#define ATA_TBUF_SIZE (*(REG32_PTR_T)(0x38E00040)) /* Size of track buffer */
546#define ATA_SBUF_START (*(REG32_PTR_T)(0x38E00044)) /* Start address of Source buffer1 */
547#define ATA_SBUF_SIZE (*(REG32_PTR_T)(0x38E00048)) /* Size of source buffer1 */
548#define ATA_CADR_TBUF (*(REG32_PTR_T)(0x38E0004C)) /* Current write address of track buffer */
549#define ATA_CADR_SBUF (*(REG32_PTR_T)(0x38E00050)) /* Current read address of source buffer */
550#define ATA_PIO_DTR (*(REG32_PTR_T)(0x38E00054)) /* PIO device data register */
551#define ATA_PIO_FED (*(REG32_PTR_T)(0x38E00058)) /* PIO device Feature/Error register */
552#define ATA_PIO_SCR (*(REG32_PTR_T)(0x38E0005C)) /* PIO sector count register */
553#define ATA_PIO_LLR (*(REG32_PTR_T)(0x38E00060)) /* PIO device LBA low register */
554#define ATA_PIO_LMR (*(REG32_PTR_T)(0x38E00064)) /* PIO device LBA middle register */
555#define ATA_PIO_LHR (*(REG32_PTR_T)(0x38E00068)) /* PIO device LBA high register */
556#define ATA_PIO_DVR (*(REG32_PTR_T)(0x38E0006C)) /* PIO device register */
557#define ATA_PIO_CSD (*(REG32_PTR_T)(0x38E00070)) /* PIO device command/status register */
558#define ATA_PIO_DAD (*(REG32_PTR_T)(0x38E00074)) /* PIO control/alternate status register */
559#define ATA_PIO_READY (*(REG32_PTR_T)(0x38E00078)) /* PIO data read/write ready */
560#define ATA_PIO_RDATA (*(REG32_PTR_T)(0x38E0007C)) /* PIO read data from device register */
561#define BUS_FIFO_STATUS (*(REG32_PTR_T)(0x38E00080)) /* Reserved */
562#define ATA_FIFO_STATUS (*(REG32_PTR_T)(0x38E00084)) /* Reserved */
563
564/* 29. CHIP ID */
565#define REG_ONE (*(REG32_PTR_T)(0x3D100000)) /* Receive the first 32 bits from a fuse box */
566#define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */
567
diff --git a/firmware/export/system.h b/firmware/export/system.h
index dc3853211b..2f6ceb3c22 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -35,6 +35,8 @@ struct flash_header {
35 char version[32]; 35 char version[32];
36}; 36};
37 37
38void UIE(unsigned int pc, unsigned int num);
39
38bool detect_flashed_romimage(void); 40bool detect_flashed_romimage(void);
39bool detect_flashed_ramimage(void); 41bool detect_flashed_ramimage(void);
40bool detect_original_firmware(void); 42bool detect_original_firmware(void);
diff --git a/firmware/system.c b/firmware/system.c
index 7163468cf6..389ecea80a 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -233,12 +233,18 @@ static const char* const uiename[] = {
233 "Divide by zero" 233 "Divide by zero"
234}; 234};
235 235
236int bla(int arg)
237{
238 return arg+1;
239}
240
236/* Unexpected Interrupt or Exception handler. Currently only deals with 241/* Unexpected Interrupt or Exception handler. Currently only deals with
237 exceptions, but will deal with interrupts later. 242 exceptions, but will deal with interrupts later.
238 */ 243 */
239void UIE(unsigned int pc, unsigned int num) __attribute__((noreturn)); 244void UIE(unsigned int pc, unsigned int num) __attribute__((noreturn));
240void UIE(unsigned int pc, unsigned int num) 245void UIE(unsigned int pc, unsigned int num)
241{ 246{
247#warning got here
242 char str[32]; 248 char str[32];
243 249
244 lcd_clear_display(); 250 lcd_clear_display();
diff --git a/firmware/target/arm/s5l8700/ata-nand-s5l8700.c b/firmware/target/arm/s5l8700/ata-nand-s5l8700.c
new file mode 100644
index 0000000000..dd0ae7a950
--- /dev/null
+++ b/firmware/target/arm/s5l8700/ata-nand-s5l8700.c
@@ -0,0 +1,94 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2007 Dave Chapman
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#include "ata.h"
20#include "ata-target.h"
21#include "ata_idle_notify.h"
22#include "system.h"
23#include <string.h>
24#include "thread.h"
25#include "led.h"
26#include "disk.h"
27#include "panic.h"
28#include "usb.h"
29
30/* for compatibility */
31int ata_spinup_time = 0;
32
33long last_disk_activity = -1;
34
35/** static, private data **/
36static bool initialized = false;
37
38static long next_yield = 0;
39#define MIN_YIELD_PERIOD 2000
40
41/* API Functions */
42
43void ata_led(bool onoff)
44{
45 led(onoff);
46}
47
48int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int incount,
49 void* inbuf)
50{
51
52}
53
54int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count,
55 const void* outbuf)
56{
57}
58
59void ata_spindown(int seconds)
60{
61 (void)seconds;
62}
63
64bool ata_disk_is_active(void)
65{
66 return 0;
67}
68
69void ata_sleep(void)
70{
71}
72
73void ata_spin(void)
74{
75}
76
77/* Hardware reset protocol as specified in chapter 9.1, ATA spec draft v5 */
78int ata_hard_reset(void)
79{
80 return 0;
81}
82
83int ata_soft_reset(void)
84{
85 return 0;
86}
87
88void ata_enable(bool on)
89{
90}
91
92int ata_init(void)
93{
94}
diff --git a/firmware/target/arm/s5l8700/boot.lds b/firmware/target/arm/s5l8700/boot.lds
new file mode 100644
index 0000000000..757abaa11a
--- /dev/null
+++ b/firmware/target/arm/s5l8700/boot.lds
@@ -0,0 +1,54 @@
1#include "config.h"
2
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/s5l8700/crt0.o)
7
8/* DRAMORIG is in fact 0x8000000 but remapped to 0x0 */
9#define DRAMORIG 0x0
10#define DRAMSIZE 16M
11#
12#define IRAMORIG 0x22000000
13#define IRAMSIZE 256K
14
15/* This is not available in all versions of the S5L8700 */
16#define FLASHORIG 0x24000000
17#define FLASHSIZE 1M
18
19SECTIONS
20{
21 . = IRAMORIG;
22
23 .text : {
24 *(.init.text)
25 *(.text*)
26 }
27
28 .data : {
29 *(.icode)
30 *(.irodata)
31 *(.idata)
32 *(.data*)
33 *(.ncdata*);
34 _dataend = . ;
35 }
36
37 .stack :
38 {
39 *(.stack)
40 _stackbegin = .;
41 stackbegin = .;
42 . += 0x2000;
43 _stackend = .;
44 stackend = .;
45 }
46
47 .bss : {
48 _edata = .;
49 *(.bss*);
50 *(.ibss);
51 *(.ncbss*);
52 _end = .;
53 }
54}
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S
new file mode 100644
index 0000000000..3ecabdeaef
--- /dev/null
+++ b/firmware/target/arm/s5l8700/crt0.S
@@ -0,0 +1,117 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Marcoen Hirschberg
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#include "config.h"
20#include "cpu.h"
21
22 .section .init.text,"ax",%progbits
23
24 .global start
25start:
26 /* Exception vectors */
27 b newstart
28 b undef_instr_handler
29 b software_int_handler
30 b prefetch_abort_handler
31 b data_abort_handler
32 b reserved_handler
33 b irq_handler
34 b fiq_handler
35 .word 0x43554644 /* DFUC */
36
37newstart:
38#if 0
39 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
40
41 /* Initialise bss section to zero */
42 ldr r2, =_edata
43 ldr r3, =_end
44 mov r4, #0
451:
46 cmp r3, r2
47 strhi r4, [r2], #4
48 bhi 1b
49
50 /* Set up some stack and munge it with 0xdeadbeef */
51 ldr sp, =stackend
52 ldr r2, =stackbegin
53 ldr r3, =0xdeadbeef
541:
55 cmp sp, r2
56 strhi r3, [r2], #4
57 bhi 1b
58
59 /* Set up stack for IRQ mode */
60 msr cpsr_c, #0xd2
61 ldr sp, =irq_stack
62
63 /* Set up stack for FIQ mode */
64 msr cpsr_c, #0xd1
65 ldr sp, =fiq_stack
66
67 /* Let abort and undefined modes use IRQ stack */
68 msr cpsr_c, #0xd7
69 ldr sp, =irq_stack
70 msr cpsr_c, #0xdb
71 ldr sp, =irq_stack
72
73 /* Switch back to supervisor mode */
74 msr cpsr_c, #0xd3
75#endif
76 bl main
77
78
79 .text
80/* .global UIE*/
81
82/* All illegal exceptions call into UIE with exception address as first
83 * parameter. This is calculated differently depending on which exception
84 * we're in. Second parameter is exception number, used for a string lookup
85 * in UIE. */
86undef_instr_handler:
87 mov r0, lr
88 mov r1, #0
89 b UIE
90
91/* We run supervisor mode most of the time, and should never see a software
92 * exception being thrown. Perhaps make it illegal and call UIE? */
93software_int_handler:
94reserved_handler:
95 movs pc, lr
96
97prefetch_abort_handler:
98 sub r0, lr, #4
99 mov r1, #1
100 b UIE
101
102data_abort_handler:
103 sub r0, lr, #8
104 mov r1, #2
105 b UIE
106
107/* 256 words of IRQ stack */
108 .space 256*4
109irq_stack:
110
111/* 256 words of FIQ stack */
112 .space 256*4
113fiq_stack:
114
115end:
116 /*.word 0xA5A5A5A5
117 .word 0x5A5A5A5A*/
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h
new file mode 100644
index 0000000000..c0a069ac0c
--- /dev/null
+++ b/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h
@@ -0,0 +1,33 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by Barry Wardell
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#ifndef _ADC_TARGET_H_
20#define _ADC_TARGET_H_
21
22/* only two channels used by the Gigabeat */
23#define NUM_ADC_CHANNELS 1
24
25#define ADC_UNKNOWN_1 0
26#define ADC_UNKNOWN_2 1
27#define ADC_BATTERY 2
28#define ADC_UNKNOWN_4 3
29
30#define ADC_UNREG_POWER ADC_BATTERY /* For compatibility */
31#define ADC_READ_ERROR 0xFFFF
32
33#endif
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/backlight-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/backlight-target.h
new file mode 100644
index 0000000000..1dc334cffa
--- /dev/null
+++ b/firmware/target/arm/s5l8700/meizu-m6sl/backlight-target.h
@@ -0,0 +1,27 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Marcoen Hirschberg
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#ifndef BACKLIGHT_TARGET_H
20#define BACKLIGHT_TARGET_H
21
22bool _backlight_init(void);
23void _backlight_on(void);
24void _backlight_off(void);
25void _backlight_set_brightness(int brightness);
26
27#endif
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h
new file mode 100644
index 0000000000..7d0d7a1c4d
--- /dev/null
+++ b/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h
@@ -0,0 +1,52 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by Linus Nielsen Feltzing
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#ifndef _BUTTON_TARGET_H_
20#define _BUTTON_TARGET_H_
21
22#include <stdbool.h>
23#include "config.h"
24
25#define HAS_BUTTON_HOLD
26
27bool button_hold(void);
28void button_init_device(void);
29int button_read_device(void);
30
31/* Toshiba Gigabeat specific button codes */
32
33#define BUTTON_LEFT 0x00000001
34#define BUTTON_RIGHT 0x00000002
35#define BUTTON_UP 0x00000004
36#define BUTTON_DOWN 0x00000008
37
38#define BUTTON_SELECT 0x00000010
39
40#define BUTTON_MENU 0x00000020
41#define BUTTON_PLAY 0x00000040
42
43
44#define BUTTON_MAIN (BUTTON_MENU|BUTTON_LEFT|BUTTON_RIGHT\
45 |BUTTON_UP|BUTTON_DOWN|BUTTON_SELECT|BUTTON_PLAY)
46
47#define BUTTON_REMOTE 0
48
49#define POWEROFF_BUTTON BUTTON_PLAY
50#define POWEROFF_COUNT 10
51
52#endif /* _BUTTON_TARGET_H_ */
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c b/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c
new file mode 100644
index 0000000000..8e5a4f472a
--- /dev/null
+++ b/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c
@@ -0,0 +1,133 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2002 by Alan Korr
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#include "config.h"
20
21#include "hwcompat.h"
22#include "kernel.h"
23#include "lcd.h"
24#include "system.h"
25#include "cpu.h"
26
27/*** definitions ***/
28
29
30/** globals **/
31
32static int xoffset; /* needed for flip */
33
34/*** hardware configuration ***/
35
36int lcd_default_contrast(void)
37{
38 return 0x1f;
39}
40
41void lcd_set_contrast(int val)
42{
43}
44
45void lcd_set_invert_display(bool yesno)
46{
47}
48
49/* turn the display upside down (call lcd_update() afterwards) */
50void lcd_set_flip(bool yesno)
51{
52 /* TODO: flip mode isn't working. The commands in the else part of
53 this function are how the original firmware inits the LCD */
54
55 if (yesno)
56 {
57 xoffset = 132 - LCD_WIDTH; /* 132 colums minus the 128 we have */
58 }
59 else
60 {
61 xoffset = 0;
62 }
63}
64
65
66/* LCD init */
67void lcd_init_device(void)
68{
69}
70
71/*** Update functions ***/
72
73/* Performance function that works with an external buffer
74 note that by and bheight are in 8-pixel units! */
75void lcd_blit_mono(const unsigned char *data, int x, int by, int width,
76 int bheight, int stride)
77{
78 /* Copy display bitmap to hardware */
79 while (bheight--)
80 {
81 }
82}
83
84
85/* Performance function that works with an external buffer
86 note that by and bheight are in 8-pixel units! */
87void lcd_blit_grey_phase_blit(unsigned char *values, unsigned char *phases,
88 int x, int by, int width, int bheight, int stride)
89{
90 (void)values;
91 (void)phases;
92 (void)x;
93 (void)by;
94 (void)width;
95 (void)bheight;
96 (void)stride;
97}
98
99/* Update the display.
100 This must be called after all other LCD functions that change the display. */
101void lcd_update(void) ICODE_ATTR;
102void lcd_update(void)
103{
104 int y;
105
106 /* Copy display bitmap to hardware */
107 for (y = 0; y < LCD_FBHEIGHT; y++)
108 {
109 }
110}
111
112/* Update a fraction of the display. */
113void lcd_update_rect(int, int, int, int) ICODE_ATTR;
114void lcd_update_rect(int x, int y, int width, int height)
115{
116 int ymax;
117
118 /* The Y coordinates have to work on even 8 pixel rows */
119 ymax = (y + height-1) >> 3;
120 y >>= 3;
121
122 if(x + width > LCD_WIDTH)
123 width = LCD_WIDTH - x;
124 if (width <= 0)
125 return; /* nothing left to do, 0 is harmful to lcd_write_data() */
126 if(ymax >= LCD_FBHEIGHT)
127 ymax = LCD_FBHEIGHT-1;
128
129 /* Copy specified rectange bitmap to hardware */
130 for (; y <= ymax; y++)
131 {
132 }
133}
diff --git a/firmware/target/arm/s5l8700/system-s5l8700.c b/firmware/target/arm/s5l8700/system-s5l8700.c
new file mode 100644
index 0000000000..2d87cc8c9a
--- /dev/null
+++ b/firmware/target/arm/s5l8700/system-s5l8700.c
@@ -0,0 +1,168 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2007 by Rob Purchase
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "kernel.h"
21#include "system.h"
22#include "panic.h"
23
24#define default_interrupt(name) \
25 extern __attribute__((weak,alias("UIRQ"))) void name (void)
26
27void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
28void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
29
30default_interrupt(EXT0);
31default_interrupt(EXT1);
32default_interrupt(EXT2);
33default_interrupt(EINT_VBUS);
34default_interrupt(EINTG);
35default_interrupt(INT_TIMERA);
36default_interrupt(INT_WDT);
37default_interrupt(INT_TIMERB);
38default_interrupt(INT_TIMERC);
39default_interrupt(INT_TIMERD);
40default_interrupt(INT_DMA);
41default_interrupt(INT_ALARM_RTC);
42default_interrupt(INT_PRI_RTC);
43default_interrupt(RESERVED1);
44default_interrupt(INT_UART);
45default_interrupt(INT_USB_HOST);
46default_interrupt(INT_USB_FUNC);
47default_interrupt(INT_LCDC_0);
48default_interrupt(INT_LCDC_1);
49default_interrupt(INT_ECC);
50default_interrupt(INT_CALM);
51default_interrupt(INT_ATA);
52default_interrupt(INT_UART0);
53default_interrupt(INT_SPDIF_OUT);
54default_interrupt(INT_SDCI);
55default_interrupt(INT_LCD);
56default_interrupt(INT_SPI);
57default_interrupt(INT_IIC);
58default_interrupt(RESERVED2);
59default_interrupt(INT_MSTICK);
60default_interrupt(INT_ADC_WAKEUP);
61default_interrupt(INT_ADC);
62
63
64
65static void (* const irqvector[])(void) =
66{
67 EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB,
68 INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
69 INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
70 INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
71};
72
73static const char * const irqname[] =
74{
75 "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB",
76 "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
77 "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
78 "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
79};
80
81static void UIRQ(void)
82{
83 unsigned int offset = INTOFFSET;
84 panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
85}
86
87void irq_handler(void)
88{
89 /*
90 * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
91 */
92
93 asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
94 "sub sp, sp, #8 \n"); /* Reserve stack */
95
96 int irq_no = INTOFFSET; /* Read clears the corresponding IRQ status */
97
98 if ((irq_no & (1<<31)) == 0) /* Ensure invalid flag is not set */
99 {
100 irqvector[irq_no]();
101 }
102
103 asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
104 "ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
105 "subs pc, lr, #4 \n"); /* Return from IRQ */
106}
107
108void fiq_handler(void)
109{
110 asm volatile (
111 "subs pc, lr, #4 \r\n"
112 );
113}
114
115
116static void gpio_init(void)
117{
118}
119
120static void clock_init(void)
121{
122}
123
124
125void system_init(void)
126{
127}
128
129void system_reboot(void)
130{
131}
132
133int system_memory_guard(int newmode)
134{
135 (void)newmode;
136 return 0;
137}
138
139#ifdef HAVE_ADJUSTABLE_CPU_FREQ
140
141void set_cpu_frequency(long frequency)
142{
143 if (cpu_frequency == frequency)
144 return;
145
146 /* CPU/COP frequencies can be scaled between Fbus (min) and Fsys (max).
147 Fbus should not be set below ~32Mhz with LCD enabled or the display
148 will be garbled. */
149 if (frequency == CPUFREQ_MAX)
150 {
151 }
152 else if (frequency == CPUFREQ_NORMAL)
153 {
154 }
155 else
156 {
157 }
158
159 asm volatile (
160 "nop \n\t"
161 "nop \n\t"
162 "nop \n\t"
163 );
164
165 cpu_frequency = frequency;
166}
167
168#endif
diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h
new file mode 100644
index 0000000000..158bc44190
--- /dev/null
+++ b/firmware/target/arm/s5l8700/system-target.h
@@ -0,0 +1,35 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2007 by Dave Chapman
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#ifndef SYSTEM_TARGET_H
20#define SYSTEM_TARGET_H
21
22#include "system-arm.h"
23
24#define CPUFREQ_DEFAULT 32000000
25#define CPUFREQ_NORMAL 48000000
26#define CPUFREQ_MAX 192000000
27
28#define inl(a) (*(volatile unsigned long *) (a))
29#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
30#define inb(a) (*(volatile unsigned char *) (a))
31#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
32#define inw(a) (*(volatile unsigned short *) (a))
33#define outw(a,b) (*(volatile unsigned short *) (b) = (a))
34
35#endif /* SYSTEM_TARGET_H */
diff --git a/tools/configure b/tools/configure
index 3d9afdbfda..6410f9043f 100755
--- a/tools/configure
+++ b/tools/configure
@@ -248,6 +248,14 @@ arm9tdmicc () {
248 gccchoice="4.0.3" 248 gccchoice="4.0.3"
249} 249}
250 250
251arm940tbecc () {
252 prefixtools arm-elf-
253 GCCOPTS="$CCOPTS -mbig-endian -mcpu=arm940t -mlong-calls"
254 GCCOPTIMIZE="-fomit-frame-pointer"
255 endian="big"
256 gccchoice="4.0.3"
257}
258
251arm946cc () { 259arm946cc () {
252 prefixtools arm-elf- 260 prefixtools arm-elf-
253 GCCOPTS="$CCOPTS -mcpu=arm9e -mlong-calls" 261 GCCOPTS="$CCOPTS -mcpu=arm9e -mlong-calls"
@@ -676,12 +684,10 @@ cat <<EOF
676 ==Tatung== ==Olympus== ==Logik== 684 ==Tatung== ==Olympus== ==Logik==
677 60) Elio TPJ-1022 70) M:Robe 500 80) DAX 1GB MP3/DAB 685 60) Elio TPJ-1022 70) M:Robe 500 80) DAX 1GB MP3/DAB
678 71) M:Robe 100 686 71) M:Robe 100
679 687 ==Creative== ==Philips== ==Meizu==
680 ==Creative== ==Philips== 688 90) Zen Vision:M 30GB 100) GoGear SA9200 110) M6SL
681 90) Zen Vision:M 30GB 100) GoGear SA9200
682 91) Zen Vision:M 60GB 101) GoGear HDD1630 689 91) Zen Vision:M 60GB 101) GoGear HDD1630
683 92) Zen Vision 690 92) Zen Vision
684
685EOF 691EOF
686 692
687 buildfor=`input`; 693 buildfor=`input`;
@@ -1720,6 +1726,27 @@ fi
1720 t_model="hdd1630" 1726 t_model="hdd1630"
1721 ;; 1727 ;;
1722 1728
1729 110|meizum6sl)
1730 target_id=20
1731 modelname="meizum6sl"
1732 target="-DMEIZU_M6SL"
1733 memory=16 # always
1734 arm940tbecc
1735 tool="cp"
1736 bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
1737 bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
1738 output="rockbox.meizu"
1739 appextra="recorder:gui"
1740 plugins="no" #FIXME
1741 swcodec="yes"
1742 toolset=$genericbitmaptools
1743 boottool="cp"
1744 bootoutput="rockboot.ebn"
1745 # architecture, manufacturer and model for the target-tree build
1746 t_cpu="arm"
1747 t_manufacturer="s5l8700"
1748 t_model="meizu-m6sl"
1749 ;;
1723 *) 1750 *)
1724 echo "Please select a supported target platform!" 1751 echo "Please select a supported target platform!"
1725 exit 1752 exit
diff --git a/tools/makesrc.inc b/tools/makesrc.inc
index 846df8cb9e..be9c34e16b 100644
--- a/tools/makesrc.inc
+++ b/tools/makesrc.inc
@@ -11,4 +11,5 @@
11 11
12SRC := $(shell cat SOURCES | $(CC) -DMEMORYSIZE=$(MEMORYSIZE) $(INCLUDES) \ 12SRC := $(shell cat SOURCES | $(CC) -DMEMORYSIZE=$(MEMORYSIZE) $(INCLUDES) \
13$(TARGET) $(DEFINES) $(EXTRA_DEFINES) -E -P -include "config.h" - 2>/dev/null \ 13$(TARGET) $(DEFINES) $(EXTRA_DEFINES) -E -P -include "config.h" - 2>/dev/null \
14| grep -v "^\#") 14| grep -v "^\#" | xargs ls)
15#| grep -v "^\#")
diff --git a/tools/rockboxdev.sh b/tools/rockboxdev.sh
index fd4982b96e..77442c8efc 100755
--- a/tools/rockboxdev.sh
+++ b/tools/rockboxdev.sh
@@ -2,7 +2,7 @@
2 2
3# this is where this script will store downloaded files and check for already 3# this is where this script will store downloaded files and check for already
4# downloaded files 4# downloaded files
5dlwhere="/tmp/rbdev-dl" 5dlwhere="/usr/tmp/rbdev-dl"
6 6
7# will append the target string to the prefix dir mentioned here 7# will append the target string to the prefix dir mentioned here
8# Note that the user running this script must be able to do make install in 8# Note that the user running this script must be able to do make install in
@@ -12,7 +12,7 @@ prefix="/usr/local"
12 12
13# This directory is used to extract all files and to build everything in. It 13# This directory is used to extract all files and to build everything in. It
14# must not exist before this script is invoked (as a security measure). 14# must not exist before this script is invoked (as a security measure).
15builddir="/tmp/rbdev-build" 15builddir="/usr/tmp/rbdev-build"
16 16
17# This script needs to use GNU Make. On Linux systems, GNU Make is invoked 17# This script needs to use GNU Make. On Linux systems, GNU Make is invoked
18# by running the "make" command, on most BSD systems, GNU Make is invoked 18# by running the "make" command, on most BSD systems, GNU Make is invoked
diff --git a/uisimulator/sdl/button.c b/uisimulator/sdl/button.c
index ba384b31b4..ee1117481b 100644
--- a/uisimulator/sdl/button.c
+++ b/uisimulator/sdl/button.c
@@ -802,6 +802,7 @@ void button_event(int key, bool pressed)
802 case SDLK_KP_ENTER: 802 case SDLK_KP_ENTER:
803 new_btn = BUTTON_MENU; 803 new_btn = BUTTON_MENU;
804 break; 804 break;
805
805#elif CONFIG_KEYPAD == CREATIVEZVM_PAD 806#elif CONFIG_KEYPAD == CREATIVEZVM_PAD
806 case SDLK_KP1: 807 case SDLK_KP1:
807 new_btn = BUTTON_BACK; 808 new_btn = BUTTON_BACK;
@@ -886,6 +887,34 @@ void button_event(int key, bool pressed)
886 break; 887 break;
887 case SDLK_s: 888 case SDLK_s:
888 new_btn = BUTTON_VOL_UP; 889 new_btn = BUTTON_VOL_UP;
890
891#elif CONFIG_KEYPAD == MEIZU_M6SL_PAD
892 case SDLK_KP1:
893 new_btn = BUTTON_PREV;
894 break;
895 case SDLK_KP3:
896 new_btn = BUTTON_NEXT;
897 break;
898 case SDLK_KP_ENTER:
899 case SDLK_RETURN:
900 case SDLK_a:
901 new_btn = BUTTON_PLAY;
902 break;
903 case SDLK_KP_PERIOD:
904 case SDLK_INSERT:
905 new_btn = BUTTON_MENU;
906 break;
907 case SDLK_KP8:
908 case SDLK_UP:
909 new_btn = BUTTON_UP;
910 break;
911 case SDLK_KP2:
912 case SDLK_DOWN:
913 new_btn = BUTTON_DOWN;
914 break;
915 case SDLK_KP5:
916 case SDLK_SPACE:
917 new_btn = BUTTON_SELECT;
889 break; 918 break;
890#else 919#else
891#error No keymap defined! 920#error No keymap defined!
diff --git a/uisimulator/sdl/uisdl.h b/uisimulator/sdl/uisdl.h
index abd320ad18..dde505bf91 100644
--- a/uisimulator/sdl/uisdl.h
+++ b/uisimulator/sdl/uisdl.h
@@ -404,6 +404,19 @@
404#define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */ 404#define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */
405#define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */ 405#define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */
406 406
407#elif defined(MEIZU_M6SL)
408#define UI_TITLE "Meizu M6"
409#define UI_WIDTH 512 /* width of GUI window */
410#define UI_HEIGHT 322 /* height of GUI window */
411#define UI_LCD_POSX 39 /* x position of lcd */
412#define UI_LCD_POSY 38 /* y position of lcd */
413#define UI_LCD_WIDTH 320
414#define UI_LCD_HEIGHT 240
415#define UI_LCD_BGCOLOR 32, 32, 32 /* bkgnd color of LCD (no backlight) */
416#define UI_LCD_BGCOLORLIGHT 192, 192, 192 /* bkgnd color of LCD (backlight) */
417#define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */
418#define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */
419
407#endif 420#endif
408extern SDL_Surface *gui_surface; 421extern SDL_Surface *gui_surface;
409extern bool background; /* True if the background image is enabled */ 422extern bool background; /* True if the background image is enabled */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-02 21:28:01 +0000