diff options
Diffstat (limited to 'firmware/export/s5l8700.h')
| -rw-r--r-- | firmware/export/s5l8700.h | 567 |
1 files changed, 567 insertions, 0 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h new file mode 100644 index 0000000000..211564e153 --- /dev/null +++ b/firmware/export/s5l8700.h | |||
| @@ -0,0 +1,567 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * $Id: S5L8700X.h 2008-03-27 Marcoen Hirschberg, Bart van Adrichem $ | ||
| 9 | * | ||
| 10 | * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem | ||
| 11 | * | ||
| 12 | * All files in this archive are subject to the GNU General Public License. | ||
| 13 | * See the file COPYING in the source tree root for full license agreement. | ||
| 14 | * | ||
| 15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 16 | * KIND, either express or implied. | ||
| 17 | * | ||
| 18 | ****************************************************************************/ | ||
| 19 | |||
| 20 | #define REG8_PTR_T volatile uint8_t * | ||
| 21 | #define REG16_PTR_T volatile uint16_t * | ||
| 22 | #define REG32_PTR_T volatile uint32_t * | ||
| 23 | |||
| 24 | /* 04. CALMADM2E */ | ||
| 25 | |||
| 26 | /* Following registers are mapped on IO Area in data memory area of Calm. */ | ||
| 27 | #define CONFIG0 (*(REG16_PTR_T)(0x3F000000)) /* configuration/control register 0 */ | ||
| 28 | #define CONFIG1 (*(REG16_PTR_T)(0x3F000002)) /* configuration/control register 1*/ | ||
| 29 | #define COMMUN (*(REG16_PTR_T)(0x3F000004)) /* Communication Control Register */ | ||
| 30 | #define DDATA0 (*(REG16_PTR_T)(0x3F000006)) /* Communication data from host to ADM */ | ||
| 31 | #define DDATA1 (*(REG16_PTR_T)(0x3F000008)) /* Communication data from host to ADM */ | ||
| 32 | #define DDATA2 (*(REG16_PTR_T)(0x3F00000A)) /* Communication data from host to ADM */ | ||
| 33 | #define DDATA3 (*(REG16_PTR_T)(0x3F00000C)) /* Communication data from host to ADM */ | ||
| 34 | #define DDATA4 (*(REG16_PTR_T)(0x3F00000E)) /* Communication data from host to ADM */ | ||
| 35 | #define DDATA5 (*(REG16_PTR_T)(0x3F000010)) /* Communication data from host to ADM */ | ||
| 36 | #define DDATA6 (*(REG16_PTR_T)(0x3F000012)) /* Communication data from host to ADM */ | ||
| 37 | #define DDATA7 (*(REG16_PTR_T)(0x3F000014)) /* Communication data from host to ADM */ | ||
| 38 | #define UDATA0 (*(REG16_PTR_T)(0x3F000016)) /* Communication data from ADM to host */ | ||
| 39 | #define UDATA1 (*(REG16_PTR_T)(0x3F000018)) /* Communication data from ADM to host */ | ||
| 40 | #define UDATA2 (*(REG16_PTR_T)(0x3F00001A)) /* Communication data from ADM to host */ | ||
| 41 | #define UDATA3 (*(REG16_PTR_T)(0x3F00001C)) /* Communication data from ADM to host */ | ||
| 42 | #define UDATA4 (*(REG16_PTR_T)(0x3F00001E)) /* Communication data from ADM to host */ | ||
| 43 | #define UDATA5 (*(REG16_PTR_T)(0x3F000020)) /* Communication data from ADM to host */ | ||
| 44 | #define UDATA6 (*(REG16_PTR_T)(0x3F000022)) /* Communication data from ADM to host */ | ||
| 45 | #define UDATA7 (*(REG16_PTR_T)(0x3F000024)) /* Communication data from ADM to host */ | ||
| 46 | #define IBASE_H (*(REG16_PTR_T)(0x3F000026)) /* Higher half of start address for ADM instruction area */ | ||
| 47 | #define IBASE_L (*(REG16_PTR_T)(0x3F000028)) /* Lower half of start address for ADM instruction area */ | ||
| 48 | #define DBASE_H (*(REG16_PTR_T)(0x3F00002A)) /* Higher half of start address for CalmRISC data area */ | ||
| 49 | #define DBASE_L (*(REG16_PTR_T)(0x3F00002C)) /* Lower half of start address for CalmRISC data area */ | ||
| 50 | #define XBASE_H (*(REG16_PTR_T)(0x3F00002E)) /* Higher half of start address for Mac X area */ | ||
| 51 | #define XBASE_L (*(REG16_PTR_T)(0x3F000030)) /* Lower half of start address for Mac X area */ | ||
| 52 | #define YBASE_H (*(REG16_PTR_T)(0x3F000032)) /* Higher half of start address for Mac Y area */ | ||
| 53 | #define YBASE_L (*(REG16_PTR_T)(0x3F000034)) /* Lower half of start address for Mac Y area */ | ||
| 54 | #define S0BASE_H (*(REG16_PTR_T)(0x3F000036)) /* Higher half of start address for sequential buffer 0 area */ | ||
| 55 | #define S0BASE_L (*(REG16_PTR_T)(0x3F000038)) /* Lower half of start address for sequential buffer 0 area */ | ||
| 56 | #define S1BASE_H (*(REG16_PTR_T)(0x3F00003A)) /* Higher half of start address for sequential buffer 1 area */ | ||
| 57 | #define S1BASE_L (*(REG16_PTR_T)(0x3F00003C)) /* Lower half of start address for sequential buffer 1 area */ | ||
| 58 | #define CACHECON (*(REG16_PTR_T)(0x3F00003E)) /* Cache Control Register */ | ||
| 59 | #define CACHESTAT (*(REG16_PTR_T)(0x3F000040)) /* Cache status register */ | ||
| 60 | #define SBFCON (*(REG16_PTR_T)(0x3F000042)) /* Sequential Buffer Control Register */ | ||
| 61 | #define SBFSTAT (*(REG16_PTR_T)(0x3F000044)) /* Sequential Buffer Status Register */ | ||
| 62 | #define SBL0OFF_H (*(REG16_PTR_T)(0x3F000046)) /* Higher bits of Offset register of sequential block 0 area */ | ||
| 63 | #define SBL0OFF_L (*(REG16_PTR_T)(0x3F000048)) /* Lower bits of Offset register of sequential block 0 area */ | ||
| 64 | #define SBL1OFF_H (*(REG16_PTR_T)(0x3F00004A)) /* Higher bits of Offset register of sequential block 1 area */ | ||
| 65 | #define SBL1OFF_L (*(REG16_PTR_T)(0x3F00004C)) /* Lower bits of Offset register of sequential block 1 area */ | ||
| 66 | #define SBL0BEGIN_H (*(REG16_PTR_T)(0x3F00004E)) /* Higher bits of Begin Offset of sequential block 0 area in ring mode */ | ||
| 67 | #define SBL0BEGIN_L (*(REG16_PTR_T)(0x3F000050)) /* Lower bits of Begin Offset of sequential block 0 area in ring mode */ | ||
| 68 | #define SBL1BEGIN_H (*(REG16_PTR_T)(0x3F000052)) /* Higher bits of Begin Offset of sequential block 1 area in ring mode */ | ||
| 69 | #define SBL1BEGIN_L (*(REG16_PTR_T)(0x3F000054)) /* Lower bits of Begin Offset of sequential block 1 area in ring mode */ | ||
| 70 | #define SBL0END_H (*(REG16_PTR_T)(0x3F000056)) /* Lower bits of End Offset of sequential block 0 area in ring mode */ | ||
| 71 | #define SBL0END_L (*(REG16_PTR_T)(0x3F000058)) /* Higher bits of End Offset of sequential block 0 area in ring mode */ | ||
| 72 | #define SBL1END_H (*(REG16_PTR_T)(0x3F00005A)) /* Lower bits of End Offset of sequential block 1 area in ring mode */ | ||
| 73 | #define SBL1END_L (*(REG16_PTR_T)(0x3F00005C)) /* Higher bits of End Offset of sequential block 1 area in ring mode */ | ||
| 74 | |||
| 75 | /* Following registers are components of SFRS of the target system */ | ||
| 76 | #define ADM_CONFIG (*(REG32_PTR_T)(0x39000000)) /* Configuration/Control Register */ | ||
| 77 | #define ADM_COMMUN (*(REG32_PTR_T)(0x39000004)) /* Communication Control Register */ | ||
| 78 | #define ADM_DDATA0 (*(REG32_PTR_T)(0x39000010)) /* Communication data from host to ADM */ | ||
| 79 | #define ADM_DDATA1 (*(REG32_PTR_T)(0x39000014)) /* Communication data from host to ADM */ | ||
| 80 | #define ADM_DDATA2 (*(REG32_PTR_T)(0x39000018)) /* Communication data from host to ADM */ | ||
| 81 | #define ADM_DDATA3 (*(REG32_PTR_T)(0x3900001C)) /* Communication data from host to ADM */ | ||
| 82 | #define ADM_DDATA4 (*(REG32_PTR_T)(0x39000020)) /* Communication data from host to ADM */ | ||
| 83 | #define ADM_DDATA5 (*(REG32_PTR_T)(0x39000024)) /* Communication data from host to ADM */ | ||
| 84 | #define ADM_DDATA6 (*(REG32_PTR_T)(0x39000028)) /* Communication data from host to ADM */ | ||
| 85 | #define ADM_DDATA7 (*(REG32_PTR_T)(0x3900002C)) /* Communication data from host to ADM */ | ||
| 86 | #define ADM_UDATA0 (*(REG32_PTR_T)(0x39000030)) /* Communication data from ADM to host */ | ||
| 87 | #define ADM_UDATA1 (*(REG32_PTR_T)(0x39000034)) /* Communication data from ADM to host */ | ||
| 88 | #define ADM_UDATA2 (*(REG32_PTR_T)(0x39000038)) /* Communication data from ADM to host */ | ||
| 89 | #define ADM_UDATA3 (*(REG32_PTR_T)(0x3900003C)) /* Communication data from ADM to host */ | ||
| 90 | #define ADM_UDATA4 (*(REG32_PTR_T)(0x39000040)) /* Communication data from ADM to host */ | ||
| 91 | #define ADM_UDATA5 (*(REG32_PTR_T)(0x39000044)) /* Communication data from ADM to host */ | ||
| 92 | #define ADM_UDATA6 (*(REG32_PTR_T)(0x39000048)) /* Communication data from ADM to host */ | ||
| 93 | #define ADM_UDATA7 (*(REG32_PTR_T)(0x3900004C)) /* Communication data from ADM to host */ | ||
| 94 | #define ADM_IBASE (*(REG32_PTR_T)(0x39000050)) /* Start Address for ADM Instruction Area */ | ||
| 95 | #define ADM_DBASE (*(REG32_PTR_T)(0x39000054)) /* Start Address for CalmRISC Data Area */ | ||
| 96 | #define ADM_XBASE (*(REG32_PTR_T)(0x39000058)) /* Start Address for Mac X Area */ | ||
| 97 | #define ADM_YBASE (*(REG32_PTR_T)(0x3900005C)) /* Start Address for Mac Y Area */ | ||
| 98 | #define ADM_S0BASE (*(REG32_PTR_T)(0x39000060)) /* Start Address for Sequential Block 0 Area */ | ||
| 99 | #define ADM_S1BASE (*(REG32_PTR_T)(0x39000064)) /* Start Address for Sequential Block 1 Area */ | ||
| 100 | |||
| 101 | /* 05. CLOCK & POWER MANAGEMENT */ | ||
| 102 | #define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */ | ||
| 103 | #define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */ | ||
| 104 | #define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */ | ||
| 105 | #define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ | ||
| 106 | #define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ | ||
| 107 | #define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ | ||
| 108 | #define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ | ||
| 109 | #define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ | ||
| 110 | #define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */ | ||
| 111 | #define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */ | ||
| 112 | #define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ | ||
| 113 | #define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */ | ||
| 114 | #define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* clock control register 2 */ | ||
| 115 | |||
| 116 | /* 06. INTERRUPT CONTROLLER UNIT */ | ||
| 117 | #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ | ||
| 118 | #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ | ||
| 119 | #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ | ||
| 120 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ | ||
| 121 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ | ||
| 122 | #define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ | ||
| 123 | #define EINTPOL (*(REG32_PTR_T)(0x39C00018)) /* Indicates external interrupt polarity */ | ||
| 124 | #define EINTPEND (*(REG32_PTR_T)(0x39C0001C)) /* Indicates whether external interrupts are pending. */ | ||
| 125 | #define EINTMSK (*(REG32_PTR_T)(0x39C00020)) /* Indicates whether external interrupts are masked */ | ||
| 126 | |||
| 127 | /* 07. MEMORY INTERFACE UNIT (MIU) */ | ||
| 128 | |||
| 129 | /* SDRAM */ | ||
| 130 | #define MIUCON (*(REG32_PTR_T)(0x38200000)) /* External Memory configuration register */ | ||
| 131 | #define MIUCOM (*(REG32_PTR_T)(0x38200004)) /* Command and status register */ | ||
| 132 | #define MIUAREF (*(REG32_PTR_T)(0x38200008)) /* Auto-refresh control register */ | ||
| 133 | #define MIUMRS (*(REG32_PTR_T)(0x3820000C)) /* SDRAM Mode Register Set Value Register */ | ||
| 134 | #define MIUSDPARA (*(REG32_PTR_T)(0x38200010)) /* SDRAM parameter register */ | ||
| 135 | |||
| 136 | /* DDR */ | ||
| 137 | #define MEMCONF (*(REG32_PTR_T)(0x38200020)) /* External Memory configuration register */ | ||
| 138 | #define USRCMD (*(REG32_PTR_T)(0x38200024)) /* Command and Status register */ | ||
| 139 | #define AREF (*(REG32_PTR_T)(0x38200028)) /* Auto-refresh control register */ | ||
| 140 | #define MRS (*(REG32_PTR_T)(0x3820002C)) /* DRAM mode register set value register */ | ||
| 141 | #define DPARAM (*(REG32_PTR_T)(0x38200030)) /* DRAM parameter register (Unit of ‘tXXX’ : tCK */ | ||
| 142 | #define SMEMCONF (*(REG32_PTR_T)(0x38200034)) /* Static memory mode register set value register */ | ||
| 143 | #define MIUS01PARA (*(REG32_PTR_T)(0x38200038)) /* SRAM0, SRAM1 static memory parameter register (In S5L8700, SRAM0 is Nor Flash) */ | ||
| 144 | #define MIUS23PARA (*(REG32_PTR_T)(0x3820003C)) /* SRAM2 and SRAM3 static memory parameter register */ | ||
| 145 | |||
| 146 | #define MIUORG (*(REG32_PTR_T)(0x38200040)) /* SDR/DDR selection */ | ||
| 147 | #define MIUDLYDQS (*(REG32_PTR_T)(0x38200044)) /* DQS/DQS-rst delay parameter */ | ||
| 148 | #define MIUDLYCLK (*(REG32_PTR_T)(0x38200048)) /* SDR/DDR Clock delay parameter */ | ||
| 149 | #define MIU_DSS_SEL_B (*(REG32_PTR_T)(0x3820004C)) /* SSTL2 Drive Strength parameter for Bi-direction signal */ | ||
| 150 | #define MIU_DSS_SEL_O (*(REG32_PTR_T)(0x38200050)) /* SSTL2 Drive Strength parameter for Output signal */ | ||
| 151 | #define MIU_DSS_SEL_C (*(REG32_PTR_T)(0x38200054)) /* SSTL2 Drive Strength parameter for Clock signal */ | ||
| 152 | #define PAD_DSS_SEL_NOR (*(REG32_PTR_T)(0x38200058)) /* Wide range I/O Drive Strength parameter for NOR interface */ | ||
| 153 | #define PAD_DSS_SEL_ATA (*(REG32_PTR_T)(0x3820005C)) /* Wide range I/O Drive Strength parameter for ATA interface */ | ||
| 154 | #define SSTL2_PAD_ON (*(REG32_PTR_T)(0x38200060)) /* SSTL2 pad ON/OFF select */ | ||
| 155 | |||
| 156 | /* 08. IODMA CONTROLLER */ | ||
| 157 | #define DMABASE0 (*(REG32_PTR_T)(0x38400000)) /* Base address register for channel 0 */ | ||
| 158 | #define DMACON0 (*(REG32_PTR_T)(0x38400004)) /* Configuration register for channel 0 */ | ||
| 159 | #define DMATCNT0 (*(REG32_PTR_T)(0x38400008)) /* Transfer count register for channel 0 */ | ||
| 160 | #define DMACADDR0 (*(REG32_PTR_T)(0x3840000C)) /* Current memory address register for channel 0 */ | ||
| 161 | #define DMACTCNT0 (*(REG32_PTR_T)(0x38400010)) /* Current transfer count register for channel 0 */ | ||
| 162 | #define DMACOM0 (*(REG32_PTR_T)(0x38400014)) /* Channel 0 command register */ | ||
| 163 | #define DMANOFF0 (*(REG32_PTR_T)(0x38400018)) /* Channel 0 offset2 register */ | ||
| 164 | #define DMABASE1 (*(REG32_PTR_T)(0x38400020)) /* Base address register for channel 1 */ | ||
| 165 | #define DMACON1 (*(REG32_PTR_T)(0x38400024)) /* Configuration register for channel 1 */ | ||
| 166 | #define DMATCNT1 (*(REG32_PTR_T)(0x38400028)) /* Transfer count register for channel 1 */ | ||
| 167 | #define DMACADDR1 (*(REG32_PTR_T)(0x3840002C)) /* Current memory address register for channel 1 */ | ||
| 168 | #define DMACTCNT1 (*(REG32_PTR_T)(0x38400030)) /* Current transfer count register for channel 1 */ | ||
| 169 | #define DMACOM1 (*(REG32_PTR_T)(0x38400034)) /* Channel 1 command register */ | ||
| 170 | #define DMABASE2 (*(REG32_PTR_T)(0x38400040)) /* Base address register for channel 2 */ | ||
| 171 | #define DMACON2 (*(REG32_PTR_T)(0x38400044)) /* Configuration register for channel 2 */ | ||
| 172 | #define DMATCNT2 (*(REG32_PTR_T)(0x38400048)) /* Transfer count register for channel 2 */ | ||
| 173 | #define DMACADDR2 (*(REG32_PTR_T)(0x3840004C)) /* Current memory address register for channel 2 */ | ||
| 174 | #define DMACTCNT2 (*(REG32_PTR_T)(0x38400050)) /* Current transfer count register for channel 2 */ | ||
| 175 | #define DMACOM2 (*(REG32_PTR_T)(0x38400054)) /* Channel 2 command register */ | ||
| 176 | #define DMABASE3 (*(REG32_PTR_T)(0x38400060)) /* Base address register for channel 3 */ | ||
| 177 | #define DMACON3 (*(REG32_PTR_T)(0x38400064)) /* Configuration register for channel 3 */ | ||
| 178 | #define DMATCNT3 (*(REG32_PTR_T)(0x38400068)) /* Transfer count register for channel 3 */ | ||
| 179 | #define DMACADDR3 (*(REG32_PTR_T)(0x3840006C)) /* Current memory address register for channel 3 */ | ||
| 180 | #define DMACTCNT3 (*(REG32_PTR_T)(0x38400070)) /* Current transfer count register for channel 3 */ | ||
| 181 | #define DMACOM3 (*(REG32_PTR_T)(0x38400074)) /* Channel 3 command register */ | ||
| 182 | #define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */ | ||
| 183 | |||
| 184 | /* 10. REAL TIMER CLOCK (RTC) */ | ||
| 185 | #define RTCCON (*(REG32_PTR_T)(0x3D200000)) /* RTC Control Register */ | ||
| 186 | #define RTCRST (*(REG32_PTR_T)(0x3D200004)) /* RTC Round Reset Register */ | ||
| 187 | #define RTCALM (*(REG32_PTR_T)(0x3D200008)) /* RTC Alarm Control Register */ | ||
| 188 | #define ALMSEC (*(REG32_PTR_T)(0x3D20000C)) /* Alarm Second Data Register */ | ||
| 189 | #define ALMMIN (*(REG32_PTR_T)(0x3D200010)) /* Alarm Minute Data Register */ | ||
| 190 | #define ALMHOUR (*(REG32_PTR_T)(0x3D200014)) /* Alarm Hour Data Register */ | ||
| 191 | #define ALMDATE (*(REG32_PTR_T)(0x3D200018)) /* Alarm Date Data Register */ | ||
| 192 | #define ALMDAY (*(REG32_PTR_T)(0x3D20001C)) /* Alarm Day of Week Data Register */ | ||
| 193 | #define ALMMON (*(REG32_PTR_T)(0x3D200020)) /* Alarm Month Data Register */ | ||
| 194 | #define ALMYEAR (*(REG32_PTR_T)(0x3D200024)) /* Alarm Year Data Register */ | ||
| 195 | #define BCDSEC (*(REG32_PTR_T)(0x3D200028)) /* BCD Second Register */ | ||
| 196 | #define BCDMIN (*(REG32_PTR_T)(0x3D20002C)) /* BCD Minute Register */ | ||
| 197 | #define BCDHOUR (*(REG32_PTR_T)(0x3D200030)) /* BCD Hour Register */ | ||
| 198 | #define BCDDATE (*(REG32_PTR_T)(0x3D200034)) /* BCD Date Register */ | ||
| 199 | #define BCDDAY (*(REG32_PTR_T)(0x3D200038)) /* BCD Day of Week Register */ | ||
| 200 | #define BCDMON (*(REG32_PTR_T)(0x3D20003C)) /* BCD Month Register */ | ||
| 201 | #define BCDYEAR (*(REG32_PTR_T)(0x3D200040)) /* BCD Year Register */ | ||
| 202 | #define RTCIM (*(REG32_PTR_T)(0x3D200044)) /* RTC Interrupt Mode Register */ | ||
| 203 | #define RTCPEND (*(REG32_PTR_T)(0x3D200048)) /* RTC Interrupt Pending Register */ | ||
| 204 | |||
| 205 | /* 09. WATCHDOG TIMER*/ | ||
| 206 | #define WDTCON (*(REG32_PTR_T)(0x3C800000)) /* Control Register */ | ||
| 207 | #define WDTCNT (*(REG32_PTR_T)(0x3C800004)) /* 11-bits internal counter */ | ||
| 208 | |||
| 209 | /* 11. 16 BIT TIMER */ | ||
| 210 | #define TACON (*(REG32_PTR_T)(0x3C700000)) /* Control Register for timer A */ | ||
| 211 | #define TACMD (*(REG32_PTR_T)(0x3C700004)) /* Command Register for timer A */ | ||
| 212 | #define TADATA0 (*(REG32_PTR_T)(0x3C700008)) /* Data0 Register */ | ||
| 213 | #define TADATA1 (*(REG32_PTR_T)(0x3C70000C)) /* Data1 Register */ | ||
| 214 | #define TAPRE (*(REG32_PTR_T)(0x3C700010)) /* Pre-scale register */ | ||
| 215 | #define TACNT (*(REG32_PTR_T)(0x3C700014)) /* Counter register */ | ||
| 216 | #define TBCON (*(REG32_PTR_T)(0x3C700020)) /* Control Register for timer B */ | ||
| 217 | #define TBCMD (*(REG32_PTR_T)(0x3C700024)) /* Command Register for timer B */ | ||
| 218 | #define TBDATA0 (*(REG32_PTR_T)(0x3C700028)) /* Data0 Register */ | ||
| 219 | #define TBDATA1 (*(REG32_PTR_T)(0x3C70002C)) /* Data1 Register */ | ||
| 220 | #define TBPRE (*(REG32_PTR_T)(0x3C700030)) /* Pre-scale register */ | ||
| 221 | #define TBCNT (*(REG32_PTR_T)(0x3C700034)) /* Counter register */ | ||
| 222 | #define TCCON (*(REG32_PTR_T)(0x3C700040)) /* Control Register for timer C */ | ||
| 223 | #define TCCMD (*(REG32_PTR_T)(0x3C700044)) /* Command Register for timer C */ | ||
| 224 | #define TCDATA0 (*(REG32_PTR_T)(0x3C700048)) /* Data0 Register */ | ||
| 225 | #define TCDATA1 (*(REG32_PTR_T)(0x3C70004C)) /* Data1 Register */ | ||
| 226 | #define TCPRE (*(REG32_PTR_T)(0x3C700050)) /* Pre-scale register */ | ||
| 227 | #define TCCNT (*(REG32_PTR_T)(0x3C700054)) /* Counter register */ | ||
| 228 | #define TDCON (*(REG32_PTR_T)(0x3C700060)) /* Control Register for timer D */ | ||
| 229 | #define TDCMD (*(REG32_PTR_T)(0x3C700064)) /* Command Register for timer D */ | ||
| 230 | #define TDDATA0 (*(REG32_PTR_T)(0x3C700068)) /* Data0 Register */ | ||
| 231 | #define TDDATA1 (*(REG32_PTR_T)(0x3C70006C)) /* Data1 Register */ | ||
| 232 | #define TDPRE (*(REG32_PTR_T)(0x3C700070)) /* Pre-scale register */ | ||
| 233 | #define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */ | ||
| 234 | |||
| 235 | /* 12. NAND FLASH CONTROLER */ | ||
| 236 | #define FMCTRL0 (*(REG32_PTR_T)(0x3C200000)) /* Control Register0 */ | ||
| 237 | #define FMCTRL1 (*(REG32_PTR_T)(0x3C200004)) /* Control Register1 */ | ||
| 238 | #define FMCMD (*(REG32_PTR_T)(0x3C200008)) /* Command Register */ | ||
| 239 | #define FMADDR0 (*(REG32_PTR_T)(0x3C20000C)) /* Address Register0 */ | ||
| 240 | #define FMADDR1 (*(REG32_PTR_T)(0x3C200010)) /* Address Register1 */ | ||
| 241 | #define FMADDR2 (*(REG32_PTR_T)(0x3C200014)) /* Address Register2 */ | ||
| 242 | #define FMADDR3 (*(REG32_PTR_T)(0x3C200018)) /* Address Register3 */ | ||
| 243 | #define FMADDR4 (*(REG32_PTR_T)(0x3C20001C)) /* Address Register4 */ | ||
| 244 | #define FMADDR5 (*(REG32_PTR_T)(0x3C200020)) /* Address Register5 */ | ||
| 245 | #define FMADDR6 (*(REG32_PTR_T)(0x3C200024)) /* Address Register6 */ | ||
| 246 | #define FMADDR7 (*(REG32_PTR_T)(0x3C200028)) /* Address Register7 */ | ||
| 247 | #define FMANUM (*(REG32_PTR_T)(0x3C20002C)) /* Address Counter Register */ | ||
| 248 | #define FMDNUM (*(REG32_PTR_T)(0x3C200030)) /* Data Counter Register */ | ||
| 249 | #define FMDATAW0 (*(REG32_PTR_T)(0x3C200034)) /* Write Data Register0 */ | ||
| 250 | #define FMDATAW1 (*(REG32_PTR_T)(0x3C200038)) /* Write Data Register1 */ | ||
| 251 | #define FMDATAW2 (*(REG32_PTR_T)(0x3C20003C)) /* Write Data Register2 */ | ||
| 252 | #define FMDATAW3 (*(REG32_PTR_T)(0x3C200040)) /* Write Data Register3 */ | ||
| 253 | #define FMCSTAT (*(REG32_PTR_T)(0x3C200048)) /* Status Register */ | ||
| 254 | #define FMSYND0 (*(REG32_PTR_T)(0x3C20004C)) /* Hamming Syndrome0 */ | ||
| 255 | #define FMSYND1 (*(REG32_PTR_T)(0x3C200050)) /* Hamming Syndrome1 */ | ||
| 256 | #define FMSYND2 (*(REG32_PTR_T)(0x3C200054)) /* Hamming Syndrome2 */ | ||
| 257 | #define FMSYND3 (*(REG32_PTR_T)(0x3C200058)) /* Hamming Syndrome3 */ | ||
| 258 | #define FMSYND4 (*(REG32_PTR_T)(0x3C20005C)) /* Hamming Syndrome4 */ | ||
| 259 | #define FMSYND5 (*(REG32_PTR_T)(0x3C200060)) /* Hamming Syndrome5 */ | ||
| 260 | #define FMSYND6 (*(REG32_PTR_T)(0x3C200064)) /* Hamming Syndrome6 */ | ||
| 261 | #define FMSYND7 (*(REG32_PTR_T)(0x3C200068)) /* Hamming Syndrome7 */ | ||
| 262 | #define FMFIFO (*(REG32_PTR_T)(0x3C200080)) /* WRITE/READ FIFO FIXME */ | ||
| 263 | #define RSCRTL (*(REG32_PTR_T)(0x3C200100)) /* Reed-Solomon Control Register */ | ||
| 264 | #define RSPaity0_0 (*(REG32_PTR_T)(0x3C200110)) /* On-the-fly Parity Register0[31:0] */ | ||
| 265 | #define RSPaity0_1 (*(REG32_PTR_T)(0x3C200114)) /* On-the-fly Parity Register0[63:32] */ | ||
| 266 | #define RSPaity0_2 (*(REG32_PTR_T)(0x3C200118)) /* On-the-fly Parity Register0[71:64] */ | ||
| 267 | #define RSPaity1_0 (*(REG32_PTR_T)(0x3C200120)) /* On-the-fly Parity Register1[31:0] */ | ||
| 268 | #define RSPaity1_1 (*(REG32_PTR_T)(0x3C200124)) /* On-the-fly Parity Register1[63:32] */ | ||
| 269 | #define RSPaity1_2 (*(REG32_PTR_T)(0x3C200128)) /* On-the-fly Parity Register1[71:64] */ | ||
| 270 | #define RSPaity2_0 (*(REG32_PTR_T)(0x3C200130)) /* On-the-fly Parity Register2[31:0] */ | ||
| 271 | #define RSPaity2_1 (*(REG32_PTR_T)(0x3C200134)) /* On-the-fly Parity Register2[63:32] */ | ||
| 272 | #define RSPaity2_2 (*(REG32_PTR_T)(0x3C200138)) /* On-the-fly Parity Register2[71:64] */ | ||
| 273 | #define RSPaity3_0 (*(REG32_PTR_T)(0x3C200140)) /* On-the-fly Parity Register3[31:0] */ | ||
| 274 | #define RSPaity3_1 (*(REG32_PTR_T)(0x3C200144)) /* On-the-fly Parity Register3[63:32] */ | ||
| 275 | #define RSPaity3_2 (*(REG32_PTR_T)(0x3C200148)) /* On-the-fly Parity Register3[71:64] */ | ||
| 276 | #define RSSynd0_0 (*(REG32_PTR_T)(0x3C200150)) /* On-the-fly Synd Register0[31:0] */ | ||
| 277 | #define RSSynd0_1 (*(REG32_PTR_T)(0x3C200154)) /* On-the-fly Synd Register0[63:32] */ | ||
| 278 | #define RSSynd0_2 (*(REG32_PTR_T)(0x3C200158)) /* On-the-fly Synd Register0[71:64] */ | ||
| 279 | #define RSSynd1_0 (*(REG32_PTR_T)(0x3C200160)) /* On-the-fly Synd Register1[31:0] */ | ||
| 280 | #define RSSynd1_1 (*(REG32_PTR_T)(0x3C200164)) /* On-the-fly Synd Register1[63:32] */ | ||
| 281 | #define RSSynd1_2 (*(REG32_PTR_T)(0x3C200168)) /* On-the-fly Synd Register1[71:64] */ | ||
| 282 | #define RSSynd2_0 (*(REG32_PTR_T)(0x3C200170)) /* On-the-fly Synd Register2[31:0] */ | ||
| 283 | #define RSSynd2_1 (*(REG32_PTR_T)(0x3C200174)) /* On-the-fly Synd Register2[63:32] */ | ||
| 284 | #define RSSynd2_2 (*(REG32_PTR_T)(0x3C200178)) /* On-the-fly Synd Register2[71:64] */ | ||
| 285 | #define RSSynd3_0 (*(REG32_PTR_T)(0x3C200180)) /* On-the-fly Synd Register3[31:0] */ | ||
| 286 | #define RSSynd3_1 (*(REG32_PTR_T)(0x3C200184)) /* On-the-fly Synd Register3[63:32] */ | ||
| 287 | #define RSSynd3_2 (*(REG32_PTR_T)(0x3C200188)) /* On-the-fly Synd Register3[71:64] */ | ||
| 288 | #define FlagSynd (*(REG32_PTR_T)(0x3C200190)) /* On-the-fly ECC Result Flag */ | ||
| 289 | |||
| 290 | /* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */ | ||
| 291 | #define SDCI_CTRL (*(REG32_PTR_T)(0x3C300000)) /* Control Register */ | ||
| 292 | #define SDCI_DCTRL (*(REG32_PTR_T)(0x3C300004)) /* Data Control Register */ | ||
| 293 | #define SDCI_CMD (*(REG32_PTR_T)(0x3C300008)) /* Command Register */ | ||
| 294 | #define SDCI_ARGU (*(REG32_PTR_T)(0x3C30000C)) /* Argument Register */ | ||
| 295 | #define SDCI_STATE (*(REG32_PTR_T)(0x3C300010)) /* State Register */ | ||
| 296 | #define SDCI_STAC (*(REG32_PTR_T)(0x3C300014)) /* Status Clear Register */ | ||
| 297 | #define SDCI_DSTA (*(REG32_PTR_T)(0x3C300018)) /* Data Status Register */ | ||
| 298 | #define SDCI_FSTA (*(REG32_PTR_T)(0x3C30001C)) /* FIFO Status Register */ | ||
| 299 | #define SDCI_RESP0 (*(REG32_PTR_T)(0x3C300020)) /* Response0 Register */ | ||
| 300 | #define SDCI_RESP1 (*(REG32_PTR_T)(0x3C300024)) /* Response1 Register */ | ||
| 301 | #define SDCI_RESP2 (*(REG32_PTR_T)(0x3C300028)) /* Response2 Register */ | ||
| 302 | #define SDCI_RESP3 (*(REG32_PTR_T)(0x3C30002C)) /* Response3 Register */ | ||
| 303 | #define SDCI_CLKDIV (*(REG32_PTR_T)(0x3C300030)) /* Clock Divider Register */ | ||
| 304 | #define SDIO_CSR (*(REG32_PTR_T)(0x3C300034)) /* SDIO Control & Status Register */ | ||
| 305 | #define SDIO_IRQ (*(REG32_PTR_T)(0x3C300038)) /* Interrupt Source Register */ | ||
| 306 | |||
| 307 | /* 14. MEMORY STICK HOST CONTROLLER */ | ||
| 308 | #define MSPRE (*(REG32_PTR_T)(0x3C600000)) /* Prescaler Register */ | ||
| 309 | #define MSINTEN (*(REG32_PTR_T)(0x3C600004)) /* Interrupt Enable Register */ | ||
| 310 | #define MSCMD (*(REG32_PTR_T)(0x3C601000)) /* Command Register */ | ||
| 311 | #define MSFIFO (*(REG32_PTR_T)(0x3C601008)) /* Receive/Transmit Register */ | ||
| 312 | #define MSPP (*(REG32_PTR_T)(0x3C601010)) /* Parallel Port Control/Data Register */ | ||
| 313 | #define MSCTRL2 (*(REG32_PTR_T)(0x3C601014)) /* Control Register 2 */ | ||
| 314 | #define MSACD (*(REG32_PTR_T)(0x3C601018)) /* ACD Command Register */ | ||
| 315 | |||
| 316 | /* 15. SPDIF TRANSMITTER (SPDIFOUT) */ | ||
| 317 | #define SPDCLKCON (*(REG32_PTR_T)(0x3CB00000)) /* Clock Control Register */ | ||
| 318 | #define SPDCON (*(REG32_PTR_T)(0x3CB00004)) /* Control Register 0020 */ | ||
| 319 | #define SPDBSTAS (*(REG32_PTR_T)(0x3CB00008)) /* Burst Status Register */ | ||
| 320 | #define SPDCSTAS (*(REG32_PTR_T)(0x3CB0000C)) /* Channel Status Register 0x2000 8000 */ | ||
| 321 | #define SPDDAT (*(REG32_PTR_T)(0x3CB00010)) /* SPDIFOUT Data Buffer */ | ||
| 322 | #define SPDCNT (*(REG32_PTR_T)(0x3CB00014)) /* Repetition Count Register */ | ||
| 323 | |||
| 324 | /* 16. REED-SOLOMON ECC CODEC */ | ||
| 325 | #define DATA_PTR (*(REG32_PTR_T)(0x39E00004)) /* Data Area Start Pointer */ | ||
| 326 | #define SPARE_PTR (*(REG32_PTR_T)(0x39E00008)) /* Spare Area Start Pointer */ | ||
| 327 | #define ECC_CTRL (*(REG32_PTR_T)(0x39E0000C)) /* ECC Control Register */ | ||
| 328 | #define ECC_RESULT (*(REG32_PTR_T)(0x39E00010)) /* ECC Result */ | ||
| 329 | #define ECC_EVAL0 (*(REG32_PTR_T)(0x39E00020)) /* Error Eval0 Poly */ | ||
| 330 | #define ECC_EVAL1 (*(REG32_PTR_T)(0x39E00024)) /* Error Eval1 Poly */ | ||
| 331 | #define ECC_LOC0 (*(REG32_PTR_T)(0x39E00028)) /* Error Loc0 Poly */ | ||
| 332 | #define ECC_LOC1 (*(REG32_PTR_T)(0x39E0002C)) /* Error Loc1 Poly */ | ||
| 333 | #define PARITY0 (*(REG32_PTR_T)(0x39E00030)) /* Encode Parity0 Poly */ | ||
| 334 | #define PARITY1 (*(REG32_PTR_T)(0x39E00034)) /* Encode Pariyt1 Poly */ | ||
| 335 | #define PARITY2 (*(REG32_PTR_T)(0x39E00038)) /* Encode Parity2 Poly */ | ||
| 336 | #define INT_CLR (*(REG32_PTR_T)(0x39E00040)) /* Interrupt Clear Register */ | ||
| 337 | #define SYND0 (*(REG32_PTR_T)(0x39E00044)) /* Syndrom0 Poly */ | ||
| 338 | #define SYND1 (*(REG32_PTR_T)(0x39E00048)) /* Syndrom1 Poly */ | ||
| 339 | #define SYND2 (*(REG32_PTR_T)(0x39E0004C)) /* Syndrom2 Poly */ | ||
| 340 | |||
| 341 | /* 17. IIS Tx/Rx INTERFACE */ | ||
| 342 | #define I2SCLKCON (*(REG32_PTR_T)(0x3CA00000)) /* Clock Control Register */ | ||
| 343 | #define I2STXCON (*(REG32_PTR_T)(0x3CA00004)) /* Tx configuration Register */ | ||
| 344 | #define I2STXCOM (*(REG32_PTR_T)(0x3CA00008)) /* Tx command Register */ | ||
| 345 | #define I2STXDB0 (*(REG32_PTR_T)(0x3CA00010)) /* Tx data buffer */ | ||
| 346 | #define I2SRXCON (*(REG32_PTR_T)(0x3CA00030)) /* Rx configuration Register */ | ||
| 347 | #define I2SRXCOM (*(REG32_PTR_T)(0x3CA00034)) /* Rx command Register */ | ||
| 348 | #define I2SRXDB (*(REG32_PTR_T)(0x3CA00038)) /* Rx data buffer */ | ||
| 349 | #define I2SSTATUS (*(REG32_PTR_T)(0x3CA0003C)) /* status register */ | ||
| 350 | |||
| 351 | /* 18. IIC BUS INTERFACE */ | ||
| 352 | #define IICCON (*(REG32_PTR_T)(0x3C900000)) /* Control Register */ | ||
| 353 | #define IICSTAT (*(REG32_PTR_T)(0x3C900004)) /* Control/Status Register */ | ||
| 354 | #define IICADD (*(REG32_PTR_T)(0x3C900008)) /* Bus Address Register */ | ||
| 355 | #define IICDS (*(REG32_PTR_T)(0x3C90000C)) | ||
| 356 | |||
| 357 | /* 19. SPI (SERIAL PERHIPERAL INTERFACE) */ | ||
| 358 | #define SPCLKCON (*(REG32_PTR_T)(0x3CD00000)) /* Clock Control Register */ | ||
| 359 | #define SPCON (*(REG32_PTR_T)(0x3CD00004)) /* Control Register */ | ||
| 360 | #define SPSTA (*(REG32_PTR_T)(0x3CD00008)) /* Status Register */ | ||
| 361 | #define SPPIN (*(REG32_PTR_T)(0x3CD0000C)) /* Pin Control Register */ | ||
| 362 | #define SPTDAT (*(REG32_PTR_T)(0x3CD00010)) /* Tx Data Register */ | ||
| 363 | #define SPRDAT (*(REG32_PTR_T)(0x3CD00014)) /* Rx Data Register */ | ||
| 364 | #define SPPRE (*(REG32_PTR_T)(0x3CD00018)) /* Baud Rate Prescaler Register */ | ||
| 365 | |||
| 366 | /* 20. ADC CONTROLLER */ | ||
| 367 | #define ADCCON (*(REG32_PTR_T)(0x3CE00000)) /* ADC Control Register */ | ||
| 368 | #define ADCTSC (*(REG32_PTR_T)(0x3CE00004)) /* ADC Touch Screen Control Register */ | ||
| 369 | #define ADCDLY (*(REG32_PTR_T)(0x3CE00008)) /* ADC Start or Interval Delay Register */ | ||
| 370 | #define ADCDAT0 (*(REG32_PTR_T)(0x3CE0000C)) /* ADC Conversion Data Register */ | ||
| 371 | #define ADCDAT1 (*(REG32_PTR_T)(0x3CE00010)) /* ADC Conversion Data Register */ | ||
| 372 | #define ADCUPDN (*(REG32_PTR_T)(0x3CE00014)) /* Stylus Up or Down Interrpt Register */ | ||
| 373 | |||
| 374 | /* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */ | ||
| 375 | #define IR (*(REG32_PTR_T)(0x38800000)) /* Index Register */ | ||
| 376 | #define EIR (*(REG32_PTR_T)(0x38800004)) /* Endpoint Interrupt Register */ | ||
| 377 | #define EIER (*(REG32_PTR_T)(0x38800008)) /* Endpoint Interrupt Enable Register */ | ||
| 378 | #define FAR (*(REG32_PTR_T)(0x3880000C)) /* Function Address Register */ | ||
| 379 | #define FNR (*(REG32_PTR_T)(0x38800010)) /* Frame Number Register */ | ||
| 380 | #define EDR (*(REG32_PTR_T)(0x38800014)) /* Endpoint Direction Register */ | ||
| 381 | #define TR (*(REG32_PTR_T)(0x38800018)) /* Test Register */ | ||
| 382 | #define SSR (*(REG32_PTR_T)(0x3880001C)) /* System Status Register */ | ||
| 383 | #define SCR (*(REG32_PTR_T)(0x38800020)) /* System Control Register */ | ||
| 384 | #define EP0SR (*(REG32_PTR_T)(0x38800024)) /* EP0 Status Register */ | ||
| 385 | #define EP0CR (*(REG32_PTR_T)(0x38800028)) /* EP0 Control Register */ | ||
| 386 | #define ESR (*(REG32_PTR_T)(0x3880002C)) /* Endpoints Status Register */ | ||
| 387 | #define ECR (*(REG32_PTR_T)(0x38800030)) /* Endpoints Control Register */ | ||
| 388 | #define BRCR (*(REG32_PTR_T)(0x38800034)) /* Byte Read Count Register */ | ||
| 389 | #define BWCR (*(REG32_PTR_T)(0x38800038)) /* Byte Write Count Register */ | ||
| 390 | #define MPR (*(REG32_PTR_T)(0x3880003C)) /* Max Packet Register */ | ||
| 391 | #define MCR (*(REG32_PTR_T)(0x38800040)) /* Master Control Register */ | ||
| 392 | #define MTCR (*(REG32_PTR_T)(0x38800044)) /* Master Transfer Counter Register */ | ||
| 393 | #define MFCR (*(REG32_PTR_T)(0x38800048)) /* Master FIFO Counter Register */ | ||
| 394 | #define MTTCR1 (*(REG32_PTR_T)(0x3880004C)) /* Master Total Transfer Counter1 Register */ | ||
| 395 | #define MTTCR2 (*(REG32_PTR_T)(0x38800050)) /* Master Total Transfer Counter2 Register */ | ||
| 396 | #define EP0BR (*(REG32_PTR_T)(0x38800060)) /* EP0 Buffer Register */ | ||
| 397 | #define EP1BR (*(REG32_PTR_T)(0x38800064)) /* EP1 Buffer Register */ | ||
| 398 | #define EP2BR (*(REG32_PTR_T)(0x38800068)) /* EP2 Buffer Register */ | ||
| 399 | #define EP3BR (*(REG32_PTR_T)(0x3880006C)) /* EP3 Buffer Register */ | ||
| 400 | #define EP4BR (*(REG32_PTR_T)(0x38800070)) /* EP4 Buffer Register */ | ||
| 401 | #define EP5BR (*(REG32_PTR_T)(0x38800074)) /* EP5 Buffer Register */ | ||
| 402 | #define EP6BR (*(REG32_PTR_T)(0x38800078)) /* EP6 Buffer Register */ | ||
| 403 | #define MICR (*(REG32_PTR_T)(0x38800084)) /* Master Interface Counter Register */ | ||
| 404 | #define MBAR1 (*(REG32_PTR_T)(0x38800088)) /* Memory Base Address Register1 */ | ||
| 405 | #define MBAR2 (*(REG32_PTR_T)(0x3880008C)) /* Memory Base Address Register2 */ | ||
| 406 | #define MCAR1 (*(REG32_PTR_T)(0x38800094)) /* Memory Current Address Register1 */ | ||
| 407 | #define MCAR2 (*(REG32_PTR_T)(0x38800098)) /* Memory Current Address Register2 */ | ||
| 408 | |||
| 409 | /* 22. USB 1.1 HOST CONTROLER SPECIAL REGISTER */ | ||
| 410 | #define HcRevision (*(REG32_PTR_T)(0x38600000)) | ||
| 411 | #define HcControl (*(REG32_PTR_T)(0x38600004)) | ||
| 412 | #define HcCommandStatus (*(REG32_PTR_T)(0x38600008)) | ||
| 413 | #define HcInterruptStatus (*(REG32_PTR_T)(0x3860000C)) | ||
| 414 | #define HcInterruptEnable (*(REG32_PTR_T)(0x38600010)) | ||
| 415 | #define HcInterruptDisable (*(REG32_PTR_T)(0x38600014)) | ||
| 416 | #define HcHCCA (*(REG32_PTR_T)(0x38600018)) | ||
| 417 | #define HcPeriodCurrentED (*(REG32_PTR_T)(0x3860001C)) | ||
| 418 | #define HcControlHeadED (*(REG32_PTR_T)(0x38600020)) | ||
| 419 | #define HcControlCurrentED (*(REG32_PTR_T)(0x38600024)) | ||
| 420 | #define HcBulkHeadED (*(REG32_PTR_T)(0x38600028)) | ||
| 421 | #define HcBulkCurrentED (*(REG32_PTR_T)(0x3860002C)) | ||
| 422 | #define HcDoneHead (*(REG32_PTR_T)(0x38600030)) | ||
| 423 | #define HcFmInterval (*(REG32_PTR_T)(0x38600034)) | ||
| 424 | #define HcFmRemaining (*(REG32_PTR_T)(0x38600038)) | ||
| 425 | #define HcFmNumber (*(REG32_PTR_T)(0x3860003C)) | ||
| 426 | #define HcPeriodicStart (*(REG32_PTR_T)(0x38600040)) | ||
| 427 | #define HcLSThreshold (*(REG32_PTR_T)(0x38600044)) | ||
| 428 | #define HcRhDescriptorA (*(REG32_PTR_T)(0x38600048)) | ||
| 429 | #define HcRhDescriptorB (*(REG32_PTR_T)(0x3860004C)) | ||
| 430 | #define HcRhStatus (*(REG32_PTR_T)(0x38600050)) | ||
| 431 | #define HcRhPortStatus (*(REG32_PTR_T)(0x38600054)) | ||
| 432 | |||
| 433 | /* 23. USB 2.0 PHY CONTROL */ | ||
| 434 | #define PHYCTRL (*(REG32_PTR_T)(0x3C400000)) /* USB2.0 PHY Control Register */ | ||
| 435 | #define PHYPWR (*(REG32_PTR_T)(0x3C400004)) /* USB2.0 PHY Power Control Register */ | ||
| 436 | #define URSTCON (*(REG32_PTR_T)(0x3C400008)) /* USB Reset Control Register */ | ||
| 437 | #define UCLKCON (*(REG32_PTR_T)(0x3C400010)) /* USB Clock Control Register */ | ||
| 438 | |||
| 439 | /* 24. GPIO PORT CONTROLL */ | ||
| 440 | #define PCON0 (*(REG32_PTR_T)(0x3CF00000)) /* Configures the pins of port 0 */ | ||
| 441 | #define PDAT0 (*(REG32_PTR_T)(0x3CF00004)) /* The data register for port 0 */ | ||
| 442 | #define PCON1 (*(REG32_PTR_T)(0x3CF00010)) /* Configures the pins of port 0 */ | ||
| 443 | #define PDAT1 (*(REG32_PTR_T)(0x3CF00014)) /* The data register for port 0 */ | ||
| 444 | #define PCON2 (*(REG32_PTR_T)(0x3CF00020)) /* Configures the pins of port 0 */ | ||
| 445 | #define PDAT2 (*(REG32_PTR_T)(0x3CF00024)) /* The data register for port 0 */ | ||
| 446 | #define PCON3 (*(REG32_PTR_T)(0x3CF00030)) /* Configures the pins of port 0 */ | ||
| 447 | #define PDAT3 (*(REG32_PTR_T)(0x3CF00034)) /* The data register for port 0 */ | ||
| 448 | #define PCON4 (*(REG32_PTR_T)(0x3CF00040)) /* Configures the pins of port 0 */ | ||
| 449 | #define PDAT4 (*(REG32_PTR_T)(0x3CF00044)) /* The data register for port 0 */ | ||
| 450 | #define PCON5 (*(REG32_PTR_T)(0x3CF00050)) /* Configures the pins of port 0 */ | ||
| 451 | #define PDAT5 (*(REG32_PTR_T)(0x3CF00054)) /* The data register for port 0 */ | ||
| 452 | #define PCON6 (*(REG32_PTR_T)(0x3CF00060)) /* Configures the pins of port 0 */ | ||
| 453 | #define PDAT6 (*(REG32_PTR_T)(0x3CF00064)) /* The data register for port 0 */ | ||
| 454 | #define PCON7 (*(REG32_PTR_T)(0x3CF00070)) /* Configures the pins of port 0 */ | ||
| 455 | #define PDAT7 (*(REG32_PTR_T)(0x3CF00074)) /* The data register for port 0 */ | ||
| 456 | #define PCON10 (*(REG32_PTR_T)(0x3CF000A0)) /* Configures the pins of port 0 */ | ||
| 457 | #define PDAT10 (*(REG32_PTR_T)(0x3CF000A4)) /* The data register for port 0 */ | ||
| 458 | #define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ | ||
| 459 | #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ | ||
| 460 | #define PCON11 (*(REG32_PTR_T)(0x3CF000F8)) /* Configures the pins of port 11 */ | ||
| 461 | #define PDAT11 (*(REG32_PTR_T)(0x3CF000FC)) /* The data register for port 11 */ | ||
| 462 | |||
| 463 | /* 25. UART */ | ||
| 464 | |||
| 465 | /* UART 0 */ | ||
| 466 | #define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */ | ||
| 467 | #define UCON0 (*(REG32_PTR_T)(0x3CC00004)) /* Control Register */ | ||
| 468 | #define UFCON0 (*(REG32_PTR_T)(0x3CC00008)) /* FIFO Control Register */ | ||
| 469 | #define UMCON0 (*(REG32_PTR_T)(0x3CC0000C)) /* Modem Control Register */ | ||
| 470 | #define UTRSTAT0 (*(REG32_PTR_T)(0x3CC00010)) /* Tx/Rx Status Register */ | ||
| 471 | #define UERSTAT0 (*(REG32_PTR_T)(0x3CC00014)) /* Rx Error Status Register */ | ||
| 472 | #define UFSTAT0 (*(REG32_PTR_T)(0x3CC00018)) /* FIFO Status Register */ | ||
| 473 | #define UMSTAT0 (*(REG32_PTR_T)(0x3CC0001C)) /* Modem Status Register */ | ||
| 474 | #define UTXH0 (*(REG32_PTR_T)(0x3CC00020)) /* Transmit Buffer Register */ | ||
| 475 | #define URXH0 (*(REG32_PTR_T)(0x3CC00024)) /* Receive Buffer Register */ | ||
| 476 | #define UBRDIV0 (*(REG32_PTR_T)(0x3CC00028)) /* Baud Rate Divisor Register */ | ||
| 477 | |||
| 478 | /* UART 1*/ | ||
| 479 | #define ULCON1 (*(REG32_PTR_T)(0x3CC08000)) /* Line Control Register */ | ||
| 480 | #define UCON1 (*(REG32_PTR_T)(0x3CC08004)) /* Control Register */ | ||
| 481 | #define UFCON1 (*(REG32_PTR_T)(0x3CC08008)) /* FIFO Control Register */ | ||
| 482 | #define UMCON1 (*(REG32_PTR_T)(0x3CC0800C)) /* Modem Control Register */ | ||
| 483 | #define UTRSTAT1 (*(REG32_PTR_T)(0x3CC08010)) /* Tx/Rx Status Register */ | ||
| 484 | #define UERSTAT1 (*(REG32_PTR_T)(0x3CC08014)) /* Rx Error Status Register */ | ||
| 485 | #define UFSTAT1 (*(REG32_PTR_T)(0x3CC08018)) /* FIFO Status Register */ | ||
| 486 | #define UMSTAT1 (*(REG32_PTR_T)(0x3CC0801C)) /* Modem Status Register */ | ||
| 487 | #define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */ | ||
| 488 | #define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */ | ||
| 489 | #define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */ | ||
| 490 | |||
| 491 | /* 26. LCD INTERFACE CONTROLLER */ | ||
| 492 | #define LCD_CON (*(REG32_PTR_T)(0x3C100000)) /* Control register. */ | ||
| 493 | #define LCD_WCMD (*(REG32_PTR_T)(0x3C100004)) /* Write command register. */ | ||
| 494 | #define LCD_RCMD (*(REG32_PTR_T)(0x3C10000C)) /* Read command register. */ | ||
| 495 | #define LCD_RDATA (*(REG32_PTR_T)(0x3C100010)) /* Read data register. */ | ||
| 496 | #define LCD_DBUFF (*(REG32_PTR_T)(0x3C100014)) /* Read Data buffer */ | ||
| 497 | #define LCD_INTCON (*(REG32_PTR_T)(0x3C100018)) /* Interrupt control register */ | ||
| 498 | #define LCD_STATUS (*(REG32_PTR_T)(0x3C10001C)) /* LCD Interface status 0106 */ | ||
| 499 | #define LCD_PHTIME (*(REG32_PTR_T)(0x3C100020)) /* Phase time register 0060 */ | ||
| 500 | #define LCD_RST_TIME (*(REG32_PTR_T)(0x3C100024)) /* Reset active period 07FF */ | ||
| 501 | #define LCD_DRV_RST (*(REG32_PTR_T)(0x3C100028)) /* Reset drive signal */ | ||
| 502 | #define LCD_WDATA (*(REG32_PTR_T)(0x3C100040)) /* Write data register FIXME */ | ||
| 503 | |||
| 504 | /* 27. CLCD CONTROLLER */ | ||
| 505 | #define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */ | ||
| 506 | #define LCDCON2 (*(REG32_PTR_T)(0x39200004)) /* LCD control 2 register */ | ||
| 507 | #define LCDTCON1 (*(REG32_PTR_T)(0x39200008)) /* LCD time control 1 register */ | ||
| 508 | #define LCDTCON2 (*(REG32_PTR_T)(0x3920000C)) /* LCD time control 2 register */ | ||
| 509 | #define LCDTCON3 (*(REG32_PTR_T)(0x39200010)) /* LCD time control 3 register */ | ||
| 510 | #define LCDOSD1 (*(REG32_PTR_T)(0x39200014)) /* LCD OSD control 1 register */ | ||
| 511 | #define LCDOSD2 (*(REG32_PTR_T)(0x39200018)) /* LCD OSD control 2 register */ | ||
| 512 | #define LCDOSD3 (*(REG32_PTR_T)(0x3920001C)) /* LCD OSD control 3 register */ | ||
| 513 | #define LCDB1SADDR1 (*(REG32_PTR_T)(0x39200020)) /* Frame buffer start address register for Back-Ground buffer 1 */ | ||
| 514 | #define LCDB2SADDR1 (*(REG32_PTR_T)(0x39200024)) /* Frame buffer start address register for Back-Ground buffer 2 */ | ||
| 515 | #define LCDF1SADDR1 (*(REG32_PTR_T)(0x39200028)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 1 */ | ||
| 516 | #define LCDF2SADDR1 (*(REG32_PTR_T)(0x3920002C)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 2 */ | ||
| 517 | #define LCDB1SADDR2 (*(REG32_PTR_T)(0x39200030)) /* Frame buffer end address register for Back-Ground buffer 1 */ | ||
| 518 | #define LCDB2SADDR2 (*(REG32_PTR_T)(0x39200034)) /* Frame buffer end address register for Back-Ground buffer 2 */ | ||
| 519 | #define LCDF1SADDR2 (*(REG32_PTR_T)(0x39200038)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 1 */ | ||
| 520 | #define LCDF2SADDR2 (*(REG32_PTR_T)(0x3920003C)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 2 */ | ||
| 521 | #define LCDB1SADDR3 (*(REG32_PTR_T)(0x39200040)) /* Virtual screen address set for Back-Ground buffer 1 */ | ||
| 522 | #define LCDB2SADDR3 (*(REG32_PTR_T)(0x39200044)) /* Virtual screen address set for Back-Ground buffer 2 */ | ||
| 523 | #define LCDF1SADDR3 (*(REG32_PTR_T)(0x39200048)) /* Virtual screen address set for Fore-Ground(OSD) buffer 1 */ | ||
| 524 | #define LCDF2SADDR3 (*(REG32_PTR_T)(0x3920004C)) /* Virtual screen address set for Fore-Ground(OSD) buffer 2 */ | ||
| 525 | #define LCDINTCON (*(REG32_PTR_T)(0x39200050)) /* Indicate the LCD interrupt control register */ | ||
| 526 | #define KEYCON (*(REG32_PTR_T)(0x39200054)) /* Color key control register */ | ||
| 527 | #define COLVAL (*(REG32_PTR_T)(0x39200058)) /* Color key value ( transparent value) register */ | ||
| 528 | #define BGCON (*(REG32_PTR_T)(0x3920005C)) /* Back-Ground color control */ | ||
| 529 | #define FGCON (*(REG32_PTR_T)(0x39200060)) /* Fore-Ground color control */ | ||
| 530 | #define DITHMODE (*(REG32_PTR_T)(0x39200064)) /* Dithering mode register. */ | ||
| 531 | |||
| 532 | /* 28. ATA CONTROLLER */ | ||
| 533 | #define ATA_CONTROL (*(REG32_PTR_T)(0x38E00000)) /* Enable and clock down status */ | ||
| 534 | #define ATA_STATUS (*(REG32_PTR_T)(0x38E00004)) /* Status */ | ||
| 535 | #define ATA_COMMAND (*(REG32_PTR_T)(0x38E00008)) /* Command */ | ||
| 536 | #define ATA_SWRST (*(REG32_PTR_T)(0x38E0000C)) /* Software reset */ | ||
| 537 | #define ATA_IRQ (*(REG32_PTR_T)(0x38E00010)) /* Interrupt sources */ | ||
| 538 | #define ATA_IRQ_MASK (*(REG32_PTR_T)(0x38E00014)) /* Interrupt mask */ | ||
| 539 | #define ATA_CFG (*(REG32_PTR_T)(0x38E00018)) /* Configuration for ATA interface */ | ||
| 540 | #define ATA_PIO_TIME (*(REG32_PTR_T)(0x38E0002C)) /* PIO timing */ | ||
| 541 | #define ATA_UDMA_TIME (*(REG32_PTR_T)(0x38E00030)) /* UDMA timing */ | ||
| 542 | #define ATA_XFR_NUM (*(REG32_PTR_T)(0x38E00034)) /* Transfer number */ | ||
| 543 | #define ATA_XFR_CNT (*(REG32_PTR_T)(0x38E00038)) /* Current transfer count */ | ||
| 544 | #define ATA_TBUF_START (*(REG32_PTR_T)(0x38E0003C)) /* Start address of track buffer */ | ||
| 545 | #define ATA_TBUF_SIZE (*(REG32_PTR_T)(0x38E00040)) /* Size of track buffer */ | ||
| 546 | #define ATA_SBUF_START (*(REG32_PTR_T)(0x38E00044)) /* Start address of Source buffer1 */ | ||
| 547 | #define ATA_SBUF_SIZE (*(REG32_PTR_T)(0x38E00048)) /* Size of source buffer1 */ | ||
| 548 | #define ATA_CADR_TBUF (*(REG32_PTR_T)(0x38E0004C)) /* Current write address of track buffer */ | ||
| 549 | #define ATA_CADR_SBUF (*(REG32_PTR_T)(0x38E00050)) /* Current read address of source buffer */ | ||
| 550 | #define ATA_PIO_DTR (*(REG32_PTR_T)(0x38E00054)) /* PIO device data register */ | ||
| 551 | #define ATA_PIO_FED (*(REG32_PTR_T)(0x38E00058)) /* PIO device Feature/Error register */ | ||
| 552 | #define ATA_PIO_SCR (*(REG32_PTR_T)(0x38E0005C)) /* PIO sector count register */ | ||
| 553 | #define ATA_PIO_LLR (*(REG32_PTR_T)(0x38E00060)) /* PIO device LBA low register */ | ||
| 554 | #define ATA_PIO_LMR (*(REG32_PTR_T)(0x38E00064)) /* PIO device LBA middle register */ | ||
| 555 | #define ATA_PIO_LHR (*(REG32_PTR_T)(0x38E00068)) /* PIO device LBA high register */ | ||
| 556 | #define ATA_PIO_DVR (*(REG32_PTR_T)(0x38E0006C)) /* PIO device register */ | ||
| 557 | #define ATA_PIO_CSD (*(REG32_PTR_T)(0x38E00070)) /* PIO device command/status register */ | ||
| 558 | #define ATA_PIO_DAD (*(REG32_PTR_T)(0x38E00074)) /* PIO control/alternate status register */ | ||
| 559 | #define ATA_PIO_READY (*(REG32_PTR_T)(0x38E00078)) /* PIO data read/write ready */ | ||
| 560 | #define ATA_PIO_RDATA (*(REG32_PTR_T)(0x38E0007C)) /* PIO read data from device register */ | ||
| 561 | #define BUS_FIFO_STATUS (*(REG32_PTR_T)(0x38E00080)) /* Reserved */ | ||
| 562 | #define ATA_FIFO_STATUS (*(REG32_PTR_T)(0x38E00084)) /* Reserved */ | ||
| 563 | |||
| 564 | /* 29. CHIP ID */ | ||
| 565 | #define REG_ONE (*(REG32_PTR_T)(0x3D100000)) /* Receive the first 32 bits from a fuse box */ | ||
| 566 | #define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ | ||
| 567 | |||