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author | Michael Sevakis <jethead71@rockbox.org> | 2010-04-10 09:24:06 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2010-04-10 09:24:06 +0000 |
commit | 79d90b9e763ab50b900b35bc6746fea9bbaacb53 (patch) | |
tree | 5e59311f7ff87c1137752874b8884ad62e06c0c0 | |
parent | 0f6e79a22727eb77d76e31138514a17debfe66d2 (diff) | |
download | rockbox-79d90b9e763ab50b900b35bc6746fea9bbaacb53.tar.gz rockbox-79d90b9e763ab50b900b35bc6746fea9bbaacb53.zip |
Gigabeat S/i.MX31: Continue, and most likely complete, the platform/player-specific code/data shuffling begun in r25547.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25564 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c | 20 | ||||
-rw-r--r-- | firmware/target/arm/imx31/mc13783-imx31.c | 17 |
2 files changed, 21 insertions, 16 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c index 2060b7bc6a..22c9f3e1df 100644 --- a/firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c | |||
@@ -22,6 +22,7 @@ | |||
22 | ****************************************************************************/ | 22 | ****************************************************************************/ |
23 | #include "config.h" | 23 | #include "config.h" |
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include "spi-imx31.h" | ||
25 | #include "mc13783.h" | 26 | #include "mc13783.h" |
26 | #include "mc13783-target.h" | 27 | #include "mc13783-target.h" |
27 | #include "adc-target.h" | 28 | #include "adc-target.h" |
@@ -30,6 +31,25 @@ | |||
30 | #include "power-gigabeat-s.h" | 31 | #include "power-gigabeat-s.h" |
31 | #include "powermgmt-target.h" | 32 | #include "powermgmt-target.h" |
32 | 33 | ||
34 | /* Gigabeat S mc13783 serial interface node. */ | ||
35 | |||
36 | /* This is all based on communicating with the MC13783 PMU which is on | ||
37 | * CSPI2 with the chip select at 0. The LCD controller resides on | ||
38 | * CSPI3 cs1, but we have no idea how to communicate to it */ | ||
39 | struct spi_node mc13783_spi = | ||
40 | { | ||
41 | CSPI2_NUM, /* CSPI module 2 */ | ||
42 | CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */ | ||
43 | CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */ | ||
44 | CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */ | ||
45 | CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */ | ||
46 | CSPI_CONREG_SSPOL | /* SS active high */ | ||
47 | CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */ | ||
48 | CSPI_CONREG_MODE, /* Master mode */ | ||
49 | 0, /* SPI clock - no wait states */ | ||
50 | }; | ||
51 | |||
52 | |||
33 | /* Gigabeat S definitions for static MC13783 event registration */ | 53 | /* Gigabeat S definitions for static MC13783 event registration */ |
34 | 54 | ||
35 | static const struct mc13783_event mc13783_events[] = | 55 | static const struct mc13783_event mc13783_events[] = |
diff --git a/firmware/target/arm/imx31/mc13783-imx31.c b/firmware/target/arm/imx31/mc13783-imx31.c index 9b7248dc45..1c43b3b6fa 100644 --- a/firmware/target/arm/imx31/mc13783-imx31.c +++ b/firmware/target/arm/imx31/mc13783-imx31.c | |||
@@ -30,23 +30,8 @@ | |||
30 | #define PMIC_DRIVER_CLOSE | 30 | #define PMIC_DRIVER_CLOSE |
31 | #endif | 31 | #endif |
32 | 32 | ||
33 | /* This is all based on communicating with the MC13783 PMU which is on | ||
34 | * CSPI2 with the chip select at 0. The LCD controller resides on | ||
35 | * CSPI3 cs1, but we have no idea how to communicate to it */ | ||
36 | static struct spi_node mc13783_spi = | ||
37 | { | ||
38 | CSPI2_NUM, /* CSPI module 2 */ | ||
39 | CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */ | ||
40 | CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */ | ||
41 | CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */ | ||
42 | CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */ | ||
43 | CSPI_CONREG_SSPOL | /* SS active high */ | ||
44 | CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */ | ||
45 | CSPI_CONREG_MODE, /* Master mode */ | ||
46 | 0, /* SPI clock - no wait states */ | ||
47 | }; | ||
48 | |||
49 | extern const struct mc13783_event_list mc13783_event_list; | 33 | extern const struct mc13783_event_list mc13783_event_list; |
34 | extern struct spi_node mc13783_spi; | ||
50 | 35 | ||
51 | static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)]; | 36 | static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)]; |
52 | static const char *mc13783_thread_name = "pmic"; | 37 | static const char *mc13783_thread_name = "pmic"; |