diff options
Diffstat (limited to 'firmware/target/arm/imx31/mc13783-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/mc13783-imx31.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/firmware/target/arm/imx31/mc13783-imx31.c b/firmware/target/arm/imx31/mc13783-imx31.c index 9b7248dc45..1c43b3b6fa 100644 --- a/firmware/target/arm/imx31/mc13783-imx31.c +++ b/firmware/target/arm/imx31/mc13783-imx31.c | |||
@@ -30,23 +30,8 @@ | |||
30 | #define PMIC_DRIVER_CLOSE | 30 | #define PMIC_DRIVER_CLOSE |
31 | #endif | 31 | #endif |
32 | 32 | ||
33 | /* This is all based on communicating with the MC13783 PMU which is on | ||
34 | * CSPI2 with the chip select at 0. The LCD controller resides on | ||
35 | * CSPI3 cs1, but we have no idea how to communicate to it */ | ||
36 | static struct spi_node mc13783_spi = | ||
37 | { | ||
38 | CSPI2_NUM, /* CSPI module 2 */ | ||
39 | CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */ | ||
40 | CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */ | ||
41 | CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */ | ||
42 | CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */ | ||
43 | CSPI_CONREG_SSPOL | /* SS active high */ | ||
44 | CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */ | ||
45 | CSPI_CONREG_MODE, /* Master mode */ | ||
46 | 0, /* SPI clock - no wait states */ | ||
47 | }; | ||
48 | |||
49 | extern const struct mc13783_event_list mc13783_event_list; | 33 | extern const struct mc13783_event_list mc13783_event_list; |
34 | extern struct spi_node mc13783_spi; | ||
50 | 35 | ||
51 | static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)]; | 36 | static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)]; |
52 | static const char *mc13783_thread_name = "pmic"; | 37 | static const char *mc13783_thread_name = "pmic"; |