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author | Jens Arnold <amiconn@rockbox.org> | 2005-11-05 03:28:20 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2005-11-05 03:28:20 +0000 |
commit | 72f98786a0b73722d2688c7509a1acc528b727af (patch) | |
tree | f658cd2f7aca2df217e0d1cfad65e9d56e230ba1 | |
parent | 81411a8226437c0e4cdd95e755a7245314d4edeb (diff) | |
download | rockbox-72f98786a0b73722d2688c7509a1acc528b727af.tar.gz rockbox-72f98786a0b73722d2688c7509a1acc528b727af.zip |
Fixup of the MCF5249 memory mapped register definitions.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7755 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/export/mcf5249.h | 49 | ||||
-rw-r--r-- | firmware/kernel.c | 2 | ||||
-rw-r--r-- | firmware/pcm_playback.c | 6 | ||||
-rw-r--r-- | firmware/pcm_record.c | 6 | ||||
-rw-r--r-- | firmware/timer.c | 3 |
5 files changed, 39 insertions, 27 deletions
diff --git a/firmware/export/mcf5249.h b/firmware/export/mcf5249.h index e2fa50e672..406e0b1c1b 100644 --- a/firmware/export/mcf5249.h +++ b/firmware/export/mcf5249.h | |||
@@ -22,14 +22,27 @@ | |||
22 | #define MBAR 0x40000000 | 22 | #define MBAR 0x40000000 |
23 | #define MBAR2 0x80000000 | 23 | #define MBAR2 0x80000000 |
24 | 24 | ||
25 | #define SYSTEM_CTRL (*(volatile unsigned char *)(MBAR + 0x000)) | 25 | #define RSR (*(volatile unsigned char *)(MBAR + 0x000)) |
26 | #define BUSMASTER_CTRL (*(volatile unsigned char *)(MBAR + 0x00c)) | 26 | #define SYPCR (*(volatile unsigned char *)(MBAR + 0x001)) |
27 | #define SWIVR (*(volatile unsigned char *)(MBAR + 0x002)) | ||
28 | #define SWSR (*(volatile unsigned char *)(MBAR + 0x003)) | ||
27 | 29 | ||
28 | #define IPR (*(volatile unsigned long *)(MBAR + 0x040)) | 30 | #define MPARK (*(volatile unsigned char *)(MBAR + 0x00c)) |
29 | #define IMR (*(volatile unsigned long *)(MBAR + 0x044)) | 31 | |
30 | #define ICR0 (*(volatile unsigned long *)(MBAR + 0x04c)) | 32 | #define IPR (*(volatile unsigned long *)(MBAR + 0x040)) |
31 | #define ICR4 (*(volatile unsigned long *)(MBAR + 0x050)) | 33 | #define IMR (*(volatile unsigned long *)(MBAR + 0x044)) |
32 | #define ICR8 (*(volatile unsigned long *)(MBAR + 0x054)) | 34 | #define ICR0 (*(volatile unsigned char *)(MBAR + 0x04c)) |
35 | #define ICR1 (*(volatile unsigned char *)(MBAR + 0x04d)) | ||
36 | #define ICR2 (*(volatile unsigned char *)(MBAR + 0x04e)) | ||
37 | #define ICR3 (*(volatile unsigned char *)(MBAR + 0x04f)) | ||
38 | #define ICR4 (*(volatile unsigned char *)(MBAR + 0x050)) | ||
39 | #define ICR5 (*(volatile unsigned char *)(MBAR + 0x051)) | ||
40 | #define ICR6 (*(volatile unsigned char *)(MBAR + 0x052)) | ||
41 | #define ICR7 (*(volatile unsigned char *)(MBAR + 0x053)) | ||
42 | #define ICR8 (*(volatile unsigned char *)(MBAR + 0x054)) | ||
43 | #define ICR9 (*(volatile unsigned char *)(MBAR + 0x055)) | ||
44 | #define ICR10 (*(volatile unsigned char *)(MBAR + 0x056)) | ||
45 | #define ICR11 (*(volatile unsigned char *)(MBAR + 0x057)) | ||
33 | 46 | ||
34 | #define CSAR0 (*(volatile unsigned long *)(MBAR + 0x080)) | 47 | #define CSAR0 (*(volatile unsigned long *)(MBAR + 0x080)) |
35 | #define CSMR0 (*(volatile unsigned long *)(MBAR + 0x084)) | 48 | #define CSMR0 (*(volatile unsigned long *)(MBAR + 0x084)) |
@@ -53,12 +66,12 @@ | |||
53 | #define TRR0 (*(volatile unsigned short *)(MBAR + 0x144)) | 66 | #define TRR0 (*(volatile unsigned short *)(MBAR + 0x144)) |
54 | #define TCR0 (*(volatile unsigned short *)(MBAR + 0x148)) | 67 | #define TCR0 (*(volatile unsigned short *)(MBAR + 0x148)) |
55 | #define TCN0 (*(volatile unsigned short *)(MBAR + 0x14c)) | 68 | #define TCN0 (*(volatile unsigned short *)(MBAR + 0x14c)) |
56 | #define TER0 (*(volatile unsigned short *)(MBAR + 0x150)) | 69 | #define TER0 (*(volatile unsigned char *)(MBAR + 0x151)) |
57 | #define TMR1 (*(volatile unsigned short *)(MBAR + 0x180)) | 70 | #define TMR1 (*(volatile unsigned short *)(MBAR + 0x180)) |
58 | #define TRR1 (*(volatile unsigned short *)(MBAR + 0x184)) | 71 | #define TRR1 (*(volatile unsigned short *)(MBAR + 0x184)) |
59 | #define TCR1 (*(volatile unsigned short *)(MBAR + 0x188)) | 72 | #define TCR1 (*(volatile unsigned short *)(MBAR + 0x188)) |
60 | #define TCN1 (*(volatile unsigned short *)(MBAR + 0x18c)) | 73 | #define TCN1 (*(volatile unsigned short *)(MBAR + 0x18c)) |
61 | #define TER1 (*(volatile unsigned short *)(MBAR + 0x190)) | 74 | #define TER1 (*(volatile unsigned char *)(MBAR + 0x191)) |
62 | 75 | ||
63 | #define UMR0 (*(volatile unsigned char *)(MBAR + 0x1c0)) | 76 | #define UMR0 (*(volatile unsigned char *)(MBAR + 0x1c0)) |
64 | #define USR0 (*(volatile unsigned char *)(MBAR + 0x1c4)) | 77 | #define USR0 (*(volatile unsigned char *)(MBAR + 0x1c4)) |
@@ -133,11 +146,11 @@ | |||
133 | #define QSPIQWR (*(volatile unsigned short *)(MBAR + 0x408)) | 146 | #define QSPIQWR (*(volatile unsigned short *)(MBAR + 0x408)) |
134 | #define QSPIQIR (*(volatile unsigned short *)(MBAR + 0x40c)) | 147 | #define QSPIQIR (*(volatile unsigned short *)(MBAR + 0x40c)) |
135 | #define QSPIQAR (*(volatile unsigned short *)(MBAR + 0x410)) | 148 | #define QSPIQAR (*(volatile unsigned short *)(MBAR + 0x410)) |
136 | #define QIR (*(volatile unsigned short *)(MBAR + 0x414)) | 149 | #define QSPIQDR (*(volatile unsigned short *)(MBAR + 0x414)) |
137 | 150 | ||
138 | #define GPIO_READ (*(volatile unsigned long *)(MBAR2 + 0x000)) | 151 | #define GPIO_READ (*(volatile unsigned long *)(MBAR2 + 0x000)) |
139 | #define GPIO_OUT (*(volatile unsigned long *)(MBAR2 + 0x004)) | 152 | #define GPIO_OUT (*(volatile unsigned long *)(MBAR2 + 0x004)) |
140 | #define GPIO_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x008)) | 153 | #define GPIO_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x008)) |
141 | #define GPIO_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x00c)) | 154 | #define GPIO_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x00c)) |
142 | 155 | ||
143 | #define IIS1CONFIG (*(volatile unsigned long *)(MBAR2 + 0x010)) | 156 | #define IIS1CONFIG (*(volatile unsigned long *)(MBAR2 + 0x010)) |
@@ -177,9 +190,11 @@ | |||
177 | #define U2CHANNELRECEIVE (*(volatile unsigned long *)(MBAR2 + 0x0d8)) | 190 | #define U2CHANNELRECEIVE (*(volatile unsigned long *)(MBAR2 + 0x0d8)) |
178 | #define Q2CHANNELRECEIVE (*(volatile unsigned long *)(MBAR2 + 0x0dc)) | 191 | #define Q2CHANNELRECEIVE (*(volatile unsigned long *)(MBAR2 + 0x0dc)) |
179 | 192 | ||
180 | #define GPIO1_READ (*(volatile unsigned long *)(MBAR2 + 0x0b0)) | 193 | #define DEVICE_ID (*(volatile unsigned long *)(MBAR2 + 0x0ac)) |
181 | #define GPIO1_OUT (*(volatile unsigned long *)(MBAR2 + 0x0b4)) | 194 | |
182 | #define GPIO1_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x0b8)) | 195 | #define GPIO1_READ (*(volatile unsigned long *)(MBAR2 + 0x0b0)) |
196 | #define GPIO1_OUT (*(volatile unsigned long *)(MBAR2 + 0x0b4)) | ||
197 | #define GPIO1_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x0b8)) | ||
183 | #define GPIO1_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x0bc)) | 198 | #define GPIO1_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x0bc)) |
184 | #define GPIO_INT_STAT (*(volatile unsigned long *)(MBAR2 + 0x0c0)) | 199 | #define GPIO_INT_STAT (*(volatile unsigned long *)(MBAR2 + 0x0c0)) |
185 | #define GPIO_INT_CLEAR (*(volatile unsigned long *)(MBAR2 + 0x0c0)) | 200 | #define GPIO_INT_CLEAR (*(volatile unsigned long *)(MBAR2 + 0x0c0)) |
@@ -222,8 +237,6 @@ | |||
222 | #define FLASHMEDIAINTSTAT (*(volatile unsigned long *)(MBAR2 + 0x47c)) | 237 | #define FLASHMEDIAINTSTAT (*(volatile unsigned long *)(MBAR2 + 0x47c)) |
223 | #define FLASHMEDIAINTCLEAR (*(volatile unsigned long *)(MBAR2 + 0x47c)) | 238 | #define FLASHMEDIAINTCLEAR (*(volatile unsigned long *)(MBAR2 + 0x47c)) |
224 | 239 | ||
225 | #define DEVICE_ID (*(volatile unsigned long *)(MBAR2 + 0x0ac)) | ||
226 | |||
227 | /* DMA Registers ... */ | 240 | /* DMA Registers ... */ |
228 | 241 | ||
229 | #define O_SAR 0x00 /* Source Address */ | 242 | #define O_SAR 0x00 /* Source Address */ |
diff --git a/firmware/kernel.c b/firmware/kernel.c index ee4e37e50d..9af4566662 100644 --- a/firmware/kernel.c +++ b/firmware/kernel.c | |||
@@ -233,7 +233,7 @@ void tick_start(unsigned int interval_in_ms) | |||
233 | 233 | ||
234 | TER0 = 0xff; /* Clear all events */ | 234 | TER0 = 0xff; /* Clear all events */ |
235 | 235 | ||
236 | ICR0 = (ICR0 & 0xff00ffff) | 0x008c0000; /* Interrupt on level 3.0 */ | 236 | ICR1 = 0x8c; /* Interrupt on level 3.0 */ |
237 | IMR &= ~0x200; | 237 | IMR &= ~0x200; |
238 | } | 238 | } |
239 | 239 | ||
diff --git a/firmware/pcm_playback.c b/firmware/pcm_playback.c index 5597f69bdb..21c4bf8c04 100644 --- a/firmware/pcm_playback.c +++ b/firmware/pcm_playback.c | |||
@@ -286,8 +286,8 @@ void pcm_init(void) | |||
286 | pcm_playing = false; | 286 | pcm_playing = false; |
287 | pcm_paused = false; | 287 | pcm_paused = false; |
288 | 288 | ||
289 | BUSMASTER_CTRL = 0x81; /* PARK[1,0]=10 + BCR24BIT */ | 289 | MPARK = 0x81; /* PARK[1,0]=10 + BCR24BIT */ |
290 | DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */ | 290 | DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */ |
291 | DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1; | 291 | DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1; |
292 | DMACONFIG = 1; /* DMA0Req = PDOR3 */ | 292 | DMACONFIG = 1; /* DMA0Req = PDOR3 */ |
293 | 293 | ||
@@ -295,7 +295,7 @@ void pcm_init(void) | |||
295 | IIS2CONFIG = IIS_RESET; | 295 | IIS2CONFIG = IIS_RESET; |
296 | 296 | ||
297 | /* Enable interrupt at level 7, priority 0 */ | 297 | /* Enable interrupt at level 7, priority 0 */ |
298 | ICR4 = (ICR4 & 0xffff00ff) | 0x00001c00; | 298 | ICR6 = 0x1c; |
299 | IMR &= ~(1<<14); /* bit 14 is DMA0 */ | 299 | IMR &= ~(1<<14); /* bit 14 is DMA0 */ |
300 | 300 | ||
301 | pcm_set_frequency(44100); | 301 | pcm_set_frequency(44100); |
diff --git a/firmware/pcm_record.c b/firmware/pcm_record.c index 8480864513..8b46a09ed3 100644 --- a/firmware/pcm_record.c +++ b/firmware/pcm_record.c | |||
@@ -570,7 +570,7 @@ static void pcmrec_open(void) | |||
570 | DIVR1 = 55; /* DMA1 is mapped into vector 55 in system.c */ | 570 | DIVR1 = 55; /* DMA1 is mapped into vector 55 in system.c */ |
571 | DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */ | 571 | DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */ |
572 | DMAROUTE = (DMAROUTE & 0xffff00ff) | DMA1_REQ_AUDIO_2; | 572 | DMAROUTE = (DMAROUTE & 0xffff00ff) | DMA1_REQ_AUDIO_2; |
573 | ICR4 = (ICR4 & 0xffffff00) | 0x0000001c; /* Enable interrupt at level 7, priority 0 */ | 573 | ICR7 = 0x1c; /* Enable interrupt at level 7, priority 0 */ |
574 | IMR &= ~(1<<15); /* bit 15 is DMA1 */ | 574 | IMR &= ~(1<<15); /* bit 15 is DMA1 */ |
575 | 575 | ||
576 | init_done = 1; | 576 | init_done = 1; |
@@ -585,8 +585,8 @@ static void pcmrec_close(void) | |||
585 | #endif | 585 | #endif |
586 | 586 | ||
587 | DMAROUTE = (DMAROUTE & 0xffff00ff); | 587 | DMAROUTE = (DMAROUTE & 0xffff00ff); |
588 | ICR4 = (ICR4 & 0xffffff00); /* Disable interrupt */ | 588 | ICR7 = 0x00; /* Disable interrupt */ |
589 | IMR |= (1<<15); /* bit 15 is DMA1 */ | 589 | IMR |= (1<<15); /* bit 15 is DMA1 */ |
590 | 590 | ||
591 | } | 591 | } |
592 | 592 | ||
diff --git a/firmware/timer.c b/firmware/timer.c index 8aff4eb6ee..e5b5b68b11 100644 --- a/firmware/timer.c +++ b/firmware/timer.c | |||
@@ -174,8 +174,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), | |||
174 | IPRD = (IPRD & 0xFF0F) | int_prio << 4; /* interrupt priority */ | 174 | IPRD = (IPRD & 0xFF0F) | int_prio << 4; /* interrupt priority */ |
175 | or_b(0x10, &TSTR); /* start timer 4 */ | 175 | or_b(0x10, &TSTR); /* start timer 4 */ |
176 | #elif defined CPU_COLDFIRE | 176 | #elif defined CPU_COLDFIRE |
177 | /* ICR2 (Timer1) */ | 177 | ICR2 = 0x90; /* interrupt on level 4.0 */ |
178 | ICR0 = (ICR0 & 0xffff00ff) | 0x00009000; /* interrupt on level 4.0 */ | ||
179 | and_l(~(1<<10), &IMR); | 178 | and_l(~(1<<10), &IMR); |
180 | TMR1 |= 1; /* start timer */ | 179 | TMR1 |= 1; /* start timer */ |
181 | #endif | 180 | #endif |