From 72f98786a0b73722d2688c7509a1acc528b727af Mon Sep 17 00:00:00 2001 From: Jens Arnold Date: Sat, 5 Nov 2005 03:28:20 +0000 Subject: Fixup of the MCF5249 memory mapped register definitions. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7755 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/mcf5249.h | 49 ++++++++++++++++++++++++++++++----------------- firmware/kernel.c | 2 +- firmware/pcm_playback.c | 6 +++--- firmware/pcm_record.c | 6 +++--- firmware/timer.c | 3 +-- 5 files changed, 39 insertions(+), 27 deletions(-) diff --git a/firmware/export/mcf5249.h b/firmware/export/mcf5249.h index e2fa50e672..406e0b1c1b 100644 --- a/firmware/export/mcf5249.h +++ b/firmware/export/mcf5249.h @@ -22,14 +22,27 @@ #define MBAR 0x40000000 #define MBAR2 0x80000000 -#define SYSTEM_CTRL (*(volatile unsigned char *)(MBAR + 0x000)) -#define BUSMASTER_CTRL (*(volatile unsigned char *)(MBAR + 0x00c)) +#define RSR (*(volatile unsigned char *)(MBAR + 0x000)) +#define SYPCR (*(volatile unsigned char *)(MBAR + 0x001)) +#define SWIVR (*(volatile unsigned char *)(MBAR + 0x002)) +#define SWSR (*(volatile unsigned char *)(MBAR + 0x003)) -#define IPR (*(volatile unsigned long *)(MBAR + 0x040)) -#define IMR (*(volatile unsigned long *)(MBAR + 0x044)) -#define ICR0 (*(volatile unsigned long *)(MBAR + 0x04c)) -#define ICR4 (*(volatile unsigned long *)(MBAR + 0x050)) -#define ICR8 (*(volatile unsigned long *)(MBAR + 0x054)) +#define MPARK (*(volatile unsigned char *)(MBAR + 0x00c)) + +#define IPR (*(volatile unsigned long *)(MBAR + 0x040)) +#define IMR (*(volatile unsigned long *)(MBAR + 0x044)) +#define ICR0 (*(volatile unsigned char *)(MBAR + 0x04c)) +#define ICR1 (*(volatile unsigned char *)(MBAR + 0x04d)) +#define ICR2 (*(volatile unsigned char *)(MBAR + 0x04e)) +#define ICR3 (*(volatile unsigned char *)(MBAR + 0x04f)) +#define ICR4 (*(volatile unsigned char *)(MBAR + 0x050)) +#define ICR5 (*(volatile unsigned char *)(MBAR + 0x051)) +#define ICR6 (*(volatile unsigned char *)(MBAR + 0x052)) +#define ICR7 (*(volatile unsigned char *)(MBAR + 0x053)) +#define ICR8 (*(volatile unsigned char *)(MBAR + 0x054)) +#define ICR9 (*(volatile unsigned char *)(MBAR + 0x055)) +#define ICR10 (*(volatile unsigned char *)(MBAR + 0x056)) +#define ICR11 (*(volatile unsigned char *)(MBAR + 0x057)) #define CSAR0 (*(volatile unsigned long *)(MBAR + 0x080)) #define CSMR0 (*(volatile unsigned long *)(MBAR + 0x084)) @@ -53,12 +66,12 @@ #define TRR0 (*(volatile unsigned short *)(MBAR + 0x144)) #define TCR0 (*(volatile unsigned short *)(MBAR + 0x148)) #define TCN0 (*(volatile unsigned short *)(MBAR + 0x14c)) -#define TER0 (*(volatile unsigned short *)(MBAR + 0x150)) +#define TER0 (*(volatile unsigned char *)(MBAR + 0x151)) #define TMR1 (*(volatile unsigned short *)(MBAR + 0x180)) #define TRR1 (*(volatile unsigned short *)(MBAR + 0x184)) #define TCR1 (*(volatile unsigned short *)(MBAR + 0x188)) #define TCN1 (*(volatile unsigned short *)(MBAR + 0x18c)) -#define TER1 (*(volatile unsigned short *)(MBAR + 0x190)) +#define TER1 (*(volatile unsigned char *)(MBAR + 0x191)) #define UMR0 (*(volatile unsigned char *)(MBAR + 0x1c0)) #define USR0 (*(volatile unsigned char *)(MBAR + 0x1c4)) @@ -133,11 +146,11 @@ #define QSPIQWR (*(volatile unsigned short *)(MBAR + 0x408)) #define QSPIQIR (*(volatile unsigned short *)(MBAR + 0x40c)) #define QSPIQAR (*(volatile unsigned short *)(MBAR + 0x410)) -#define QIR (*(volatile unsigned short *)(MBAR + 0x414)) +#define QSPIQDR (*(volatile unsigned short *)(MBAR + 0x414)) -#define GPIO_READ (*(volatile unsigned long *)(MBAR2 + 0x000)) -#define GPIO_OUT (*(volatile unsigned long *)(MBAR2 + 0x004)) -#define GPIO_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x008)) +#define GPIO_READ (*(volatile unsigned long *)(MBAR2 + 0x000)) +#define GPIO_OUT (*(volatile unsigned long *)(MBAR2 + 0x004)) +#define GPIO_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x008)) #define GPIO_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x00c)) #define IIS1CONFIG (*(volatile unsigned long *)(MBAR2 + 0x010)) @@ -177,9 +190,11 @@ #define U2CHANNELRECEIVE (*(volatile unsigned long *)(MBAR2 + 0x0d8)) #define Q2CHANNELRECEIVE (*(volatile unsigned long *)(MBAR2 + 0x0dc)) -#define GPIO1_READ (*(volatile unsigned long *)(MBAR2 + 0x0b0)) -#define GPIO1_OUT (*(volatile unsigned long *)(MBAR2 + 0x0b4)) -#define GPIO1_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x0b8)) +#define DEVICE_ID (*(volatile unsigned long *)(MBAR2 + 0x0ac)) + +#define GPIO1_READ (*(volatile unsigned long *)(MBAR2 + 0x0b0)) +#define GPIO1_OUT (*(volatile unsigned long *)(MBAR2 + 0x0b4)) +#define GPIO1_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x0b8)) #define GPIO1_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x0bc)) #define GPIO_INT_STAT (*(volatile unsigned long *)(MBAR2 + 0x0c0)) #define GPIO_INT_CLEAR (*(volatile unsigned long *)(MBAR2 + 0x0c0)) @@ -222,8 +237,6 @@ #define FLASHMEDIAINTSTAT (*(volatile unsigned long *)(MBAR2 + 0x47c)) #define FLASHMEDIAINTCLEAR (*(volatile unsigned long *)(MBAR2 + 0x47c)) -#define DEVICE_ID (*(volatile unsigned long *)(MBAR2 + 0x0ac)) - /* DMA Registers ... */ #define O_SAR 0x00 /* Source Address */ diff --git a/firmware/kernel.c b/firmware/kernel.c index ee4e37e50d..9af4566662 100644 --- a/firmware/kernel.c +++ b/firmware/kernel.c @@ -233,7 +233,7 @@ void tick_start(unsigned int interval_in_ms) TER0 = 0xff; /* Clear all events */ - ICR0 = (ICR0 & 0xff00ffff) | 0x008c0000; /* Interrupt on level 3.0 */ + ICR1 = 0x8c; /* Interrupt on level 3.0 */ IMR &= ~0x200; } diff --git a/firmware/pcm_playback.c b/firmware/pcm_playback.c index 5597f69bdb..21c4bf8c04 100644 --- a/firmware/pcm_playback.c +++ b/firmware/pcm_playback.c @@ -286,8 +286,8 @@ void pcm_init(void) pcm_playing = false; pcm_paused = false; - BUSMASTER_CTRL = 0x81; /* PARK[1,0]=10 + BCR24BIT */ - DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */ + MPARK = 0x81; /* PARK[1,0]=10 + BCR24BIT */ + DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */ DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1; DMACONFIG = 1; /* DMA0Req = PDOR3 */ @@ -295,7 +295,7 @@ void pcm_init(void) IIS2CONFIG = IIS_RESET; /* Enable interrupt at level 7, priority 0 */ - ICR4 = (ICR4 & 0xffff00ff) | 0x00001c00; + ICR6 = 0x1c; IMR &= ~(1<<14); /* bit 14 is DMA0 */ pcm_set_frequency(44100); diff --git a/firmware/pcm_record.c b/firmware/pcm_record.c index 8480864513..8b46a09ed3 100644 --- a/firmware/pcm_record.c +++ b/firmware/pcm_record.c @@ -570,7 +570,7 @@ static void pcmrec_open(void) DIVR1 = 55; /* DMA1 is mapped into vector 55 in system.c */ DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */ DMAROUTE = (DMAROUTE & 0xffff00ff) | DMA1_REQ_AUDIO_2; - ICR4 = (ICR4 & 0xffffff00) | 0x0000001c; /* Enable interrupt at level 7, priority 0 */ + ICR7 = 0x1c; /* Enable interrupt at level 7, priority 0 */ IMR &= ~(1<<15); /* bit 15 is DMA1 */ init_done = 1; @@ -585,8 +585,8 @@ static void pcmrec_close(void) #endif DMAROUTE = (DMAROUTE & 0xffff00ff); - ICR4 = (ICR4 & 0xffffff00); /* Disable interrupt */ - IMR |= (1<<15); /* bit 15 is DMA1 */ + ICR7 = 0x00; /* Disable interrupt */ + IMR |= (1<<15); /* bit 15 is DMA1 */ } diff --git a/firmware/timer.c b/firmware/timer.c index 8aff4eb6ee..e5b5b68b11 100644 --- a/firmware/timer.c +++ b/firmware/timer.c @@ -174,8 +174,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), IPRD = (IPRD & 0xFF0F) | int_prio << 4; /* interrupt priority */ or_b(0x10, &TSTR); /* start timer 4 */ #elif defined CPU_COLDFIRE - /* ICR2 (Timer1) */ - ICR0 = (ICR0 & 0xffff00ff) | 0x00009000; /* interrupt on level 4.0 */ + ICR2 = 0x90; /* interrupt on level 4.0 */ and_l(~(1<<10), &IMR); TMR1 |= 1; /* start timer */ #endif -- cgit v1.2.3