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| author | Michael Sevakis <jethead71@rockbox.org> | 2008-05-07 06:13:35 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2008-05-07 06:13:35 +0000 |
| commit | 607b63a8278bfce55ca32356c5df17e2a029eda0 (patch) | |
| tree | e831207831ae9ce98409fbc808e0df24151a5863 | |
| parent | bc1ce741c95faa7f918bb39de7cfe9eed9b34f57 (diff) | |
| download | rockbox-607b63a8278bfce55ca32356c5df17e2a029eda0.tar.gz rockbox-607b63a8278bfce55ca32356c5df17e2a029eda0.zip | |
Gigabeat S technical correction: Fix instruction order because clean dcache operand is SBZ.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17401 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/target/arm/imx31/crt0.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S index bc63a7d085..046578b5bf 100644 --- a/firmware/target/arm/imx31/crt0.S +++ b/firmware/target/arm/imx31/crt0.S | |||
| @@ -76,8 +76,8 @@ remap_start: | |||
| 76 | mrc p15, 0, r3, c1, c0, 0 /* perform writeback if D cache is enabled */ | 76 | mrc p15, 0, r3, c1, c0, 0 /* perform writeback if D cache is enabled */ |
| 77 | tst r3, #(1 << 2) /* dcache? */ | 77 | tst r3, #(1 << 2) /* dcache? */ |
| 78 | tsteq r3, #(1 << 12) /* or icache? */ | 78 | tsteq r3, #(1 << 12) /* or icache? */ |
| 79 | mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */ | ||
| 80 | mov r0, #0 | 79 | mov r0, #0 |
| 80 | mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */ | ||
| 81 | mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ | 81 | mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ |
| 82 | mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ | 82 | mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ |
| 83 | mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ | 83 | mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ |