From 607b63a8278bfce55ca32356c5df17e2a029eda0 Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Wed, 7 May 2008 06:13:35 +0000 Subject: Gigabeat S technical correction: Fix instruction order because clean dcache operand is SBZ. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17401 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/imx31/crt0.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S index bc63a7d085..046578b5bf 100644 --- a/firmware/target/arm/imx31/crt0.S +++ b/firmware/target/arm/imx31/crt0.S @@ -76,8 +76,8 @@ remap_start: mrc p15, 0, r3, c1, c0, 0 /* perform writeback if D cache is enabled */ tst r3, #(1 << 2) /* dcache? */ tsteq r3, #(1 << 12) /* or icache? */ - mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */ mov r0, #0 + mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */ mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ -- cgit v1.2.3