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authorDave Chapman <dave@dchapman.com>2009-09-17 08:05:19 +0000
committerDave Chapman <dave@dchapman.com>2009-09-17 08:05:19 +0000
commit43ec944e3c0c31a7b4bedbb371f1ce9c1c24a80d (patch)
treef63c1452752ff80ac06cd0c56f5b57b0cfde4ebd
parentd67c4d2f6ba5bde26ca6e121064d4da116e868c5 (diff)
downloadrockbox-43ec944e3c0c31a7b4bedbb371f1ce9c1c24a80d.tar.gz
rockbox-43ec944e3c0c31a7b4bedbb371f1ce9c1c24a80d.zip
TIMERB is in a different location on the S5L8701
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22716 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/export/s5l8700.h5
-rw-r--r--firmware/target/arm/s5l8700/kernel-s5l8700.c2
-rw-r--r--firmware/target/arm/s5l8700/system-s5l8700.c14
3 files changed, 18 insertions, 3 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
index cfd8e59ad6..f43b9f408c 100644
--- a/firmware/export/s5l8700.h
+++ b/firmware/export/s5l8700.h
@@ -125,6 +125,11 @@
125#define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ 125#define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */
126#define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ 126#define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */
127#define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ 127#define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */
128#if CONFIG_CPU==S5L8701
129#define INTMSK_TIMERB (1<<5)
130#else
131#define INTMSK_TIMERB (1<<7)
132#endif
128#define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ 133#define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */
129#define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ 134#define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */
130#define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ 135#define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */
diff --git a/firmware/target/arm/s5l8700/kernel-s5l8700.c b/firmware/target/arm/s5l8700/kernel-s5l8700.c
index 6f131d93f8..21b73e466d 100644
--- a/firmware/target/arm/s5l8700/kernel-s5l8700.c
+++ b/firmware/target/arm/s5l8700/kernel-s5l8700.c
@@ -54,6 +54,6 @@ void tick_start(unsigned int interval_in_ms)
54 TBCMD = (1 << 0); /* TB_EN */ 54 TBCMD = (1 << 0); /* TB_EN */
55 55
56 /* enable timer interrupt */ 56 /* enable timer interrupt */
57 INTMSK |= (1 << 7); 57 INTMSK |= INTMSK_TIMERB;
58} 58}
59 59
diff --git a/firmware/target/arm/s5l8700/system-s5l8700.c b/firmware/target/arm/s5l8700/system-s5l8700.c
index 48c50645e9..da1811dc11 100644
--- a/firmware/target/arm/s5l8700/system-s5l8700.c
+++ b/firmware/target/arm/s5l8700/system-s5l8700.c
@@ -66,7 +66,12 @@ default_interrupt(INT_ADC);
66 66
67static void (* const irqvector[])(void) = 67static void (* const irqvector[])(void) =
68{ 68{
69 EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB, 69 EXT0,EXT1,EXT2,EINT_VBUS,EINTG,
70#if CONFIG_CPU==S5L8701
71 INT_TIMERB,INT_WDT,INT_TIMERA,
72#else
73 INT_TIMERA,INT_WDT,INT_TIMERB,
74#endif
70 INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST, 75 INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
71 INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT, 76 INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
72 INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC 77 INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
@@ -74,7 +79,12 @@ static void (* const irqvector[])(void) =
74 79
75static const char * const irqname[] = 80static const char * const irqname[] =
76{ 81{
77 "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB", 82 "EXT0","EXT1","EXT2","EINT_VBUS","EINTG",
83#if CONFIG_CPU==S5L8701
84 "INT_TIMERB","INT_WDT","INT_TIMERA",
85#else
86 "INT_TIMERA","INT_WDT","INT_TIMERB",
87#endif
78 "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST", 88 "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
79 "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT", 89 "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
80 "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC" 90 "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"