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authorDave Chapman <dave@dchapman.com>2009-09-17 07:36:09 +0000
committerDave Chapman <dave@dchapman.com>2009-09-17 07:36:09 +0000
commitd67c4d2f6ba5bde26ca6e121064d4da116e868c5 (patch)
tree2769b9fff7e8e555e19d8ace569e77b4177fae77
parent8dae933293223e28648ec72ac818ab2a98ee2482 (diff)
downloadrockbox-d67c4d2f6ba5bde26ca6e121064d4da116e868c5.tar.gz
rockbox-d67c4d2f6ba5bde26ca6e121064d4da116e868c5.zip
Add PLL2 definitions for the S5L8701, plus some config file tweaks for the Nano2G
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22715 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/export/config-ipodnano2g.h20
-rw-r--r--firmware/export/config.h1
-rw-r--r--firmware/export/s5l8700.h2
3 files changed, 9 insertions, 14 deletions
diff --git a/firmware/export/config-ipodnano2g.h b/firmware/export/config-ipodnano2g.h
index 02277adcaa..31830fd2c1 100644
--- a/firmware/export/config-ipodnano2g.h
+++ b/firmware/export/config-ipodnano2g.h
@@ -9,11 +9,11 @@
9#define MODEL_NAME "Apple iPod Nano 2g" 9#define MODEL_NAME "Apple iPod Nano 2g"
10 10
11/* define this if you have recording possibility */ 11/* define this if you have recording possibility */
12//#define HAVE_RECORDING 12#define HAVE_RECORDING
13 13
14/* Define bitmask of input sources - recordable bitmask can be defined 14/* Define bitmask of input sources - recordable bitmask can be defined
15 explicitly if different */ 15 explicitly if different */
16#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_FMRADIO) 16#define INPUT_SRC_CAPS (SRC_CAP_LINEIN)
17 17
18/* define the bitmask of hardware sample rates */ 18/* define the bitmask of hardware sample rates */
19#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11) 19#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
@@ -86,7 +86,7 @@
86#define CONFIG_LCD LCD_NANO2G 86#define CONFIG_LCD LCD_NANO2G
87 87
88/* Define the type of audio codec */ 88/* Define the type of audio codec */
89#define HAVE_UDA1380 89#define HAVE_WM8975
90 90
91/* Define this for LCD backlight available */ 91/* Define this for LCD backlight available */
92#define HAVE_BACKLIGHT 92#define HAVE_BACKLIGHT
@@ -101,14 +101,6 @@
101/* The number of bytes reserved for loadable plugins */ 101/* The number of bytes reserved for loadable plugins */
102#define PLUGIN_BUFFER_SIZE 0x80000 102#define PLUGIN_BUFFER_SIZE 0x80000
103 103
104/* FM Tuner */
105#define CONFIG_TUNER TEA5760
106#define CONFIG_TUNER_XTAL 32768
107
108//#define HAVE_TLV320
109
110/* TLV320 has no tone controls, so we use the software ones */
111#define HAVE_SW_TONE_CONTROLS
112 104
113#define BATTERY_CAPACITY_DEFAULT 700 /* default battery capacity */ 105#define BATTERY_CAPACITY_DEFAULT 700 /* default battery capacity */
114#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ 106#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */
@@ -124,10 +116,10 @@
124/* Define this if your LCD can set contrast */ 116/* Define this if your LCD can set contrast */
125//#define HAVE_LCD_CONTRAST 117//#define HAVE_LCD_CONTRAST
126 118
127/* Define this if you have a Motorola SCF5250 */ 119/* The exact type of CPU */
128#define CONFIG_CPU S5L8701 120#define CONFIG_CPU S5L8701
129 121
130/* Define this if you want to use coldfire's i2c interface */ 122/* I2C interface */
131#define CONFIG_I2C I2C_S5L8700 123#define CONFIG_I2C I2C_S5L8700
132 124
133/* define this if the hardware can be powered off while charging */ 125/* define this if the hardware can be powered off while charging */
@@ -137,7 +129,7 @@
137#define FLASH_SIZE 0x400000 129#define FLASH_SIZE 0x400000
138 130
139/* Define this to the CPU frequency */ 131/* Define this to the CPU frequency */
140#define CPU_FREQ 11289600 132#define CPU_FREQ 200000000
141 133
142/* Define this if you have ATA power-off control */ 134/* Define this if you have ATA power-off control */
143//#define HAVE_ATA_POWER_OFF 135//#define HAVE_ATA_POWER_OFF
diff --git a/firmware/export/config.h b/firmware/export/config.h
index 331c7d75d9..a1a8a9df2a 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -197,6 +197,7 @@
197#define LCD_LYRE_PROTO1 33 /* as used by the Lyre */ 197#define LCD_LYRE_PROTO1 33 /* as used by the Lyre */
198#define LCD_YH925 34 /* as used by Samsung YH-925 (similar to the H10 20GB) */ 198#define LCD_YH925 34 /* as used by Samsung YH-925 (similar to the H10 20GB) */
199#define LCD_VIEW 35 /* as used by the Sansa View */ 199#define LCD_VIEW 35 /* as used by the Sansa View */
200#define LCD_NANO2G 36 /* as used by the iPod Nano 2nd Generation */
200 201
201/* LCD_PIXELFORMAT */ 202/* LCD_PIXELFORMAT */
202#define HORIZONTAL_PACKING 1 203#define HORIZONTAL_PACKING 1
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
index 4360f14a2d..cfd8e59ad6 100644
--- a/firmware/export/s5l8700.h
+++ b/firmware/export/s5l8700.h
@@ -108,8 +108,10 @@
108#define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */ 108#define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */
109#define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */ 109#define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */
110#define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */ 110#define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */
111#define PLL2PMS (*(REG32_PTR_T)(0x3C50000C)) /* PLL PMS value Register - S5L8701 only? */
111#define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ 112#define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */
112#define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ 113#define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */
114#define PLL2LCNT (*(REG32_PTR_T)(0x3C50001C)) /* PLL2 lock count register - S5L8701 only? */
113#define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ 115#define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */
114#define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ 116#define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */
115#define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ 117#define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */