imx233: add DCP driver (only memcpy implemented), move channel arbiter to kernel-imx233

Change-Id: I2bc5a49459c354027fc67a880bbf3b87c942bdd0

8 files changed, 663 insertions, 52 deletions

diff --git a/firmware/SOURCES b/firmware/SOURCES
index 4d0d71222f..438c9e6526 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -542,6 +542,7 @@ target/arm/imx233/powermgmt-imx233.c
 target/arm/imx233/adc-imx233.c
 target/arm/imx233/lradc-imx233.c
 target/arm/imx233/rtc-imx233.c
+target/arm/imx233/dcp-imx233.c
 #ifndef BOOTLOADER
 target/arm/imx233/debug-imx233.c
 #endif
diff --git a/firmware/target/arm/imx233/dcp-imx233.c b/firmware/target/arm/imx233/dcp-imx233.c
new file mode 100644
index 0000000000..565dba7691
--- /dev/null
+++ b/firmware/target/arm/imx233/dcp-imx233.c
@@ -0,0 +1,198 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2011 by amaury Pouly
+ *
+ * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
+ * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
+ * 
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "system.h"
+#include "dcp-imx233.h"
+#include "string.h"
+#include "kernel-imx233.h"
+
+/* The hardware uses 160 bytes of storage to enable context switching */
+static uint8_t dcp_context[160] NOCACHEBSS_ATTR;
+/* Channel arbiter */
+static struct channel_arbiter_t channel_arbiter;
+/* Channel packets */
+static struct imx233_dcp_packet_t channel_packet[HW_DCP_NUM_CHANNELS];
+/* completion semaphore */
+static struct semaphore channel_sema[HW_DCP_NUM_CHANNELS];
+
+void INT_DCP(void)
+{
+    /* clear interrupt and wakeup completion handler */
+    for(int i = 0; i < HW_DCP_NUM_CHANNELS; i++)
+    {
+        if(HW_DCP_STAT & HW_DCP_STAT__IRQ(i))
+        {
+            __REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(i);
+            semaphore_release(&channel_sema[i]);
+        }
+    }
+}
+
+void imx233_dcp_init(void)
+{
+    /* Reset block */
+    imx233_reset_block(&HW_DCP_CTRL);
+    /* Setup contexte pointer */
+    HW_DCP_CONTEXT = (uint32_t)PHYSICAL_ADDR(&dcp_context);
+    /* Enable context switching and caching */
+    __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__ENABLE_CONTEXT_CACHING |
+        HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING;
+    /* Check that there are sufficiently many channels */
+    if(__XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS) != HW_DCP_NUM_CHANNELS)
+        panicf("DCP has %lu channels but was configured to use %d !",
+               __XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS), HW_DCP_NUM_CHANNELS);
+    /* Setup channel arbiter to use */
+    arbiter_init(&channel_arbiter, HW_DCP_NUM_CHANNELS);
+    /* Merge channel0 interrupt */
+    __REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED;
+    /* setup semaphores */
+    for(int i = 0; i< HW_DCP_NUM_CHANNELS; i++)
+        semaphore_init(&channel_sema[i], 1, 0);
+}
+
+// return OBJ_WAIT_TIMEOUT on failure
+int imx233_dcp_acquire_channel(int timeout)
+{
+    return arbiter_acquire(&channel_arbiter, timeout);
+}
+
+void imx233_dcp_release_channel(int chan)
+{
+    arbiter_release(&channel_arbiter, chan);
+}
+
+// doesn't check that channel is in use!
+void imx233_dcp_reserve_channel(int channel)
+{
+    arbiter_reserve(&channel_arbiter, channel);
+}
+
+static enum imx233_dcp_error_t get_error_status(int ch)
+{
+    uint32_t stat = channel_packet[ch].status;
+    if(stat & HW_DCP_STATUS__ERROR_SETUP)
+        return DCP_ERROR_SETUP;
+    if(stat & HW_DCP_STATUS__ERROR_PACKET)
+        return DCP_ERROR_PACKET;
+    if(stat & HW_DCP_STATUS__ERROR_SRC)
+        return DCP_ERROR_SRC;
+    if(stat & HW_DCP_STATUS__ERROR_DST)
+        return DCP_ERROR_DST;
+    switch(__XTRACT_EX(stat, HW_DCP_STATUS__ERROR_CODE))
+    {
+        case 0: return DCP_SUCCESS;
+        case 1: return DCP_ERROR_CHAIN_IS_0;
+        case 2: return DCP_ERROR_NO_CHAIN;
+        case 3: return DCP_ERROR_CONTEXT;
+        case 4: return DCP_ERROR_PAYLOAD;
+        case 5: return DCP_ERROR_MODE;
+        default: return DCP_ERROR;
+    }
+}
+
+enum imx233_dcp_error_t imx233_dcp_memcpy_ex(int ch, void *src, void *dst, size_t len)
+{
+    /* enable channel, clear interrupt, enable interrupt */
+    imx233_enable_interrupt(INT_SRC_DCP, true);
+    __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch);
+    __REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(ch);
+    __REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(ch);
+
+    /* prepare packet */
+    channel_packet[ch].next = 0;
+    channel_packet[ch].ctrl0 = HW_DCP_CTRL0__INTERRUPT_ENABLE |
+        HW_DCP_CTRL0__ENABLE_MEMCOPY | HW_DCP_CTRL0__DECR_SEMAPHORE;
+    channel_packet[ch].ctrl1 = 0;
+    channel_packet[ch].src = (uint32_t)PHYSICAL_ADDR(src);
+    channel_packet[ch].dst = (uint32_t)PHYSICAL_ADDR(dst);
+    channel_packet[ch].size = len;
+    channel_packet[ch].payload = 0;
+    channel_packet[ch].status = 0;
+
+    /* write-back src, discard dst, write-back packet */
+    commit_discard_dcache_range(src, len);
+    discard_dcache_range(dst, len);
+    commit_discard_dcache_range(&channel_packet[ch], sizeof(struct imx233_dcp_packet_t));
+    /* write 1 to semaphore to run job */
+    HW_DCP_CHxCMDPTR(ch) = (uint32_t)PHYSICAL_ADDR(&channel_packet[ch]);
+    HW_DCP_CHxSEMA(ch) = 1;
+    /* wait completion */
+    semaphore_wait(&channel_sema[ch], TIMEOUT_BLOCK);
+    /* read status */
+    return get_error_status(ch);
+}
+
+enum imx233_dcp_error_t imx233_dcp_memcpy(void *src, void *dst, size_t len, int tmo)
+{
+    int chan = imx233_dcp_acquire_channel(tmo);
+    if(chan == OBJ_WAIT_TIMEDOUT)
+        return DCP_TIMEOUT;
+    enum imx233_dcp_error_t err = imx233_dcp_memcpy_ex(chan, src, dst, len);
+    imx233_dcp_release_channel(chan);
+    return err;
+}
+
+struct imx233_dcp_info_t imx233_dcp_get_info(unsigned flags)
+{
+    struct imx233_dcp_info_t info;
+    memset(&info, 0, sizeof(info));
+    if(flags & DCP_INFO_CAPABILITIES)
+    {
+        info.has_crypto = HW_DCP_CTRL & HW_DCP_CTRL__PRESENT_CRYPTO;
+        info.has_csc = HW_DCP_CTRL & HW_DCP_CTRL__PRESENT_CSC;
+        info.num_keys = __XTRACT(HW_DCP_CAPABILITY0, NUM_KEYS);
+        info.num_channels = __XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS);
+        info.ciphers = __XTRACT(HW_DCP_CAPABILITY1, CIPHER_ALGORITHMS);
+        info.hashs = __XTRACT(HW_DCP_CAPABILITY1, HASH_ALGORITHMS);
+    }
+    if(flags & DCP_INFO_GLOBAL_STATE)
+    {
+        info.otp_key_ready = HW_DCP_STAT & HW_DCP_STAT__OTP_KEY_READY;
+        info.context_switching = HW_DCP_CTRL & HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING;
+        info.context_caching = HW_DCP_CTRL & HW_DCP_CTRL__ENABLE_CONTEXT_CACHING;
+        info.gather_writes = HW_DCP_CTRL & HW_DCP_CTRL__GATHER_RESIDUAL_WRITES;
+        info.ch0_merged = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED;
+    }
+    if(flags & DCP_INFO_CHANNELS)
+    {
+        for(int i = 0; i < HW_DCP_NUM_CHANNELS; i++)
+        {
+            info.channel[i].irq_en = HW_DCP_CTRL & HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(i);
+            info.channel[i].irq = HW_DCP_STAT & HW_DCP_STAT__IRQ(i);
+            info.channel[i].ready = HW_DCP_STAT & HW_DCP_STAT__READY_CHANNELS(i);
+            info.channel[i].high_priority = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL(i);
+            info.channel[i].enable = HW_DCP_CHANNELCTRL & HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(i);
+            info.channel[i].sema = __XTRACT_EX(HW_DCP_CHxSEMA(i), HW_DCP_CHxSEMA__VALUE);
+            info.channel[i].cmdptr = HW_DCP_CHxCMDPTR(i);
+        }
+    }
+    if(flags & DCP_INFO_CSC)
+    {
+        info.csc.irq_en = HW_DCP_CTRL & HW_DCP_CTRL__CSC_INTERRUPT_ENABLE;
+        info.csc.irq = HW_DCP_STAT & HW_DCP_STAT__CSCIRQ;
+        info.csc.priority = __XTRACT(HW_DCP_CHANNELCTRL, CSC_PRIORITY);
+        info.csc.enable = HW_DCP_CSCCTRL0 & HW_DCP_CSCCTRL0__ENABLE;
+    }
+    return info;
+}
\ No newline at end of file
diff --git a/firmware/target/arm/imx233/dcp-imx233.h b/firmware/target/arm/imx233/dcp-imx233.h
new file mode 100644
index 0000000000..375da16c04
--- /dev/null
+++ b/firmware/target/arm/imx233/dcp-imx233.h
@@ -0,0 +1,363 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2011 by amaury Pouly
+ *
+ * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
+ * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
+ * 
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __DCP_IMX233_H__
+#define __DCP_IMX233_H__
+
+#include "cpu.h"
+#include "system.h"
+#include "system-target.h"
+
+#define HW_DCP_BASE         0x80028000
+
+/* channels */
+#define HW_DCP_CH(x)    (x)
+#define HW_DCP_NUM_CHANNELS 4
+#define HW_DCP_CSC      8
+
+/* ciphers */
+#define HW_DCP_CIPHER_AES128    1
+
+/* hash */
+#define HW_DCP_HASH_SHA1    1
+#define HW_DCP_HASH_CRC32   2
+
+#define HW_DCP_CTRL         (*(volatile uint32_t *)(HW_DCP_BASE + 0x0))
+#define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE_BP    0
+#define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE_BM    0xf
+#define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(x)    (1 << (x))
+#define HW_DCP_CTRL__CSC_INTERRUPT_ENABLE   (1 << 8)
+#define HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING   (1 << 21)
+#define HW_DCP_CTRL__ENABLE_CONTEXT_CACHING (1 << 22)
+#define HW_DCP_CTRL__GATHER_RESIDUAL_WRITES (1 << 23)
+#define HW_DCP_CTRL__PRESENT_CSC    (1 << 28)
+#define HW_DCP_CTRL__PRESENT_CRYPTO (1 << 29)
+
+#define HW_DCP_STAT         (*(volatile uint32_t *)(HW_DCP_BASE + 0x10))
+#define HW_DCP_STAT__IRQ_BP 0
+#define HW_DCP_STAT__IRQ_BM 0xf
+#define HW_DCP_STAT__IRQ(x) (1 << (x))
+#define HW_DCP_STAT__CSCIRQ (1 << 8)
+#define HW_DCP_STAT__READY_CHANNELS_BP  16
+#define HW_DCP_STAT__READY_CHANNELS_BM  (0xff << 16)
+#define HW_DCP_STAT__READY_CHANNELS(x)  (1 << (16 + (x)))
+#define HW_DCP_STAT__CUR_CHANNEL_BP 24
+#define HW_DCP_STAT__CUR_CHANNEL_BM (0xf << 24)
+#define HW_DCP_STAT__OTP_KEY_READY  (1 << 28)
+
+#define HW_DCP_CHANNELCTRL  (*(volatile uint32_t *)(HW_DCP_BASE + 0x20))
+#define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL_BP   0
+#define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL_BM   0xff
+#define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(x)   (1 << (x))
+#define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL_BP    8
+#define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL_BM    (0xff << 8)
+#define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL(x)    (1 << (8 + (x)))
+#define HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED  (1 << 16)
+#define HW_DCP_CHANNELCTRL__CSC_PRIORITY_BP 17
+#define HW_DCP_CHANNELCTRL__CSC_PRIORITY_BM (3 << 17)
+
+#define HW_DCP_CAPABILITY0  (*(volatile uint32_t *)(HW_DCP_BASE + 0x30))
+#define HW_DCP_CAPABILITY0__NUM_KEYS_BP 0
+#define HW_DCP_CAPABILITY0__NUM_KEYS_BM 0xff
+#define HW_DCP_CAPABILITY0__NUM_CHANNELS_BP 8
+#define HW_DCP_CAPABILITY0__NUM_CHANNELS_BM 0xf00
+#define HW_DCP_CAPABILITY0__ENABLE_TZONE    (1 << 30)
+#define HW_DCP_CAPABILITY0__DISABLE_DECRYPT (1 << 31)
+
+#define HW_DCP_CAPABILITY1  (*(volatile uint32_t *)(HW_DCP_BASE + 0x40))
+#define HW_DCP_CAPABILITY1__CIPHER_ALGORITHMS_BP    0
+#define HW_DCP_CAPABILITY1__CIPHER_ALGORITHMS_BM    0xffff
+#define HW_DCP_CAPABILITY1__HASH_ALGORITHMS_BP      16
+#define HW_DCP_CAPABILITY1__HASH_ALGORITHMS_BM      0xffff0000
+
+#define HW_DCP_CONTEXT      (*(volatile uint32_t *)(HW_DCP_BASE + 0x50))
+
+#define HW_DCP_KEY          (*(volatile uint32_t *)(HW_DCP_BASE + 0x60))
+
+#define HW_DCP_KEYDATA      (*(volatile uint32_t *)(HW_DCP_BASE + 0x70))
+
+#define HW_DCP_PACKET0      (*(volatile uint32_t *)(HW_DCP_BASE + 0x80))
+
+#define HW_DCP_PACKET1      (*(volatile uint32_t *)(HW_DCP_BASE + 0x90))
+
+#define HW_DCP_PACKET2      (*(volatile uint32_t *)(HW_DCP_BASE + 0xa0))
+
+#define HW_DCP_PACKET3      (*(volatile uint32_t *)(HW_DCP_BASE + 0xb0))
+
+#define HW_DCP_PACKET4      (*(volatile uint32_t *)(HW_DCP_BASE + 0xc0))
+
+#define HW_DCP_PACKET5      (*(volatile uint32_t *)(HW_DCP_BASE + 0xd0))
+
+#define HW_DCP_PACKET6      (*(volatile uint32_t *)(HW_DCP_BASE + 0xe0))
+
+#define HW_DCP_CHxCMDPTR(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x100 + (x) * 0x40))
+
+#define HW_DCP_CHxSEMA(x)   (*(volatile uint32_t *)(HW_DCP_BASE + 0x110 + (x) * 0x40))
+#define HW_DCP_CHxSEMA__INCREMENT_BP    0
+#define HW_DCP_CHxSEMA__INCREMENT_BM    0xff
+#define HW_DCP_CHxSEMA__VALUE_BP        16
+#define HW_DCP_CHxSEMA__VALUE_BM        0xff0000
+
+#define HW_DCP_CHxSTAT(x)   (*(volatile uint32_t *)(HW_DCP_BASE + 0x120 + (x) * 0x40))
+
+#define HW_DCP_CHxOPTS(x)   (*(volatile uint32_t *)(HW_DCP_BASE + 0x130 + (x) * 0x40))
+#define HW_DCP_CHxOPTS__RECOVERY_TIMER_BP   0
+#define HW_DCP_CHxOPTS__RECOVERY_TIMER_BM   0xffff
+
+#define HW_DCP_CSCCTRL0     (*(volatile uint32_t *)(HW_DCP_BASE + 0x300))
+#define HW_DCP_CSCCTRL0__ENABLE     (1 << 0)
+#define HW_DCP_CSCCTRL0__YUV_FORMAT_BP  4
+#define HW_DCP_CSCCTRL0__YUV_FORMAT_BM  0xf0
+#define HW_DCP_CSCCTRL0__YUV_FORMAT__YUV420 0x0
+#define HW_DCP_CSCCTRL0__YUV_FORMAT__YUV422 0x2
+#define HW_DCP_CSCCTRL0__RGB_FORMAT_BP  8
+#define HW_DCP_CSCCTRL0__RGB_FORMAT_BM  0x300
+#define HW_DCP_CSCCTRL0__RGB_FORMAT__RGB16_565  0x0
+#define HW_DCP_CSCCTRL0__RGB_FORMAT__YCbCrI     0x1
+#define HW_DCP_CSCCTRL0__RGB_FORMAT__RGB24      0x2
+#define HW_DCP_CSCCTRL0__RGB_FORMAT__YUV422I    0x3
+#define HW_DCP_CSCCTRL0__DELTA      (1 << 10)
+#define HW_DCP_CSCCTRL0__SUBSAMPLE  (1 << 11)
+#define HW_DCP_CSCCTRL0__ROTATE     (1 << 12)
+#define HW_DCP_CSCCTRL0__SCALE      (1 << 13)
+#define HW_DCP_CSCCTRL0__UPSAMPLE   (1 << 14)
+#define HW_DCP_CSCCTRL0__CLIP       (1 << 15)
+
+#define HW_DCP_CSCSTAT      (*(volatile uint32_t *)(HW_DCP_BASE + 0x310))
+#define HW_DCP_CSCSTAT__COMPLETE    (1 << 0)
+#define HW_DCP_CSCSTAT__ERROR_SETUP (1 << 2)
+#define HW_DCP_CSCSTAT__ERROR_SRC   (1 << 4)
+#define HW_DCP_CSCSTAT__ERROR_DST   (1 << 5)
+#define HW_DCP_CSCSTAT__ERROR_PAGEFAULT (1 << 6)
+#define HW_DCP_CSCSTAT__ERROR_CODE_BP   16
+#define HW_DCP_CSCSTAT__ERROR_CODE_BM   (0xff << 16)
+
+#define HW_DCP_CSCOUTBUFPARAM   (*(volatile uint32_t *)(HW_DCP_BASE + 0x320))
+#define HW_DCP_CSCOUTBUFPARAM__LINE_SIZE_BP 0
+#define HW_DCP_CSCOUTBUFPARAM__LINE_SIZE_BM 0xfff
+#define HW_DCP_CSCOUTBUFPARAM__FIELD_SIZE_BP    12
+#define HW_DCP_CSCOUTBUFPARAM__FIELD_SIZE_BM    0xfff000
+
+#define HW_DCP_CSCINBUFPARAM    (*(volatile uint32_t *)(HW_DCP_BASE + 0x330))
+#define HW_DCP_CSCINBUFPARAM__LINE_SIZE_BP  0
+#define HW_DCP_CSCINBUFPARAM__LINE_SIZE_BM  0xfff
+
+#define HW_DCP_CSCRGB       (*(volatile uint32_t *)(HW_DCP_BASE + 0x340))
+
+#define HW_DCP_CSCLUMA      (*(volatile uint32_t *)(HW_DCP_BASE + 0x350))
+
+#define HW_DCP_CSCCHROMAU   (*(volatile uint32_t *)(HW_DCP_BASE + 0x360))
+
+#define HW_DCP_CSCCHROMAV   (*(volatile uint32_t *)(HW_DCP_BASE + 0x370))
+
+#define HW_DCP_CSCCOEFF0    (*(volatile uint32_t *)(HW_DCP_BASE + 0x380))
+#define HW_DCP_CSCCOEFF0__Y_OFFSET_BP   0
+#define HW_DCP_CSCCOEFF0__Y_OFFSET_BM   0xff
+#define HW_DCP_CSCCOEFF0__UV_OFFSET_BP  8
+#define HW_DCP_CSCCOEFF0__UV_OFFSET_BM  0xff00
+#define HW_DCP_CSCCOEFF0__C0_BP 16
+#define HW_DCP_CSCCOEFF0__C0_BM 0x3ff0000
+
+#define HW_DCP_CSCCOEFF1    (*(volatile uint32_t *)(HW_DCP_BASE + 0x390))
+#define HW_DCP_CSCCOEFF1__C4_BP 0
+#define HW_DCP_CSCCOEFF1__C4_BM 0x3ff
+#define HW_DCP_CSCCOEFF1__C1_BP 16
+#define HW_DCP_CSCCOEFF1__C1_BM 0x3ff0000
+
+#define HW_DCP_CSCCOEFF2    (*(volatile uint32_t *)(HW_DCP_BASE + 0x3a0))
+#define HW_DCP_CSCCOEFF2__C3_BP 0
+#define HW_DCP_CSCCOEFF2__C3_BM 0x3ff
+#define HW_DCP_CSCCOEFF2__C2_BP 16
+#define HW_DCP_CSCCOEFF2__C2_BM 0x3ff0000
+
+#define HW_DCP_CSCCLIP      (*(volatile uint32_t *)(HW_DCP_BASE + 0x3b0))
+#define HW_DCP_CSCCLIP__WIDTH_BP    0
+#define HW_DCP_CSCCLIP__WIDTH_BM    0xfff
+#define HW_DCP_CSCCLIP__HEIGHT_BP   12
+#define HW_DCP_CSCCLIP__HEIGHT_BM   0xfff000
+
+#define HW_DCP_CSCXSCALE    (*(volatile uint32_t *)(HW_DCP_BASE + 0x3c0))
+#define HW_DCP_CSCXSCALE__WIDTH_BP  0
+#define HW_DCP_CSCXSCALE__WIDTH_BM  0xfff
+#define HW_DCP_CSCXSCALE__FRAC_BP   12
+#define HW_DCP_CSCXSCALE__FRAC_BM   0xfff000
+#define HW_DCP_CSCXSCALE__INT_BP    24
+#define HW_DCP_CSCXSCALE__INT_BM    0x3000000
+
+#define HW_DCP_CSCYSCALE    (*(volatile uint32_t *)(HW_DCP_BASE + 0x3d0))
+#define HW_DCP_CSCYSCALE__WIDTH_BP  0
+#define HW_DCP_CSCYSCALE__WIDTH_BM  0xfff
+#define HW_DCP_CSCYSCALE__FRAC_BP   12
+#define HW_DCP_CSCYSCALE__FRAC_BM   0xfff000
+#define HW_DCP_CSCYSCALE__INT_BP    24
+#define HW_DCP_CSCYSCALE__INT_BM    0x3000000
+
+#define HW_DCP_PAGETABLE    (*(volatile uint32_t *)(HW_DCP_BASE + 0x420))
+#define HW_DCP_PAGETABLE__ENABLE    (1 << 0)
+#define HW_DCP_PAGETABLE__FLUSH     (1 << 1)
+#define HW_DCP_PAGETABLE__BASE_BP   2
+#define HW_DCP_PAGETABLE__BASE_BM   0xfffffffc
+
+struct imx233_dcp_packet_t
+{
+    uint32_t next;
+    uint32_t ctrl0;
+    uint32_t ctrl1;
+    uint32_t src;
+    uint32_t dst;
+    uint32_t size;
+    uint32_t payload;
+    uint32_t status;
+} __attribute__((packed));
+
+#define HW_DCP_CTRL0__INTERRUPT_ENABLE  (1 << 0)
+#define HW_DCP_CTRL0__DECR_SEMAPHORE    (1 << 1)
+#define HW_DCP_CTRL0__CHAIN             (1 << 2)
+#define HW_DCP_CTRL0__CHAIN_CONTINUOUS  (1 << 3)
+#define HW_DCP_CTRL0__ENABLE_MEMCOPY    (1 << 4)
+#define HW_DCP_CTRL0__ENABLE_CIPHER     (1 << 5)
+#define HW_DCP_CTRL0__ENABLE_HASH       (1 << 6)
+#define HW_DCP_CTRL0__ENABLE_BLIT       (1 << 7)
+#define HW_DCP_CTRL0__CIPHER_ENCRYPT    (1 << 8)
+#define HW_DCP_CTRL0__CIPHER_INIT       (1 << 9)
+#define HW_DCP_CTRL0__OTP_KEY           (1 << 10)
+#define HW_DCP_CTRL0__PAYLOAD_KEY       (1 << 11)
+#define HW_DCP_CTRL0__HASH_INIT         (1 << 12)
+#define HW_DCP_CTRL0__HASH_TERM         (1 << 13)
+#define HW_DCP_CTRL0__HASH_CHECK        (1 << 14)
+#define HW_DCP_CTRL0__HASH_OUTPUT       (1 << 15)
+#define HW_DCP_CTRL0__CONSTANT_FILL     (1 << 16)
+#define HW_DCP_CTRL0__TEST_SEMA_IRQ     (1 << 17)
+#define HW_DCP_CTRL0__KEY_BYTESWAP      (1 << 18)
+#define HW_DCP_CTRL0__KEY_WORDSWAP      (1 << 19)
+#define HW_DCP_CTRL0__INPUT_BYTESWAP    (1 << 20)
+#define HW_DCP_CTRL0__INPUT_WORDSWAP    (1 << 21)
+#define HW_DCP_CTRL0__OUTPUT_BYTESWAP   (1 << 22)
+#define HW_DCP_CTRL0__OUTPUT_WORDSWAP   (1 << 23)
+#define HW_DCP_CTRL0__TAG_BP            24
+#define HW_DCP_CTRL0__TAG_BM            (0xff << 24)
+
+#define HW_DCP_CTRL1__CIPHER_SELECT_BP  0
+#define HW_DCP_CTRL1__CIPHER_SELECT_BM  0xf
+#define HW_DCP_CTRL1__CIPHER_MODE_BP    4
+#define HW_DCP_CTRL1__CIPHER_MODE_BM    0xf0
+#define HW_DCP_CTRL1__KEY_SELECT_BP     8
+#define HW_DCP_CTRL1__KEY_SELECT_BM     0xff00
+#define HW_DCP_CTRL1__FRAMEBUFFER_LENGTH_BP 0
+#define HW_DCP_CTRL1__FRAMEBUFFER_LENGTH_BM 0xffff
+#define HW_DCP_CTRL1__HASH_SELECT_BP    16
+#define HW_DCP_CTRL1__HASH_SELECT_BM    0xf0000
+#define HW_DCP_CTRL1__CIPHER_CONFIG_BP  24
+#define HW_DCP_CTRL1__CIPHER_CONFIG_BM  (0xff << 24)
+
+#define HW_DCP_SIZE__BLIT_WIDTH_BP  0
+#define HW_DCP_SIZE__BLIT_WIDTH_BM  0xffff
+#define HW_DCP_SIZE__NUMBER_LINES_BP    16
+#define HW_DCP_SIZE__NUMBER_LINES_BM    0xffff0000
+
+#define HW_DCP_STATUS__COMPLETE     (1 << 0)
+#define HW_DCP_STATUS__HASH_MISMATCH    (1 << 1)
+#define HW_DCP_STATUS__ERROR_SETUP  (1 << 2)
+#define HW_DCP_STATUS__ERROR_PACKET (1 << 3)
+#define HW_DCP_STATUS__ERROR_SRC    (1 << 4)
+#define HW_DCP_STATUS__ERROR_DST    (1 << 5)
+#define HW_DCP_STATUS__ERROR_CODE_BP    16
+#define HW_DCP_STATUS__ERROR_CODE_BM    (0xff << 16)
+#define HW_DCP_STATUS__TAG_BP       24
+#define HW_DCP_STATUS__TAG_BM       (0xff << 24)
+
+struct imx233_dcp_channel_info_t
+{
+    bool irq;
+    bool irq_en;
+    bool enable;
+    bool high_priority;
+    bool ready;
+    int sema;
+    uint32_t cmdptr;
+};
+
+struct imx233_dcp_csc_info_t
+{
+    bool irq;
+    bool irq_en;
+    bool enable;
+    int priority;
+};
+
+struct imx233_dcp_info_t
+{
+    /* capabilities */
+    bool has_crypto;
+    bool has_csc;
+    int num_keys;
+    int num_channels;
+    unsigned ciphers;
+    unsigned hashs;
+    /* global state */
+    bool context_switching;
+    bool context_caching;
+    bool gather_writes;
+    bool otp_key_ready;
+    bool ch0_merged;
+    /* channel state */
+    struct imx233_dcp_channel_info_t channel[HW_DCP_NUM_CHANNELS];
+    /* csc state */
+    struct imx233_dcp_csc_info_t csc;
+};
+
+#define DCP_INFO_CAPABILITIES   (1 << 0)
+#define DCP_INFO_GLOBAL_STATE   (1 << 1)
+#define DCP_INFO_CHANNELS       (1 << 2)
+#define DCP_INFO_CSC            (1 << 3)
+#define DCP_INFO_ALL            0xf
+
+enum imx233_dcp_error_t
+{
+    DCP_SUCCESS = 0,
+    DCP_TIMEOUT = -1,
+    DCP_ERROR_SETUP = -2,
+    DCP_ERROR_PACKET = -3,
+    DCP_ERROR_SRC = -4,
+    DCP_ERROR_DST = -5,
+    DCP_ERROR_CHAIN_IS_0  = -6,
+    DCP_ERROR_NO_CHAIN = -7,
+    DCP_ERROR_CONTEXT = -8,
+    DCP_ERROR_PAYLOAD = -9,
+    DCP_ERROR_MODE = -10,
+    DCP_ERROR = -11
+};
+
+void imx233_dcp_init(void);
+// return OBJ_WAIT_TIMEOUT on failure
+int imx233_dcp_acquire_channel(int timeout);
+void imx233_dcp_release_channel(int chan);
+// doesn't check that channel is in use!
+void imx233_dcp_reserve_channel(int channel);
+
+enum imx233_dcp_error_t imx233_dcp_memcpy_ex(int channel, void *src, void *dst, size_t len);
+enum imx233_dcp_error_t imx233_dcp_memcpy(void *src, void *dst, size_t len, int tmo);
+
+struct imx233_dcp_info_t imx233_dcp_get_info(unsigned flags);
+
+#endif // __DMA_IMX233_H__
diff --git a/firmware/target/arm/imx233/debug-imx233.c b/firmware/target/arm/imx233/debug-imx233.c
index 51d306b7b1..7db7ee97d7 100644
--- a/firmware/target/arm/imx233/debug-imx233.c
+++ b/firmware/target/arm/imx233/debug-imx233.c
@@ -30,6 +30,7 @@
 #include "clkctrl-imx233.h"
 #include "powermgmt-imx233.h"
 #include "rtc-imx233.h"
+#include "dcp-imx233.h"
 #include "string.h"
 
 #define DEBUG_CANCEL  BUTTON_BACK
@@ -347,11 +348,57 @@ bool dbg_hw_info_rtc(void)
     }
 }
 
+bool dbg_hw_info_dcp(void)
+{
+    lcd_setfont(FONT_SYSFIXED);
+    
+    while(1)
+    {
+        int button = get_action(CONTEXT_STD, HZ / 10);
+        switch(button)
+        {
+            case ACTION_STD_NEXT:
+            case ACTION_STD_PREV:
+            case ACTION_STD_OK:
+            case ACTION_STD_MENU:
+                lcd_setfont(FONT_UI);
+                return true;
+            case ACTION_STD_CANCEL:
+                lcd_setfont(FONT_UI);
+                return false;
+        }
+        
+        lcd_clear_display();
+        struct imx233_dcp_info_t info = imx233_dcp_get_info(DCP_INFO_ALL);
+        
+        lcd_putsf(0, 0, "crypto: %d  csc: %d", info.has_crypto, info.has_csc);
+        lcd_putsf(0, 1, "keys: %d  channels: %d", info.num_keys, info.num_channels);
+        lcd_putsf(0, 2, "ciphers: 0x%lx  hash: 0x%lx", info.ciphers, info.hashs);
+        lcd_putsf(0, 3, "gather wr: %d  otp rdy: %d ch0merged: %d",
+            info.gather_writes, info.otp_key_ready, info.ch0_merged);
+        lcd_putsf(0, 4, "ctx switching: %d caching: %d", info.context_switching,
+            info.context_caching);
+        lcd_putsf(0, 5, "ch  irq ien en rdy pri sem cmdptr");
+        int nr = HW_DCP_NUM_CHANNELS;
+        for(int i = 0; i < nr; i++)
+        {
+            lcd_putsf(0, 6 + i, "%d    %d   %d   %d  %d   %d   %d  0x%08lx",
+                i, info.channel[i].irq, info.channel[i].irq_en, info.channel[i].enable,
+                info.channel[i].ready, info.channel[i].high_priority,
+                info.channel[i].sema, info.channel[i].cmdptr);
+        }
+        lcd_putsf(0, 6 + nr, "csc  %d   %d   %d      %d",
+                  info.csc.irq, info.csc.irq_en, info.csc.enable, info.csc.priority);
+        lcd_update();
+        yield();
+    }
+}
+
 bool dbg_hw_info(void)
 {
     return dbg_hw_info_clkctrl() && dbg_hw_info_dma() && dbg_hw_info_adc() &&
         dbg_hw_info_power() && dbg_hw_info_powermgmt() && dbg_hw_info_rtc() &&
-        dbg_hw_target_info();
+        dbg_hw_info_dcp() && dbg_hw_target_info();
 }
 
 bool dbg_ports(void)
diff --git a/firmware/target/arm/imx233/kernel-imx233.c b/firmware/target/arm/imx233/kernel-imx233.c
index edb9b8366c..b59d3ed63f 100644
--- a/firmware/target/arm/imx233/kernel-imx233.c
+++ b/firmware/target/arm/imx233/kernel-imx233.c
@@ -21,6 +21,7 @@
 #include "kernel.h"
 #include "timrot-imx233.h"
 #include "clkctrl-imx233.h"
+#include "kernel-imx233.h"
 
 static void tick_timer(void)
 {
@@ -35,3 +36,45 @@ void tick_start(unsigned int interval_in_ms)
         HW_TIMROT_TIMCTRL__SELECT_1KHZ_XTAL, HW_TIMROT_TIMCTRL__PRESCALE_1,
         false, &tick_timer);
 }
+
+
+void arbiter_init(struct channel_arbiter_t *a, unsigned count)
+{
+    mutex_init(&a->mutex);
+    semaphore_init(&a->sema, count, count);
+    a->free_bm = (1 << count) - 1;
+    a->count = count;
+}
+
+// doesn't check in use !
+void arbiter_reserve(struct channel_arbiter_t *a, unsigned channel)
+{
+    // assume semaphore has a free slot immediately
+    if(semaphore_wait(&a->sema, TIMEOUT_NOBLOCK) != OBJ_WAIT_SUCCEEDED)
+        panicf("arbiter_reserve failed on semaphore_wait !");
+    mutex_lock(&a->mutex);
+    a->free_bm &= ~(1 << channel);
+    mutex_unlock(&a->mutex);
+}
+
+int arbiter_acquire(struct channel_arbiter_t *a, int timeout)
+{
+    int w = semaphore_wait(&a->sema, timeout);
+    if(w == OBJ_WAIT_TIMEDOUT)
+        return w;
+    mutex_lock(&a->mutex);
+    int chan = find_first_set_bit(a->free_bm);
+    if(chan >= a->count)
+        panicf("arbiter_acquire cannot find a free channel !");
+    a->free_bm &= ~(1 << chan);
+    mutex_unlock(&a->mutex);
+    return chan;
+}
+
+void arbiter_release(struct channel_arbiter_t *a, int channel)
+{
+    mutex_lock(&a->mutex);
+    a->free_bm |= 1 << channel;
+    mutex_unlock(&a->mutex);
+    semaphore_release(&a->sema);
+}
diff --git a/firmware/target/arm/imx233/lradc-imx233.c b/firmware/target/arm/imx233/lradc-imx233.c
index 8b065bffea..432d1c1035 100644
--- a/firmware/target/arm/imx233/lradc-imx233.c
+++ b/firmware/target/arm/imx233/lradc-imx233.c
@@ -21,60 +21,12 @@
 #include "system.h"
 #include "system-target.h"
 #include "lradc-imx233.h"
-
-struct channel_arbiter_t
-{
-    struct semaphore sema;
-    struct mutex mutex;
-    unsigned free_bm;
-    int count;
-};
-
-static void arbiter_init(struct channel_arbiter_t *a, unsigned count)
-{
-    mutex_init(&a->mutex);
-    semaphore_init(&a->sema, count, count);
-    a->free_bm = (1 << count) - 1;
-    a->count = count;
-}
-
-// doesn't check in use !
-static void arbiter_reserve(struct channel_arbiter_t *a, unsigned channel)
-{
-    // assume semaphore has a free slot immediately
-    if(semaphore_wait(&a->sema, TIMEOUT_NOBLOCK) != OBJ_WAIT_SUCCEEDED)
-        panicf("arbiter_reserve failed on semaphore_wait !");
-    mutex_lock(&a->mutex);
-    a->free_bm &= ~(1 << channel);
-    mutex_unlock(&a->mutex);
-}
-
-static int arbiter_acquire(struct channel_arbiter_t *a, int timeout)
-{
-    int w = semaphore_wait(&a->sema, timeout);
-    if(w == OBJ_WAIT_TIMEDOUT)
-        return w;
-    mutex_lock(&a->mutex);
-    int chan = find_first_set_bit(a->free_bm);
-    if(chan >= a->count)
-        panicf("arbiter_acquire cannot find a free channel !");
-    a->free_bm &= ~(1 << chan);
-    mutex_unlock(&a->mutex);
-    return chan;
-}
-
-static void arbiter_release(struct channel_arbiter_t *a, int channel)
-{
-    mutex_lock(&a->mutex);
-    a->free_bm |= 1 << channel;
-    mutex_unlock(&a->mutex);
-    semaphore_release(&a->sema);
-}
+#include "kernel-imx233.h"
 
 /* channels */
-struct channel_arbiter_t channel_arbiter;
+static struct channel_arbiter_t channel_arbiter;
 /* delay channels */
-struct channel_arbiter_t delay_arbiter;
+static struct channel_arbiter_t delay_arbiter;
 
 void imx233_lradc_setup_channel(int channel, bool div2, bool acc, int nr_samples, int src)
 {
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index 19d0a7fac9..c9d490302e 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -30,6 +30,7 @@
 #include "dma-imx233.h"
 #include "ssp-imx233.h"
 #include "i2c-imx233.h"
+#include "dcp-imx233.h"
 #include "lcd.h"
 #include "backlight-target.h"
 #include "button.h"
@@ -68,6 +69,7 @@ default_interrupt(INT_LRADC_CH6);
 default_interrupt(INT_LRADC_CH7);
 default_interrupt(INT_DAC_DMA);
 default_interrupt(INT_DAC_ERROR);
+default_interrupt(INT_DCP);
 
 typedef void (*isr_t)(void);
 
@@ -100,6 +102,7 @@ static isr_t isr_table[INT_SRC_NR_SOURCES] =
     [INT_SRC_LRADC_CHx(7)] = INT_LRADC_CH7,
     [INT_SRC_DAC_DMA] = INT_DAC_DMA,
     [INT_SRC_DAC_ERROR] = INT_DAC_ERROR,
+    [INT_SRC_DCP] = INT_DCP,
 };
 
 static void UIRQ(void)
@@ -205,6 +208,7 @@ void system_init(void)
     imx233_timrot_init();
     imx233_dma_init();
     imx233_ssp_init();
+    imx233_dcp_init();
 }
 
 bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h
index 9ad9d1d808..6a5cecaf87 100644
--- a/firmware/target/arm/imx233/system-target.h
+++ b/firmware/target/arm/imx233/system-target.h
@@ -34,6 +34,8 @@
 #define HW_DIGCTL_CTRL          (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0))
 #define HW_DIGCTL_CTRL__USB_CLKGATE (1 << 2)
 
+#define HW_DIGCTL_HCLKCOUNT     (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x20))
+
 #define HW_DIGCTL_MICROSECONDS  (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
 
 /* USB Phy */
@@ -80,6 +82,7 @@
 #define INT_SRC_LRADC_CHx(x)    (37 + (x))
 #define INT_SRC_LCDIF_DMA   45
 #define INT_SRC_LCDIF_ERROR 46
+#define INT_SRC_DCP         54
 #define INT_SRC_NR_SOURCES  66
 
 /**