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author | Solomon Peachy <pizza@shaftnet.org> | 2020-09-05 20:15:23 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2020-09-06 00:27:07 +0000 |
commit | 2dadb8c7d6bc4383565e0f35ef0f0a5b9520044d (patch) | |
tree | 7719b0a6684a8bc60dd7123b336f83b1295a47bd | |
parent | d015165bc546e80b1c033c23c68a0ba307b7a39f (diff) | |
download | rockbox-2dadb8c7d6bc4383565e0f35ef0f0a5b9520044d.tar.gz rockbox-2dadb8c7d6bc4383565e0f35ef0f0a5b9520044d.zip |
jz4760: Use a #define for the timer id, not a raw number
Change-Id: Ic31267a2ae82beede72100c1cc5ddf7211aa0abe
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/timer-jz4760.c | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/timer-jz4760.c b/firmware/target/mips/ingenic_jz47xx/timer-jz4760.c index b90dc8fcf0..34517965d5 100644 --- a/firmware/target/mips/ingenic_jz47xx/timer-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/timer-jz4760.c | |||
@@ -18,16 +18,18 @@ | |||
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "cpu.h" | 23 | #include "cpu.h" |
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include "timer.h" | 25 | #include "timer.h" |
26 | 26 | ||
27 | #define TIMER_ID 5 | ||
28 | |||
27 | /* Interrupt handler */ | 29 | /* Interrupt handler */ |
28 | void TCU1(void) | 30 | void TCU1(void) |
29 | { | 31 | { |
30 | __tcu_clear_full_match_flag(5); | 32 | __tcu_clear_full_match_flag(TIMER_ID); |
31 | 33 | ||
32 | if (pfn_timer != NULL) | 34 | if (pfn_timer != NULL) |
33 | pfn_timer(); | 35 | pfn_timer(); |
@@ -56,24 +58,24 @@ bool timer_set(long cycles, bool start) | |||
56 | 58 | ||
57 | old_irq = disable_irq_save(); | 59 | old_irq = disable_irq_save(); |
58 | 60 | ||
59 | __tcu_stop_counter(5); | 61 | __tcu_stop_counter(TIMER_ID); |
60 | if(start) | 62 | if(start) |
61 | { | 63 | { |
62 | __tcu_disable_pwm_output(5); | 64 | __tcu_disable_pwm_output(TIMER_ID); |
63 | 65 | ||
64 | __tcu_mask_half_match_irq(5); | 66 | __tcu_mask_half_match_irq(TIMER_ID); |
65 | __tcu_unmask_full_match_irq(5); | 67 | __tcu_unmask_full_match_irq(TIMER_ID); |
66 | 68 | ||
67 | /* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */ | 69 | /* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */ |
68 | __tcu_select_extalclk(5); | 70 | __tcu_select_extalclk(TIMER_ID); |
69 | } | 71 | } |
70 | 72 | ||
71 | REG_TCU_TCSR(5) = (REG_TCU_TCSR(5) & ~TCSR_PRESCALE_MASK) | (prescaler_bit << TCSR_PRESCALE_LSB); | 73 | REG_TCU_TCSR(TIMER_ID) = (REG_TCU_TCSR(TIMER_ID) & ~TCSR_PRESCALE_MASK) | (prescaler_bit << TCSR_PRESCALE_LSB); |
72 | REG_TCU_TCNT(5) = 0; | 74 | REG_TCU_TCNT(TIMER_ID) = 0; |
73 | REG_TCU_TDHR(5) = 0; | 75 | REG_TCU_TDHR(TIMER_ID) = 0; |
74 | REG_TCU_TDFR(5) = divider; | 76 | REG_TCU_TDFR(TIMER_ID) = divider; |
75 | 77 | ||
76 | __tcu_clear_full_match_flag(5); | 78 | __tcu_clear_full_match_flag(TIMER_ID); |
77 | 79 | ||
78 | if(start) | 80 | if(start) |
79 | { | 81 | { |
@@ -81,14 +83,14 @@ bool timer_set(long cycles, bool start) | |||
81 | } | 83 | } |
82 | 84 | ||
83 | restore_irq(old_irq); | 85 | restore_irq(old_irq); |
84 | __tcu_start_counter(5); | 86 | __tcu_start_counter(TIMER_ID); |
85 | 87 | ||
86 | return true; | 88 | return true; |
87 | } | 89 | } |
88 | 90 | ||
89 | bool timer_start(void) | 91 | bool timer_start(void) |
90 | { | 92 | { |
91 | __tcu_start_counter(5); | 93 | __tcu_start_counter(TIMER_ID); |
92 | 94 | ||
93 | return true; | 95 | return true; |
94 | } | 96 | } |
@@ -96,6 +98,6 @@ bool timer_start(void) | |||
96 | void timer_stop(void) | 98 | void timer_stop(void) |
97 | { | 99 | { |
98 | unsigned int old_irq = disable_irq_save(); | 100 | unsigned int old_irq = disable_irq_save(); |
99 | __tcu_stop_counter(5); | 101 | __tcu_stop_counter(TIMER_ID); |
100 | restore_irq(old_irq); | 102 | restore_irq(old_irq); |
101 | } | 103 | } |