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author | Amaury Pouly <pamaury@rockbox.org> | 2010-06-19 20:39:57 +0000 |
---|---|---|
committer | Amaury Pouly <pamaury@rockbox.org> | 2010-06-19 20:39:57 +0000 |
commit | 19b3348656c305f8550b99c3368f9404ca913f94 (patch) | |
tree | fc85bc3ff82510d4fff86a88fa25216cef834596 | |
parent | f9242c06d01b6fe4532cb5511b1470046df5650b (diff) | |
download | rockbox-19b3348656c305f8550b99c3368f9404ca913f94.tar.gz rockbox-19b3348656c305f8550b99c3368f9404ca913f94.zip |
as3525v2-usb: major code renaming
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26971 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.c | 358 | ||||
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.h | 564 |
2 files changed, 488 insertions, 434 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.c b/firmware/target/arm/as3525/usb-drv-as3525v2.c index 0149cac653..951e0b0687 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.c +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.c | |||
@@ -36,16 +36,16 @@ | |||
36 | #include "usb-drv-as3525v2.h" | 36 | #include "usb-drv-as3525v2.h" |
37 | #include "usb_core.h" | 37 | #include "usb_core.h" |
38 | 38 | ||
39 | static int __in_ep_list[USB_NUM_IN_EP] = {USB_IN_EP_LIST}; | 39 | static int __in_ep_list[NUM_IN_EP] = {IN_EP_LIST}; |
40 | static int __out_ep_list[USB_NUM_OUT_EP] = {USB_OUT_EP_LIST}; | 40 | static int __out_ep_list[NUM_OUT_EP] = {OUT_EP_LIST}; |
41 | 41 | ||
42 | /* iterate through each in/out ep except EP0 | 42 | /* iterate through each in/out ep except EP0 |
43 | * 'counter' is the counter, 'ep' is the actual value */ | 43 | * 'counter' is the counter, 'ep' is the actual value */ |
44 | #define FOR_EACH_IN_EP(counter, ep) \ | 44 | #define FOR_EACH_IN_EP(counter, ep) \ |
45 | for(counter = 0, ep = __in_ep_list[0]; counter < USB_NUM_IN_EP; counter++, ep = __in_ep_list[counter]) | 45 | for(counter = 0, ep = __in_ep_list[0]; counter < NUM_IN_EP; counter++, ep = __in_ep_list[counter]) |
46 | 46 | ||
47 | #define FOR_EACH_OUT_EP(counter, ep) \ | 47 | #define FOR_EACH_OUT_EP(counter, ep) \ |
48 | for(counter = 0, ep = __out_ep_list[0]; counter < USB_NUM_OUT_EP; counter++, ep = __out_ep_list[counter]) | 48 | for(counter = 0, ep = __out_ep_list[0]; counter < NUM_OUT_EP; counter++, ep = __out_ep_list[counter]) |
49 | 49 | ||
50 | struct usb_endpoint | 50 | struct usb_endpoint |
51 | { | 51 | { |
@@ -91,29 +91,29 @@ static void as3525v2_connect(void) | |||
91 | CGU_USB |= 0x20; | 91 | CGU_USB |= 0x20; |
92 | usb_delay(); | 92 | usb_delay(); |
93 | /* 3) clear "stop pclk" */ | 93 | /* 3) clear "stop pclk" */ |
94 | USB_PCGCCTL &= ~0x1; | 94 | PCGCCTL &= ~0x1; |
95 | usb_delay(); | 95 | usb_delay(); |
96 | /* 4) clear "power clamp" */ | 96 | /* 4) clear "power clamp" */ |
97 | USB_PCGCCTL &= ~0x4; | 97 | PCGCCTL &= ~0x4; |
98 | usb_delay(); | 98 | usb_delay(); |
99 | /* 5) clear "reset power down module" */ | 99 | /* 5) clear "reset power down module" */ |
100 | USB_PCGCCTL &= ~0x8; | 100 | PCGCCTL &= ~0x8; |
101 | usb_delay(); | 101 | usb_delay(); |
102 | /* 6) set "power on program done" */ | 102 | /* 6) set "power on program done" */ |
103 | USB_DCTL |= USB_DCTL_pwronprgdone; | 103 | DCTL |= DCTL_pwronprgdone; |
104 | usb_delay(); | 104 | usb_delay(); |
105 | /* 7) core soft reset */ | 105 | /* 7) core soft reset */ |
106 | USB_GRSTCTL |= USB_GRSTCTL_csftrst; | 106 | GRSTCTL |= GRSTCTL_csftrst; |
107 | usb_delay(); | 107 | usb_delay(); |
108 | /* 8) hclk soft reset */ | 108 | /* 8) hclk soft reset */ |
109 | USB_GRSTCTL |= USB_GRSTCTL_hsftrst; | 109 | GRSTCTL |= GRSTCTL_hsftrst; |
110 | usb_delay(); | 110 | usb_delay(); |
111 | /* 9) flush and reset everything */ | 111 | /* 9) flush and reset everything */ |
112 | USB_GRSTCTL |= 0x3f; | 112 | GRSTCTL |= 0x3f; |
113 | usb_delay(); | 113 | usb_delay(); |
114 | /* 10) force device mode*/ | 114 | /* 10) force device mode*/ |
115 | USB_GUSBCFG &= ~USB_GUSBCFG_force_host_mode; | 115 | GUSBCFG &= ~GUSBCFG_force_host_mode; |
116 | USB_GUSBCFG |= USB_GUSBCFG_force_device_mode; | 116 | GUSBCFG |= GUSBCFG_force_device_mode; |
117 | usb_delay(); | 117 | usb_delay(); |
118 | /* 11) Do something that is probably CCU related but undocumented*/ | 118 | /* 11) Do something that is probably CCU related but undocumented*/ |
119 | CCU_USB_THINGY &= ~0x1000; | 119 | CCU_USB_THINGY &= ~0x1000; |
@@ -121,48 +121,48 @@ static void as3525v2_connect(void) | |||
121 | CCU_USB_THINGY &= ~0x300000; | 121 | CCU_USB_THINGY &= ~0x300000; |
122 | usb_delay(); | 122 | usb_delay(); |
123 | /* 12) reset usb core parameters (dev addr, speed, ...) */ | 123 | /* 12) reset usb core parameters (dev addr, speed, ...) */ |
124 | USB_DCFG = 0; | 124 | DCFG = 0; |
125 | usb_delay(); | 125 | usb_delay(); |
126 | } | 126 | } |
127 | 127 | ||
128 | static void usb_enable_device_interrupts(void) | 128 | static void enable_device_interrupts(void) |
129 | { | 129 | { |
130 | /* Clear any pending interrupt */ | 130 | /* Clear any pending interrupt */ |
131 | USB_GINTSTS = 0xffffffff; | 131 | GINTSTS = 0xffffffff; |
132 | /* Clear any pending otg interrupt */ | 132 | /* Clear any pending otg interrupt */ |
133 | USB_GOTGINT = 0xffffffff; | 133 | GOTGINT = 0xffffffff; |
134 | /* Enable interrupts */ | 134 | /* Enable interrupts */ |
135 | USB_GINTMSK = USB_GINTMSK_usbreset | 135 | GINTMSK = GINTMSK_usbreset |
136 | | USB_GINTMSK_enumdone | 136 | | GINTMSK_enumdone |
137 | | USB_GINTMSK_inepintr | 137 | | GINTMSK_inepintr |
138 | | USB_GINTMSK_outepintr | 138 | | GINTMSK_outepintr |
139 | | USB_GINTMSK_otgintr | 139 | | GINTMSK_otgintr |
140 | | USB_GINTMSK_disconnect; | 140 | | GINTMSK_disconnect; |
141 | } | 141 | } |
142 | 142 | ||
143 | static void usb_flush_tx_fifos(int nums) | 143 | static void flush_tx_fifos(int nums) |
144 | { | 144 | { |
145 | unsigned int i = 0; | 145 | unsigned int i = 0; |
146 | 146 | ||
147 | USB_GRSTCTL = (USB_GRSTCTL & (~USB_GRSTCTL_txfnum_bits)) | 147 | GRSTCTL = (GRSTCTL & (~GRSTCTL_txfnum_bits)) |
148 | | (nums << USB_GRSTCTL_txfnum_bit_pos) | 148 | | (nums << GRSTCTL_txfnum_bit_pos) |
149 | | USB_GRSTCTL_txfflsh_flush; | 149 | | GRSTCTL_txfflsh_flush; |
150 | while(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush && i < 0x300) | 150 | while(GRSTCTL & GRSTCTL_txfflsh_flush && i < 0x300) |
151 | i++; | 151 | i++; |
152 | if(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush) | 152 | if(GRSTCTL & GRSTCTL_txfflsh_flush) |
153 | panicf("usb: hang of flush tx fifos (%x)", nums); | 153 | panicf("usb: hang of flush tx fifos (%x)", nums); |
154 | /* wait 3 phy clocks */ | 154 | /* wait 3 phy clocks */ |
155 | udelay(1); | 155 | udelay(1); |
156 | } | 156 | } |
157 | 157 | ||
158 | static void usb_flush_rx_fifo(void) | 158 | static void flush_rx_fifo(void) |
159 | { | 159 | { |
160 | unsigned int i = 0; | 160 | unsigned int i = 0; |
161 | 161 | ||
162 | USB_GRSTCTL = USB_GRSTCTL_rxfflsh_flush; | 162 | GRSTCTL = GRSTCTL_rxfflsh_flush; |
163 | while(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush && i < 0x300) | 163 | while(GRSTCTL & GRSTCTL_rxfflsh_flush && i < 0x300) |
164 | i++; | 164 | i++; |
165 | if(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush) | 165 | if(GRSTCTL & GRSTCTL_rxfflsh_flush) |
166 | panicf("usb: hang of flush rx fifo"); | 166 | panicf("usb: hang of flush rx fifo"); |
167 | /* wait 3 phy clocks */ | 167 | /* wait 3 phy clocks */ |
168 | udelay(1); | 168 | udelay(1); |
@@ -172,15 +172,15 @@ static void core_reset(void) | |||
172 | { | 172 | { |
173 | unsigned int i = 0; | 173 | unsigned int i = 0; |
174 | /* Wait for AHB master IDLE state. */ | 174 | /* Wait for AHB master IDLE state. */ |
175 | while((USB_GRSTCTL & USB_GRSTCTL_ahbidle) == 0) | 175 | while((GRSTCTL & GRSTCTL_ahbidle) == 0) |
176 | udelay(10); | 176 | udelay(10); |
177 | /* Core Soft Reset */ | 177 | /* Core Soft Reset */ |
178 | USB_GRSTCTL |= USB_GRSTCTL_csftrst; | 178 | GRSTCTL |= GRSTCTL_csftrst; |
179 | /* Waits for the hardware to clear reset bit */ | 179 | /* Waits for the hardware to clear reset bit */ |
180 | while(USB_GRSTCTL & USB_GRSTCTL_csftrst && i < 0x300) | 180 | while(GRSTCTL & GRSTCTL_csftrst && i < 0x300) |
181 | i++; | 181 | i++; |
182 | 182 | ||
183 | if(USB_GRSTCTL & USB_GRSTCTL_csftrst) | 183 | if(GRSTCTL & GRSTCTL_csftrst) |
184 | panicf("oops, usb core soft reset hang :("); | 184 | panicf("oops, usb core soft reset hang :("); |
185 | 185 | ||
186 | /* Wait for 3 PHY Clocks */ | 186 | /* Wait for 3 PHY Clocks */ |
@@ -192,16 +192,16 @@ static void reset_endpoints(void) | |||
192 | int i, ep; | 192 | int i, ep; |
193 | /* disable all endpoints except EP0 */ | 193 | /* disable all endpoints except EP0 */ |
194 | FOR_EACH_IN_EP(i, ep) | 194 | FOR_EACH_IN_EP(i, ep) |
195 | if(USB_DIEPCTL(ep) & USB_DEPCTL_epena) | 195 | if(DIEPCTL(ep) & DEPCTL_epena) |
196 | USB_DIEPCTL(ep) = USB_DEPCTL_epdis | USB_DEPCTL_snak; | 196 | DIEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak; |
197 | else | 197 | else |
198 | USB_DIEPCTL(ep) = 0; | 198 | DIEPCTL(ep) = 0; |
199 | 199 | ||
200 | FOR_EACH_OUT_EP(i, ep) | 200 | FOR_EACH_OUT_EP(i, ep) |
201 | if(USB_DOEPCTL(ep) & USB_DEPCTL_epena) | 201 | if(DOEPCTL(ep) & DEPCTL_epena) |
202 | USB_DOEPCTL(ep) = USB_DEPCTL_epdis | USB_DEPCTL_snak; | 202 | DOEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak; |
203 | else | 203 | else |
204 | USB_DOEPCTL(ep) = 0; | 204 | DOEPCTL(ep) = 0; |
205 | /* Setup EP0 OUT with the following parameters: | 205 | /* Setup EP0 OUT with the following parameters: |
206 | * packet count = 1 | 206 | * packet count = 1 |
207 | * setup packet count = 1 | 207 | * setup packet count = 1 |
@@ -209,88 +209,90 @@ static void reset_endpoints(void) | |||
209 | * Setup EP0 IN/OUT with 64 byte maximum packet size and activate both. Enable transfer on EP0 OUT | 209 | * Setup EP0 IN/OUT with 64 byte maximum packet size and activate both. Enable transfer on EP0 OUT |
210 | */ | 210 | */ |
211 | 211 | ||
212 | USB_DOEPTSIZ(0) = (1 << USB_DEPTSIZ0_supcnt_bit_pos) | 212 | DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bit_pos) |
213 | | (1 << USB_DEPTSIZ0_pkcnt_bit_pos) | 213 | | (1 << DEPTSIZ0_pkcnt_bit_pos) |
214 | | 8; | 214 | | 8; |
215 | 215 | ||
216 | /* setup DMA */ | 216 | /* setup DMA */ |
217 | clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ | 217 | clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ |
218 | USB_DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */ | 218 | DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */ |
219 | 219 | ||
220 | /* Enable endpoint, clear nak */ | 220 | /* Enable endpoint, clear nak */ |
221 | USB_DOEPCTL(0) = USB_DEPCTL_epena | USB_DEPCTL_cnak | USB_DEPCTL_usbactep | 221 | DOEPCTL(0) = DEPCTL_epena | DEPCTL_cnak | DEPCTL_usbactep |
222 | | (USB_DEPCTL_MPS_8 << USB_DEPCTL_mps_bit_pos); | 222 | | (DEPCTL_MPS_8 << DEPCTL_mps_bit_pos); |
223 | 223 | ||
224 | /* 64 bytes packet size, active endpoint */ | 224 | /* 64 bytes packet size, active endpoint */ |
225 | USB_DIEPCTL(0) = (USB_DEPCTL_MPS_8 << USB_DEPCTL_mps_bit_pos) | 225 | DIEPCTL(0) = (DEPCTL_MPS_8 << DEPCTL_mps_bit_pos) |
226 | | USB_DEPCTL_usbactep; | 226 | | DEPCTL_usbactep; |
227 | 227 | ||
228 | USB_DCTL = USB_DCTL_cgnpinnak | USB_DCTL_cgoutnak; | 228 | DCTL = DCTL_cgnpinnak | DCTL_cgoutnak; |
229 | } | 229 | } |
230 | 230 | ||
231 | static void core_dev_init(void) | 231 | static void core_dev_init(void) |
232 | { | 232 | { |
233 | unsigned int usb_num_in_ep = 0; | 233 | unsigned int num_in_ep = 0; |
234 | unsigned int usb_num_out_ep = 0; | 234 | unsigned int num_out_ep = 0; |
235 | unsigned int i; | 235 | unsigned int i; |
236 | /* Restart the phy clock */ | 236 | /* Restart the phy clock */ |
237 | USB_PCGCCTL = 0; | 237 | PCGCCTL = 0; |
238 | /* Set phy speed : high speed */ | 238 | /* Set phy speed : high speed */ |
239 | USB_DCFG = (USB_DCFG & ~USB_DCFG_devspd_bits) | USB_DCFG_devspd_hs_phy_hs; | 239 | DCFG = (DCFG & ~DCFG_devspd_bits) | DCFG_devspd_hs_phy_hs; |
240 | 240 | ||
241 | /* Check hardware capabilities */ | 241 | /* Check hardware capabilities */ |
242 | if(USB_GHWCFG2_ARCH != USB_INT_DMA_ARCH) | 242 | if(extract(GHWCFG2, ARCH) != INT_DMA_ARCH) |
243 | panicf("usb: wrong architecture (%ld)", USB_GHWCFG2_ARCH); | 243 | panicf("usb: wrong architecture (%ld)", extract(GHWCFG2, ARCH)); |
244 | if(USB_GHWCFG2_HS_PHY_TYPE != USB_PHY_TYPE_UTMI) | 244 | if(extract(GHWCFG2, HS_PHY_TYPE) != PHY_TYPE_UTMI) |
245 | panicf("usb: wrong HS phy type (%ld)", USB_GHWCFG2_HS_PHY_TYPE); | 245 | panicf("usb: wrong HS phy type (%ld)", extract(GHWCFG2, HS_PHY_TYPE)); |
246 | if(USB_GHWCFG2_FS_PHY_TYPE != USB_PHY_TYPE_UNSUPPORTED) | 246 | if(extract(GHWCFG2, FS_PHY_TYPE) != PHY_TYPE_UNSUPPORTED) |
247 | panicf("usb: wrong FS phy type (%ld)", USB_GHWCFG2_FS_PHY_TYPE); | 247 | panicf("usb: wrong FS phy type (%ld)", extract(GHWCFG2, FS_PHY_TYPE)); |
248 | if(USB_GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2) | 248 | if(GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2) |
249 | panicf("usb: wrong utmi data width (%ld)", USB_GHWCFG4_UTMI_PHY_DATA_WIDTH); | 249 | panicf("usb: wrong utmi data width (%ld)", GHWCFG4_UTMI_PHY_DATA_WIDTH); |
250 | if(USB_GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */ | 250 | if(GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */ |
251 | panicf("usb: no multiple tx fifo"); | 251 | panicf("usb: no multiple tx fifo"); |
252 | 252 | ||
253 | #ifdef USB_USE_CUSTOM_FIFO_LAYOUT | 253 | #ifdef USE_CUSTOM_FIFO_LAYOUT |
254 | if(USB_GHWCFG2_DYN_FIFO != 1) | 254 | if(!(GHWCFG2 & GHWCFG2_DYN_FIFO)) |
255 | panicf("usb: no dynamic fifo"); | 255 | panicf("usb: no dynamic fifo"); |
256 | if(USB_GRXFSIZ != USB_DATA_FIFO_DEPTH) | 256 | if(GRXFSIZ != DATA_FIFO_DEPTH) |
257 | panicf("usb: wrong data fifo size"); | 257 | panicf("usb: wrong data fifo size"); |
258 | #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ | 258 | #endif /* USE_CUSTOM_FIFO_LAYOUT */ |
259 | 259 | ||
260 | /* do some logging */ | 260 | /* do some logging */ |
261 | logf("hwcfg1: %08lx", USB_GHWCFG1); | 261 | logf("hwcfg1: %08lx", GHWCFG1); |
262 | logf("hwcfg2: %08lx", USB_GHWCFG2); | 262 | logf("hwcfg2: %08lx", GHWCFG2); |
263 | logf("hwcfg3: %08lx", USB_GHWCFG3); | 263 | logf("hwcfg3: %08lx", GHWCFG3); |
264 | logf("hwcfg4: %08lx", USB_GHWCFG4); | 264 | logf("hwcfg4: %08lx", GHWCFG4); |
265 | 265 | ||
266 | logf("%ld endpoints", USB_GHWCFG2_NUM_EP); | 266 | logf("%ld endpoints", extract(GHWCFG2, NUM_EP)); |
267 | usb_num_in_ep = 0; | 267 | num_in_ep = 0; |
268 | usb_num_out_ep = 0; | 268 | num_out_ep = 0; |
269 | for(i = 0; i < USB_GHWCFG2_NUM_EP; i++) | 269 | for(i = 0; i < extract(GHWCFG2, NUM_EP); i++) |
270 | { | 270 | { |
271 | if(USB_GHWCFG1_IN_EP(i)) | 271 | if(GHWCFG1 & GHWCFG1_IN_EP(i)) |
272 | usb_num_in_ep++; | 272 | num_in_ep++; |
273 | if(USB_GHWCFG1_OUT_EP(i)) | 273 | if(GHWCFG1 & GHWCFG1_OUT_EP(i)) |
274 | usb_num_out_ep++; | 274 | num_out_ep++; |
275 | logf(" EP%d: IN=%ld OUT=%ld", i, USB_GHWCFG1_IN_EP(i), USB_GHWCFG1_OUT_EP(i)); | 275 | logf(" EP%d: IN=%s OUT=%s", i, |
276 | GHWCFG1 & GHWCFG1_IN_EP(i) ? "yes" : "no", | ||
277 | GHWCFG1 & GHWCFG1_OUT_EP(i) ? "yes" : "no"); | ||
276 | } | 278 | } |
277 | 279 | ||
278 | if(usb_num_in_ep != USB_GHWCFG4_NUM_IN_EP) | 280 | if(num_in_ep != GHWCFG4_NUM_IN_EP) |
279 | panicf("usb: num in ep mismatch(%d,%lu)", usb_num_in_ep, USB_GHWCFG4_NUM_IN_EP); | 281 | panicf("usb: num in ep mismatch(%d,%lu)", num_in_ep, GHWCFG4_NUM_IN_EP); |
280 | if(usb_num_in_ep != USB_NUM_IN_EP) | 282 | if(num_in_ep != NUM_IN_EP) |
281 | panicf("usb: num in ep static mismatch(%u,%u)", usb_num_in_ep, USB_NUM_IN_EP); | 283 | panicf("usb: num in ep static mismatch(%u,%u)", num_in_ep, NUM_IN_EP); |
282 | if(usb_num_out_ep != USB_NUM_OUT_EP) | 284 | if(num_out_ep != NUM_OUT_EP) |
283 | panicf("usb: num out ep static mismatch(%u,%u)", usb_num_out_ep, USB_NUM_OUT_EP); | 285 | panicf("usb: num out ep static mismatch(%u,%u)", num_out_ep, NUM_OUT_EP); |
284 | 286 | ||
285 | logf("%d in ep, %d out ep", usb_num_in_ep, usb_num_out_ep); | 287 | logf("%d in ep, %d out ep", num_in_ep, num_out_ep); |
286 | 288 | ||
287 | logf("initial:"); | 289 | logf("initial:"); |
288 | logf(" tot fifo sz: %lx", USB_GHWCFG3_DFIFO_LEN); | 290 | logf(" tot fifo sz: %lx", GHWCFG3_DFIFO_LEN); |
289 | logf(" rx fifo: [%04x,+%4lx]", 0, USB_GRXFSIZ); | 291 | logf(" rx fifo: [%04x,+%4lx]", 0, GRXFSIZ); |
290 | logf(" nptx fifo: [%04lx,+%4lx]", USB_GET_FIFOSIZE_START_ADR(USB_GNPTXFSIZ), | 292 | logf(" nptx fifo: [%04lx,+%4lx]", GET_FIFOSIZE_START_ADR(GNPTXFSIZ), |
291 | USB_GET_FIFOSIZE_DEPTH(USB_GNPTXFSIZ)); | 293 | GET_FIFOSIZE_DEPTH(GNPTXFSIZ)); |
292 | 294 | ||
293 | #ifdef USB_USE_CUSTOM_FIFO_LAYOUT | 295 | #ifdef USE_CUSTOM_FIFO_LAYOUT |
294 | /* Setup FIFOs */ | 296 | /* Setup FIFOs */ |
295 | /* Organize FIFO as follow: | 297 | /* Organize FIFO as follow: |
296 | * 0 -> rxfsize : RX fifo | 298 | * 0 -> rxfsize : RX fifo |
@@ -301,38 +303,38 @@ static void core_dev_init(void) | |||
301 | */ | 303 | */ |
302 | 304 | ||
303 | unsigned short adr = 0; | 305 | unsigned short adr = 0; |
304 | unsigned short depth = USB_RX_FIFO_SIZE; | 306 | unsigned short depth = RX_FIFO_SIZE; |
305 | USB_GRXFSIZ = depth; | 307 | GRXFSIZ = depth; |
306 | adr += depth; | 308 | adr += depth; |
307 | depth = USB_NPTX_FIFO_SIZE; | 309 | depth = NPTX_FIFO_SIZE; |
308 | USB_GNPTXFSIZ = USB_MAKE_FIFOSIZE_DATA(adr, depth); | 310 | GNPTXFSIZ = MAKE_FIFOSIZE_DATA(adr, depth); |
309 | adr += depth; | 311 | adr += depth; |
310 | 312 | ||
311 | for(i = 1; i <= USB_NUM_IN_EP; i++) | 313 | for(i = 1; i <= NUM_IN_EP; i++) |
312 | { | 314 | { |
313 | depth = USB_EPTX_FIFO_SIZE; | 315 | depth = EPTX_FIFO_SIZE; |
314 | USB_DIEPTXFSIZ(i) = USB_MAKE_FIFOSIZE_DATA(adr, depth); | 316 | DIEPTXFSIZ(i) = MAKE_FIFOSIZE_DATA(adr, depth); |
315 | adr += depth; | 317 | adr += depth; |
316 | } | 318 | } |
317 | 319 | ||
318 | if(adr > USB_DATA_FIFO_DEPTH) | 320 | if(adr > DATA_FIFO_DEPTH) |
319 | panicf("usb: total data fifo size exceeded"); | 321 | panicf("usb: total data fifo size exceeded"); |
320 | #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ | 322 | #endif /* USE_CUSTOM_FIFO_LAYOUT */ |
321 | 323 | ||
322 | for(i = 1; i <= USB_NUM_IN_EP; i++) | 324 | for(i = 1; i <= NUM_IN_EP; i++) |
323 | { | 325 | { |
324 | logf(" dieptx fifo(%2u): [%04lx,+%4lx]", i, | 326 | logf(" dieptx fifo(%2u): [%04lx,+%4lx]", i, |
325 | USB_GET_FIFOSIZE_START_ADR(USB_DIEPTXFSIZ(i)), | 327 | GET_FIFOSIZE_START_ADR(DIEPTXFSIZ(i)), |
326 | USB_GET_FIFOSIZE_DEPTH(USB_DIEPTXFSIZ(i))); | 328 | GET_FIFOSIZE_DEPTH(DIEPTXFSIZ(i))); |
327 | } | 329 | } |
328 | 330 | ||
329 | /* Setup interrupt masks for endpoints */ | 331 | /* Setup interrupt masks for endpoints */ |
330 | /* Setup interrupt masks */ | 332 | /* Setup interrupt masks */ |
331 | USB_DOEPMSK = USB_DOEPINT_setup | USB_DOEPINT_xfercompl | USB_DOEPINT_ahberr | 333 | DOEPMSK = DOEPINT_setup | DOEPINT_xfercompl | DOEPINT_ahberr |
332 | | USB_DOEPINT_epdisabled; | 334 | | DOEPINT_epdisabled; |
333 | USB_DIEPMSK = USB_DIEPINT_xfercompl | USB_DIEPINT_timeout | 335 | DIEPMSK = DIEPINT_xfercompl | DIEPINT_timeout |
334 | | USB_DIEPINT_epdisabled | USB_DIEPINT_ahberr; | 336 | | DIEPINT_epdisabled | DIEPINT_ahberr; |
335 | USB_DAINTMSK = 0xffffffff; | 337 | DAINTMSK = 0xffffffff; |
336 | 338 | ||
337 | reset_endpoints(); | 339 | reset_endpoints(); |
338 | 340 | ||
@@ -340,50 +342,50 @@ static void core_dev_init(void) | |||
340 | /* only dump them for now, leave threshold disabled */ | 342 | /* only dump them for now, leave threshold disabled */ |
341 | /* | 343 | /* |
342 | logf("threshold control:"); | 344 | logf("threshold control:"); |
343 | logf(" non_iso_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_non_iso_thr_en) ? 1 : 0); | 345 | logf(" non_iso_thr_en: %d", (DTHRCTL & DTHRCTL_non_iso_thr_en) ? 1 : 0); |
344 | logf(" iso_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_iso_thr_en) ? 1 : 0); | 346 | logf(" iso_thr_en: %d", (DTHRCTL & DTHRCTL_iso_thr_en) ? 1 : 0); |
345 | logf(" tx_thr_len: %lu", (USB_DTHRCTL & USB_DTHRCTL_tx_thr_len_bits) >> USB_DTHRCTL_tx_thr_len_bit_pos); | 347 | logf(" tx_thr_len: %lu", (DTHRCTL & DTHRCTL_tx_thr_len_bits) >> DTHRCTL_tx_thr_len_bit_pos); |
346 | logf(" rx_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_rx_thr_en) ? 1 : 0); | 348 | logf(" rx_thr_en: %d", (DTHRCTL & DTHRCTL_rx_thr_en) ? 1 : 0); |
347 | logf(" rx_thr_len: %lu", (USB_DTHRCTL & USB_DTHRCTL_rx_thr_len_bits) >> USB_DTHRCTL_rx_thr_len_bit_pos); | 349 | logf(" rx_thr_len: %lu", (DTHRCTL & DTHRCTL_rx_thr_len_bits) >> DTHRCTL_rx_thr_len_bit_pos); |
348 | */ | 350 | */ |
349 | 351 | ||
350 | USB_DTHRCTL = 0; | 352 | DTHRCTL = 0; |
351 | 353 | ||
352 | /* enable USB interrupts */ | 354 | /* enable USB interrupts */ |
353 | usb_enable_device_interrupts(); | 355 | enable_device_interrupts(); |
354 | } | 356 | } |
355 | 357 | ||
356 | static void core_init(void) | 358 | static void core_init(void) |
357 | { | 359 | { |
358 | /* Disconnect */ | 360 | /* Disconnect */ |
359 | USB_DCTL |= USB_DCTL_sftdiscon; | 361 | DCTL |= DCTL_sftdiscon; |
360 | /* Select UTMI+ 16 */ | 362 | /* Select UTMI+ 16 */ |
361 | USB_GUSBCFG |= USB_GUSBCFG_phy_if; | 363 | GUSBCFG |= GUSBCFG_phy_if; |
362 | 364 | ||
363 | /* fixme: the current code is for internal DMA only, the clip+ architecture | 365 | /* fixme: the current code is for internal DMA only, the clip+ architecture |
364 | * define the internal DMA model */ | 366 | * define the internal DMA model */ |
365 | /* Set burstlen and enable DMA*/ | 367 | /* Set burstlen and enable DMA*/ |
366 | USB_GAHBCFG = (USB_GAHBCFG_INT_DMA_BURST_INCR4 << USB_GAHBCFG_hburstlen_bit_pos) | 368 | GAHBCFG = (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bit_pos) |
367 | | USB_GAHBCFG_dma_enable; | 369 | | GAHBCFG_dma_enable; |
368 | /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */ | 370 | /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */ |
369 | USB_GUSBCFG &= ~(USB_GUSBCFG_srpcap | USB_GUSBCFG_hnpcapp); | 371 | GUSBCFG &= ~(GUSBCFG_srpcap | GUSBCFG_hnpcapp); |
370 | 372 | ||
371 | /* perform device model specific init */ | 373 | /* perform device model specific init */ |
372 | core_dev_init(); | 374 | core_dev_init(); |
373 | 375 | ||
374 | /* Reconnect */ | 376 | /* Reconnect */ |
375 | USB_DCTL &= ~USB_DCTL_sftdiscon; | 377 | DCTL &= ~DCTL_sftdiscon; |
376 | } | 378 | } |
377 | 379 | ||
378 | static void usb_enable_global_interrupts(void) | 380 | static void enable_global_interrupts(void) |
379 | { | 381 | { |
380 | VIC_INT_ENABLE = INTERRUPT_USB; | 382 | VIC_INT_ENABLE = INTERRUPT_USB; |
381 | USB_GAHBCFG |= USB_GAHBCFG_glblintrmsk; | 383 | GAHBCFG |= GAHBCFG_glblintrmsk; |
382 | } | 384 | } |
383 | 385 | ||
384 | static void usb_disable_global_interrupts(void) | 386 | static void disable_global_interrupts(void) |
385 | { | 387 | { |
386 | USB_GAHBCFG &= ~USB_GAHBCFG_glblintrmsk; | 388 | GAHBCFG &= ~GAHBCFG_glblintrmsk; |
387 | VIC_INT_EN_CLEAR = INTERRUPT_USB; | 389 | VIC_INT_EN_CLEAR = INTERRUPT_USB; |
388 | } | 390 | } |
389 | 391 | ||
@@ -392,11 +394,11 @@ void usb_drv_init(void) | |||
392 | logf("usb_drv_init"); | 394 | logf("usb_drv_init"); |
393 | /* Enable PHY and clocks (but leave pullups disabled) */ | 395 | /* Enable PHY and clocks (but leave pullups disabled) */ |
394 | as3525v2_connect(); | 396 | as3525v2_connect(); |
395 | logf("usb: synopsis id: %lx", USB_GSNPSID); | 397 | logf("usb: synopsis id: %lx", GSNPSID); |
396 | /* Core init */ | 398 | /* Core init */ |
397 | core_init(); | 399 | core_init(); |
398 | /* Enable global interrupts */ | 400 | /* Enable global interrupts */ |
399 | usb_enable_global_interrupts(); | 401 | enable_global_interrupts(); |
400 | } | 402 | } |
401 | 403 | ||
402 | void usb_drv_exit(void) | 404 | void usb_drv_exit(void) |
@@ -404,23 +406,23 @@ void usb_drv_exit(void) | |||
404 | logf("usb_drv_exit"); | 406 | logf("usb_drv_exit"); |
405 | } | 407 | } |
406 | 408 | ||
407 | static bool handle_usb_reset(void) | 409 | static bool handle_reset(void) |
408 | { | 410 | { |
409 | logf("usb: bus reset"); | 411 | logf("usb: bus reset"); |
410 | 412 | ||
411 | /* Clear the Remote Wakeup Signalling */ | 413 | /* Clear the Remote Wakeup Signalling */ |
412 | USB_DCTL &= ~USB_DCTL_rmtwkupsig; | 414 | DCTL &= ~DCTL_rmtwkupsig; |
413 | 415 | ||
414 | /* Flush FIFOs */ | 416 | /* Flush FIFOs */ |
415 | usb_flush_tx_fifos(0x10); | 417 | flush_tx_fifos(0x10); |
416 | 418 | ||
417 | /* Flush the Learning Queue */ | 419 | /* Flush the Learning Queue */ |
418 | USB_GRSTCTL = USB_GRSTCTL_intknqflsh; | 420 | GRSTCTL = GRSTCTL_intknqflsh; |
419 | 421 | ||
420 | reset_endpoints(); | 422 | reset_endpoints(); |
421 | 423 | ||
422 | /* Reset Device Address */ | 424 | /* Reset Device Address */ |
423 | USB_DCFG &= ~USB_DCFG_devadr_bits; | 425 | DCFG &= ~DCFG_devadr_bits; |
424 | 426 | ||
425 | usb_core_bus_reset(); | 427 | usb_core_bus_reset(); |
426 | 428 | ||
@@ -432,51 +434,51 @@ static bool handle_enum_done(void) | |||
432 | logf("usb: enum done"); | 434 | logf("usb: enum done"); |
433 | 435 | ||
434 | /* read speed */ | 436 | /* read speed */ |
435 | logf("DSTS: %lx", USB_DSTS); | 437 | logf("DSTS: %lx", DSTS); |
436 | logf("DOEPCTL0=%lx", USB_DOEPCTL(0)); | 438 | logf("DOEPCTL0=%lx", DOEPCTL(0)); |
437 | logf("DOEPTSIZ=%lx", USB_DOEPTSIZ(0)); | 439 | logf("DOEPTSIZ=%lx", DOEPTSIZ(0)); |
438 | logf("DIEPCTL0=%lx", USB_DIEPCTL(0)); | 440 | logf("DIEPCTL0=%lx", DIEPCTL(0)); |
439 | logf("DOEPMSK=%lx", USB_DOEPMSK); | 441 | logf("DOEPMSK=%lx", DOEPMSK); |
440 | logf("DIEPMSK=%lx", USB_DIEPMSK); | 442 | logf("DIEPMSK=%lx", DIEPMSK); |
441 | logf("DAINTMSK=%lx", USB_DAINTMSK); | 443 | logf("DAINTMSK=%lx", DAINTMSK); |
442 | logf("DAINT=%lx", USB_DAINT); | 444 | logf("DAINT=%lx", DAINT); |
443 | logf("GINTSTS=%lx", USB_GINTSTS); | 445 | logf("GINTSTS=%lx", GINTSTS); |
444 | logf("GINTMSK=%lx", USB_GINTMSK); | 446 | logf("GINTMSK=%lx", GINTMSK); |
445 | logf("DCTL=%lx", USB_DCTL); | 447 | logf("DCTL=%lx", DCTL); |
446 | logf("GAHBCFG=%lx", USB_GAHBCFG); | 448 | logf("GAHBCFG=%lx", GAHBCFG); |
447 | logf("GUSBCFG=%lx", USB_GUSBCFG); | 449 | logf("GUSBCFG=%lx", GUSBCFG); |
448 | logf("DCFG=%lx", USB_DCFG); | 450 | logf("DCFG=%lx", DCFG); |
449 | logf("DTHRCTL=%lx", USB_DTHRCTL); | 451 | logf("DTHRCTL=%lx", DTHRCTL); |
450 | 452 | ||
451 | switch((USB_DSTS & USB_DSTS_enumspd_bits) >> USB_DSTS_enumspd_bit_pos) | 453 | switch((DSTS & DSTS_enumspd_bits) >> DSTS_enumspd_bit_pos) |
452 | { | 454 | { |
453 | case USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: | 455 | case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: |
454 | logf("usb: HS"); | 456 | logf("usb: HS"); |
455 | break; | 457 | break; |
456 | case USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: | 458 | case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: |
457 | case USB_DSTS_ENUMSPD_FS_PHY_48MHZ: | 459 | case DSTS_ENUMSPD_FS_PHY_48MHZ: |
458 | logf("usb: FS"); | 460 | logf("usb: FS"); |
459 | break; | 461 | break; |
460 | case USB_DSTS_ENUMSPD_LS_PHY_6MHZ: | 462 | case DSTS_ENUMSPD_LS_PHY_6MHZ: |
461 | panicf("usb: LS is not supported"); | 463 | panicf("usb: LS is not supported"); |
462 | } | 464 | } |
463 | 465 | ||
464 | USB_DOEPCTL(0) = (USB_DOEPCTL(0) & ~USB_DEPCTL_mps_bits) | 466 | DOEPCTL(0) = (DOEPCTL(0) & ~DEPCTL_mps_bits) |
465 | | (USB_DEPCTL_MPS_64 << USB_DEPCTL_mps_bit_pos); | 467 | | (DEPCTL_MPS_64 << DEPCTL_mps_bit_pos); |
466 | USB_DIEPCTL(0) = (USB_DIEPCTL(0) & ~USB_DEPCTL_mps_bits) | 468 | DIEPCTL(0) = (DIEPCTL(0) & ~DEPCTL_mps_bits) |
467 | | (USB_DEPCTL_MPS_64 << USB_DEPCTL_mps_bit_pos); | 469 | | (DEPCTL_MPS_64 << DEPCTL_mps_bit_pos); |
468 | 470 | ||
469 | unsigned i, ep; | 471 | unsigned i, ep; |
470 | FOR_EACH_IN_EP(i, ep) | 472 | FOR_EACH_IN_EP(i, ep) |
471 | USB_DIEPCTL(ep) = (USB_DIEPCTL(ep) & ~USB_DEPCTL_mps_bits) | 473 | DIEPCTL(ep) = (DIEPCTL(ep) & ~DEPCTL_mps_bits) |
472 | | (512 << USB_DEPCTL_mps_bit_pos); | 474 | | (512 << DEPCTL_mps_bit_pos); |
473 | 475 | ||
474 | FOR_EACH_OUT_EP(i, ep) | 476 | FOR_EACH_OUT_EP(i, ep) |
475 | USB_DOEPCTL(ep) = (USB_DOEPCTL(ep) & ~USB_DEPCTL_mps_bits) | 477 | DOEPCTL(ep) = (DOEPCTL(ep) & ~DEPCTL_mps_bits) |
476 | | (512 << USB_DEPCTL_mps_bit_pos); | 478 | | (512 << DEPCTL_mps_bit_pos); |
477 | 479 | ||
478 | USB_DOEPTSIZ(0) = (1 << USB_DEPTSIZ0_supcnt_bit_pos) | 480 | DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bit_pos) |
479 | | (1 << USB_DEPTSIZ0_pkcnt_bit_pos) | 481 | | (1 << DEPTSIZ0_pkcnt_bit_pos) |
480 | | 64; | 482 | | 64; |
481 | 483 | ||
482 | return true; | 484 | return true; |
@@ -499,7 +501,7 @@ static void dump_intsts(char *buffer, size_t size, unsigned long sts) | |||
499 | (void) size; | 501 | (void) size; |
500 | buffer[0] = 0; | 502 | buffer[0] = 0; |
501 | #define DUMP_CASE(name) \ | 503 | #define DUMP_CASE(name) \ |
502 | if(sts & USB_GINTMSK_##name) strcat(buffer, #name " "); | 504 | if(sts & GINTMSK_##name) strcat(buffer, #name " "); |
503 | 505 | ||
504 | DUMP_CASE(modemismatch) | 506 | DUMP_CASE(modemismatch) |
505 | DUMP_CASE(otgintr) | 507 | DUMP_CASE(otgintr) |
@@ -536,7 +538,7 @@ void INT_USB(void) | |||
536 | { | 538 | { |
537 | /* some bits in GINTSTS can be set even though we didn't enable the interrupt source | 539 | /* some bits in GINTSTS can be set even though we didn't enable the interrupt source |
538 | * so AND it with the actual mask */ | 540 | * so AND it with the actual mask */ |
539 | unsigned long sts = USB_GINTSTS & USB_GINTMSK; | 541 | unsigned long sts = GINTSTS & GINTMSK; |
540 | unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */ | 542 | unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */ |
541 | 543 | ||
542 | #define HANDLED_CASE(bitmask, callfn) \ | 544 | #define HANDLED_CASE(bitmask, callfn) \ |
@@ -553,25 +555,25 @@ void INT_USB(void) | |||
553 | goto Lunhandled; | 555 | goto Lunhandled; |
554 | 556 | ||
555 | /* device part */ | 557 | /* device part */ |
556 | HANDLED_CASE(USB_GINTMSK_usbreset, handle_usb_reset) | 558 | HANDLED_CASE(GINTMSK_usbreset, handle_reset) |
557 | HANDLED_CASE(USB_GINTMSK_enumdone, handle_enum_done) | 559 | HANDLED_CASE(GINTMSK_enumdone, handle_enum_done) |
558 | /* | 560 | /* |
559 | HANDLED_CASE(USB_GINTMSK_inepintr, handle_in_ep_int) | 561 | HANDLED_CASE(GINTMSK_inepintr, handle_in_ep_int) |
560 | HANDLED_CASE(USB_GINTMSK_outepintr, handle_out_ep_int) | 562 | HANDLED_CASE(GINTMSK_outepintr, handle_out_ep_int) |
561 | */ | 563 | */ |
562 | UNHANDLED_CASE(USB_GINTMSK_outepintr) | 564 | UNHANDLED_CASE(GINTMSK_outepintr) |
563 | UNHANDLED_CASE(USB_GINTMSK_inepintr) | 565 | UNHANDLED_CASE(GINTMSK_inepintr) |
564 | 566 | ||
565 | /* common part */ | 567 | /* common part */ |
566 | UNHANDLED_CASE(USB_GINTMSK_otgintr) | 568 | UNHANDLED_CASE(GINTMSK_otgintr) |
567 | UNHANDLED_CASE(USB_GINTMSK_conidstschng) | 569 | UNHANDLED_CASE(GINTMSK_conidstschng) |
568 | UNHANDLED_CASE(USB_GINTMSK_disconnect) | 570 | UNHANDLED_CASE(GINTMSK_disconnect) |
569 | 571 | ||
570 | /* unlisted ones */ | 572 | /* unlisted ones */ |
571 | if(sts & ~handled_one) | 573 | if(sts & ~handled_one) |
572 | goto Lunhandled; | 574 | goto Lunhandled; |
573 | 575 | ||
574 | USB_GINTSTS = USB_GINTSTS; | 576 | GINTSTS = GINTSTS; |
575 | 577 | ||
576 | return; | 578 | return; |
577 | 579 | ||
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index 23be1c5b49..96b13f2028 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h | |||
@@ -23,254 +23,306 @@ | |||
23 | 23 | ||
24 | #include "as3525v2.h" | 24 | #include "as3525v2.h" |
25 | 25 | ||
26 | /* All multi-bit fields in the driver use the following convention. | ||
27 | * If the register name is NAME, then there is one define NAME_bit_pos | ||
28 | * which holds the bit position and one define NAME_bits which holds | ||
29 | * a mask of the bits within the register. | ||
30 | * These macros allow easy access and construction of such fields */ | ||
31 | /* Usage: | ||
32 | * - extract(reg_name,field_name) | ||
33 | note: the field_name must not be prefix with the reg name */ | ||
34 | #define extract(reg_name, field_name) \ | ||
35 | ((reg_name & reg_name##_##field_name##_bits) >> reg_name##_##field_name##_bit_pos) | ||
36 | |||
26 | #define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */ | 37 | #define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */ |
27 | 38 | ||
28 | /** | 39 | /** |
29 | * Core Global Registers | 40 | * Core Global Registers |
30 | */ | 41 | */ |
31 | #define USB_BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset)) | 42 | #define BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset)) |
32 | 43 | ||
33 | #define USB_GOTGCTL USB_BASE_REG(0x000) /** OTG Control and Status Register */ | 44 | /** OTG Control and Status Register */ |
34 | #define USB_GOTGINT USB_BASE_REG(0x004) /** OTG Interrupt Register */ | 45 | #define GOTGCTL BASE_REG(0x000) |
35 | #define USB_GAHBCFG USB_BASE_REG(0x008) /** Core AHB Configuration Register */ | 46 | |
36 | #define USB_GUSBCFG USB_BASE_REG(0x00C) /** Core USB Configuration Register */ | 47 | /** OTG Interrupt Register */ |
37 | #define USB_GRSTCTL USB_BASE_REG(0x010) /** Core Reset Register */ | 48 | #define GOTGINT BASE_REG(0x004) |
38 | #define USB_GINTSTS USB_BASE_REG(0x014) /** Core Interrupt Register */ | 49 | |
39 | #define USB_GINTMSK USB_BASE_REG(0x018) /** Core Interrupt Mask Register */ | 50 | /** Core AHB Configuration Register */ |
40 | #define USB_GRXSTSR USB_BASE_REG(0x01C) /** Receive Status Debug Read Register (Read Only) */ | 51 | #define GAHBCFG BASE_REG(0x008) |
41 | #define USB_GRXSTSP USB_BASE_REG(0x020) /** Receive Status Read /Pop Register (Read Only) */ | 52 | #define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ |
42 | #define USB_GRXFSIZ USB_BASE_REG(0x024) /** Receive FIFO Size Register */ | 53 | #define GAHBCFG_hburstlen_bit_pos 1 |
43 | #define USB_GNPTXFSIZ USB_BASE_REG(0x028) /** Periodic Transmit FIFO Size Register */ | 54 | #define GAHBCFG_INT_DMA_BURST_SINGLE 0 |
44 | #define USB_GNPTXSTS USB_BASE_REG(0x02C) /** Non-Periodic Transmit FIFO/Queue Status Register */ | 55 | #define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ |
45 | #define USB_GI2CCTL USB_BASE_REG(0x030) /** I2C Access Register */ | 56 | #define GAHBCFG_INT_DMA_BURST_INCR4 3 |
46 | #define USB_GPVNDCTL USB_BASE_REG(0x034) /** PHY Vendor Control Register */ | 57 | #define GAHBCFG_INT_DMA_BURST_INCR8 5 |
47 | #define USB_GGPIO USB_BASE_REG(0x038) /** General Purpose Input/Output Register */ | 58 | #define GAHBCFG_INT_DMA_BURST_INCR16 7 |
48 | #define USB_GUID USB_BASE_REG(0x03C) /** User ID Register */ | 59 | #define GAHBCFG_dma_enable (1 << 5) /** Enable DMA */ |
49 | #define USB_GSNPSID USB_BASE_REG(0x040) /** Synopsys ID Register */ | 60 | |
50 | #define USB_GHWCFG1 USB_BASE_REG(0x044) /** User HW Config1 Register */ | 61 | /** Core USB Configuration Register */ |
51 | #define USB_GHWCFG2 USB_BASE_REG(0x048) /** User HW Config2 Register */ | 62 | #define GUSBCFG BASE_REG(0x00C) |
52 | #define USB_GHWCFG3 USB_BASE_REG(0x04C) /** User HW Config3 Register */ | 63 | #define GUSBCFG_toutcal_bit_pos 0 |
53 | #define USB_GHWCFG4 USB_BASE_REG(0x050) /** User HW Config4 Register */ | 64 | #define GUSBCFG_toutcal_bits (0x7 << GUSBCFG_toutcal_bit_pos) |
65 | #define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ | ||
66 | #define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ | ||
67 | #define GUSBCFG_fsintf (1 << 5) | ||
68 | #define GUSBCFG_physel (1 << 6) | ||
69 | #define GUSBCFG_ddrsel (1 << 7) | ||
70 | #define GUSBCFG_srpcap (1 << 8) | ||
71 | #define GUSBCFG_hnpcapp (1 << 9) | ||
72 | #define GUSBCFG_usbtrdtim_bit_pos 10 | ||
73 | #define GUSBCFG_usbtrdtim_bits (0xf << GUSBCFG_usbtrdtim_bit_pos) | ||
74 | #define GUSBCFG_nptxfrwnden (1 << 14) | ||
75 | #define GUSBCFG_phylpwrclksel (1 << 15) | ||
76 | #define GUSBCFG_otgutmifssel (1 << 16) | ||
77 | #define GUSBCFG_ulpi_fsls (1 << 17) | ||
78 | #define GUSBCFG_ulpi_auto_res (1 << 18) | ||
79 | #define GUSBCFG_ulpi_clk_sus_m (1 << 19) | ||
80 | #define GUSBCFG_ulpi_ext_vbus_drv (1 << 20) | ||
81 | #define GUSBCFG_ulpi_int_vbus_indicator (1 << 21) | ||
82 | #define GUSBCFG_term_sel_dl_pulse (1 << 22) | ||
83 | #define GUSBCFG_force_host_mode (1 << 29) | ||
84 | #define GUSBCFG_force_device_mode (1 << 30) | ||
85 | #define GUSBCFG_corrupt_tx_packet (1 << 31) | ||
86 | |||
87 | /** Core Reset Register */ | ||
88 | #define GRSTCTL BASE_REG(0x010) | ||
89 | #define GRSTCTL_csftrst (1 << 0) /** Core soft reset */ | ||
90 | #define GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ | ||
91 | #define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ | ||
92 | #define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ | ||
93 | #define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ | ||
94 | #define GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */ | ||
95 | #define GRSTCTL_txfnum_bits (0x1f << 6) | ||
96 | #define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ | ||
97 | |||
98 | /** Core Interrupt Register */ | ||
99 | #define GINTSTS BASE_REG(0x014) | ||
100 | /* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */ | ||
101 | #define GINTSTS_curmode (1 << 0) /** Current mode, 0 for device */ | ||
102 | |||
103 | /** Core Interrupt Mask Register */ | ||
104 | #define GINTMSK BASE_REG(0x018) | ||
105 | #define GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */ | ||
106 | #define GINTMSK_otgintr (1 << 2) | ||
107 | #define GINTMSK_sofintr (1 << 3) | ||
108 | #define GINTMSK_rxstsqlvl (1 << 4) | ||
109 | #define GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */ | ||
110 | #define GINTMSK_ginnakeff (1 << 6) | ||
111 | #define GINTMSK_goutnakeff (1 << 7) | ||
112 | #define GINTMSK_i2cintr (1 << 9) | ||
113 | #define GINTMSK_erlysuspend (1 << 10) | ||
114 | #define GINTMSK_usbsuspend (1 << 11) /** USB suspend */ | ||
115 | #define GINTMSK_usbreset (1 << 12) /** USB reset */ | ||
116 | #define GINTMSK_enumdone (1 << 13) /** Enumeration done */ | ||
117 | #define GINTMSK_isooutdrop (1 << 14) | ||
118 | #define GINTMSK_eopframe (1 << 15) | ||
119 | #define GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */ | ||
120 | #define GINTMSK_inepintr (1 << 18) /** in pending ? */ | ||
121 | #define GINTMSK_outepintr (1 << 19) /** out pending ? */ | ||
122 | #define GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */ | ||
123 | #define GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */ | ||
124 | #define GINTMSK_portintr (1 << 24) /** Port status change ? */ | ||
125 | #define GINTMSK_hcintr (1 << 25) | ||
126 | #define GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */ | ||
127 | #define GINTMSK_conidstschng (1 << 28) | ||
128 | #define GINTMSK_disconnect (1 << 29) /** Disconnect */ | ||
129 | #define GINTMSK_sessreqintr (1 << 30) /** Session request */ | ||
130 | #define GINTMSK_wkupintr (1 << 31) /** Wake up */ | ||
131 | |||
132 | /** Receive Status Debug Read Register (Read Only) */ | ||
133 | #define GRXSTSR BASE_REG(0x01C) | ||
134 | |||
135 | /** Receive Status Read /Pop Register (Read Only) */ | ||
136 | #define GRXSTSP BASE_REG(0x020) | ||
137 | |||
138 | /** Receive FIFO Size Register */ | ||
139 | #define GRXFSIZ BASE_REG(0x024) | ||
140 | |||
141 | /** Periodic Transmit FIFO Size Register */ | ||
142 | #define GNPTXFSIZ BASE_REG(0x028) | ||
143 | |||
144 | /** Non-Periodic Transmit FIFO/Queue Status Register */ | ||
145 | #define GNPTXSTS BASE_REG(0x02C) | ||
146 | |||
147 | /** I2C Access Register */ | ||
148 | #define GI2CCTL BASE_REG(0x030) | ||
149 | |||
150 | /** PHY Vendor Control Register */ | ||
151 | #define GPVNDCTL BASE_REG(0x034) | ||
152 | |||
153 | /** General Purpose Input/Output Register */ | ||
154 | #define GGPIO BASE_REG(0x038) | ||
155 | |||
156 | /** User ID Register */ | ||
157 | #define GUID BASE_REG(0x03C) | ||
158 | |||
159 | /** Synopsys ID Register */ | ||
160 | #define GSNPSID BASE_REG(0x040) | ||
161 | |||
162 | /** User HW Config1 Register */ | ||
163 | #define GHWCFG1 BASE_REG(0x044) | ||
164 | #define GHWCFG1_IN_EP(ep) (1 << (2 * (ep))) /** 1 if EP(ep) has in cap */ | ||
165 | #define GHWCFG1_OUT_EP(ep) (1 << (1 + 2 * (ep))) /** same for out */ | ||
166 | |||
167 | /** User HW Config2 Register */ | ||
168 | #define GHWCFG2 BASE_REG(0x048) | ||
169 | #define GHWCFG2_ARCH_bit_pos 3 /** Architecture */ | ||
170 | #define GHWCFG2_ARCH_bits (0x3 << GHWCFG2_ARCH_bit_pos) | ||
171 | #define GHWCFG2_HS_PHY_TYPE_bit_pos 6 /** High speed PHY type */ | ||
172 | #define GHWCFG2_HS_PHY_TYPE_bits (0x3 << GHWCFG2_HS_PHY_TYPE_bit_pos) | ||
173 | #define GHWCFG2_FS_PHY_TYPE_bit_pos 8 /** Full speed PHY type */ | ||
174 | #define GHWCFG2_FS_PHY_TYPE_bits (0x3 << GHWCFG2_FS_PHY_TYPE_bit_pos) | ||
175 | #define GHWCFG2_NUM_EP_bit_pos 10 /** Number of endpoints */ | ||
176 | #define GHWCFG2_NUM_EP_bits (0xf << GHWCFG2_NUM_EP_bit_pos) | ||
177 | #define GHWCFG2_DYN_FIFO (1 << 19) /** Dynamic FIFO */ | ||
178 | /* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_SS_PHY_TYPE */ | ||
179 | #define PHY_TYPE_UNSUPPORTED 0 | ||
180 | #define PHY_TYPE_UTMI 1 | ||
181 | #define INT_DMA_ARCH 2 | ||
182 | |||
183 | /** User HW Config3 Register */ | ||
184 | #define GHWCFG3 BASE_REG(0x04C) | ||
185 | |||
186 | /** User HW Config4 Register */ | ||
187 | #define GHWCFG4 BASE_REG(0x050) | ||
54 | 188 | ||
55 | /* 1<=ep<=15, don't use ep=0 !!! */ | 189 | /* 1<=ep<=15, don't use ep=0 !!! */ |
56 | /** Device IN Endpoint Transmit FIFO (ep) Size Register */ | 190 | /** Device IN Endpoint Transmit FIFO (ep) Size Register */ |
57 | #define USB_DIEPTXFSIZ(ep) USB_BASE_REG(0x100 + 4 * (ep)) | 191 | #define DIEPTXFSIZ(ep) BASE_REG(0x100 + 4 * (ep)) |
58 | 192 | ||
59 | /** Build the content of a FIFO size register like USB_DIEPTXFSIZ(i) and USB_GNPTXFSIZ*/ | 193 | /** Build the content of a FIFO size register like DIEPTXFSIZ(i) and GNPTXFSIZ*/ |
60 | #define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \ | 194 | #define MAKE_FIFOSIZE_DATA(startadr, depth) \ |
61 | (((startadr) & 0xffff) | ((depth) << 16)) | 195 | (((startadr) & 0xffff) | ((depth) << 16)) |
62 | |||
63 | /** Retrieve fifo size for such registers */ | 196 | /** Retrieve fifo size for such registers */ |
64 | #define USB_GET_FIFOSIZE_DEPTH(data) \ | 197 | #define GET_FIFOSIZE_DEPTH(data) \ |
65 | ((data) >> 16) | 198 | ((data) >> 16) |
66 | |||
67 | /** Retrieve fifo start address for such registers */ | 199 | /** Retrieve fifo start address for such registers */ |
68 | #define USB_GET_FIFOSIZE_START_ADR(data) \ | 200 | #define GET_FIFOSIZE_START_ADR(data) \ |
69 | ((data) & 0xffff) | 201 | ((data) & 0xffff) |
70 | 202 | ||
71 | #define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */ | 203 | |
72 | #define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ | 204 | |
73 | #define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ | 205 | |
74 | #define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ | 206 | |
75 | #define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ | 207 | #define GHWCFG3_DFIFO_LEN (GHWCFG3 >> 16) /** Total fifo size */ |
76 | #define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */ | 208 | |
77 | #define USB_GRSTCTL_txfnum_bits (0x1f << 6) | 209 | #define GHWCFG4_UTMI_PHY_DATA_WIDTH ((GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */ |
78 | #define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ | 210 | #define GHWCFG4_DED_FIFO_EN ((GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */ |
79 | 211 | #define GHWCFG4_NUM_IN_EP ((GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */ | |
80 | #define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */ | 212 | |
81 | #define USB_GHWCFG1_OUT_EP(ep) ((USB_GHWCFG1 >> ((ep) *2 + 1)) & 0x1)/** 1 if EP(ep) has out cap */ | 213 | |
82 | |||
83 | #define USB_GHWCFG2_ARCH ((USB_GHWCFG2 >> 3) & 0x3) /** Architecture */ | ||
84 | #define USB_GHWCFG2_HS_PHY_TYPE ((USB_GHWCFG2 >> 6) & 0x3) /** High speed PHY type */ | ||
85 | #define USB_GHWCFG2_FS_PHY_TYPE ((USB_GHWCFG2 >> 8) & 0x3) /** Full speed PHY type */ | ||
86 | #define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */ | ||
87 | #define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */ | ||
88 | |||
89 | /* For USB_GHWCFG2_HS_PHY_TYPE and USB_GHWCFG2_SS_PHY_TYPE */ | ||
90 | #define USB_PHY_TYPE_UNSUPPORTED 0 | ||
91 | #define USB_PHY_TYPE_UTMI 1 | ||
92 | #define USB_INT_DMA_ARCH 2 | ||
93 | |||
94 | #define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */ | ||
95 | |||
96 | #define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */ | ||
97 | #define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */ | ||
98 | #define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */ | ||
99 | |||
100 | #define USB_GUSBCFG_toutcal_bit_pos 0 | ||
101 | #define USB_GUSBCFG_toutcal_bits (0x7 << USB_GUSBCFG_toutcal_bit_pos) | ||
102 | #define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ | ||
103 | #define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ | ||
104 | #define USB_GUSBCFG_fsintf (1 << 5) | ||
105 | #define USB_GUSBCFG_physel (1 << 6) | ||
106 | #define USB_GUSBCFG_ddrsel (1 << 7) | ||
107 | #define USB_GUSBCFG_srpcap (1 << 8) | ||
108 | #define USB_GUSBCFG_hnpcapp (1 << 9) | ||
109 | #define USB_GUSBCFG_usbtrdtim_bit_pos 10 | ||
110 | #define USB_GUSBCFG_usbtrdtim_bits (0xf << USB_GUSBCFG_usbtrdtim_bit_pos) | ||
111 | #define USB_GUSBCFG_nptxfrwnden (1 << 14) | ||
112 | #define USB_GUSBCFG_phylpwrclksel (1 << 15) | ||
113 | #define USB_GUSBCFG_otgutmifssel (1 << 16) | ||
114 | #define USB_GUSBCFG_ulpi_fsls (1 << 17) | ||
115 | #define USB_GUSBCFG_ulpi_auto_res (1 << 18) | ||
116 | #define USB_GUSBCFG_ulpi_clk_sus_m (1 << 19) | ||
117 | #define USB_GUSBCFG_ulpi_ext_vbus_drv (1 << 20) | ||
118 | #define USB_GUSBCFG_ulpi_int_vbus_indicator (1 << 21) | ||
119 | #define USB_GUSBCFG_term_sel_dl_pulse (1 << 22) | ||
120 | #define USB_GUSBCFG_force_host_mode (1 << 29) | ||
121 | #define USB_GUSBCFG_force_device_mode (1 << 30) | ||
122 | #define USB_GUSBCFG_corrupt_tx_packet (1 << 31) | ||
123 | |||
124 | #define USB_GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ | ||
125 | #define USB_GAHBCFG_hburstlen_bit_pos 1 | ||
126 | #define USB_GAHBCFG_INT_DMA_BURST_SINGLE 0 | ||
127 | #define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ | ||
128 | #define USB_GAHBCFG_INT_DMA_BURST_INCR4 3 | ||
129 | #define USB_GAHBCFG_INT_DMA_BURST_INCR8 5 | ||
130 | #define USB_GAHBCFG_INT_DMA_BURST_INCR16 7 | ||
131 | #define USB_GAHBCFG_dma_enable (1 << 5) /** Enable DMA */ | ||
132 | |||
133 | /* NOTE: USB_GINTSTS bits are the same as in USB_GINTMSK plus the following one */ | ||
134 | #define USB_GINTSTS_curmode (1 << 0) /** Current mode: 1 for host, 0 for device */ | ||
135 | |||
136 | #define USB_GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */ | ||
137 | #define USB_GINTMSK_otgintr (1 << 2) | ||
138 | #define USB_GINTMSK_sofintr (1 << 3) | ||
139 | #define USB_GINTMSK_rxstsqlvl (1 << 4) | ||
140 | #define USB_GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */ | ||
141 | #define USB_GINTMSK_ginnakeff (1 << 6) | ||
142 | #define USB_GINTMSK_goutnakeff (1 << 7) | ||
143 | #define USB_GINTMSK_i2cintr (1 << 9) | ||
144 | #define USB_GINTMSK_erlysuspend (1 << 10) | ||
145 | #define USB_GINTMSK_usbsuspend (1 << 11) /** USB suspend */ | ||
146 | #define USB_GINTMSK_usbreset (1 << 12) /** USB reset */ | ||
147 | #define USB_GINTMSK_enumdone (1 << 13) /** Enumeration done */ | ||
148 | #define USB_GINTMSK_isooutdrop (1 << 14) | ||
149 | #define USB_GINTMSK_eopframe (1 << 15) | ||
150 | #define USB_GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */ | ||
151 | #define USB_GINTMSK_inepintr (1 << 18) /** in pending ? */ | ||
152 | #define USB_GINTMSK_outepintr (1 << 19) /** out pending ? */ | ||
153 | #define USB_GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */ | ||
154 | #define USB_GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */ | ||
155 | #define USB_GINTMSK_portintr (1 << 24) /** Port status change ? */ | ||
156 | #define USB_GINTMSK_hcintr (1 << 25) | ||
157 | #define USB_GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */ | ||
158 | #define USB_GINTMSK_conidstschng (1 << 28) | ||
159 | #define USB_GINTMSK_disconnect (1 << 29) /** Disconnect */ | ||
160 | #define USB_GINTMSK_sessreqintr (1 << 30) /** Session request */ | ||
161 | #define USB_GINTMSK_wkupintr (1 << 31) /** Wake up */ | ||
162 | 214 | ||
163 | /** | 215 | /** |
164 | * Device Registers Base Addresses | 216 | * Device Registers Base Addresses |
165 | */ | 217 | */ |
166 | #define USB_DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset)) | 218 | #define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset)) |
167 | 219 | ||
168 | #define USB_DCFG USB_DEV_REG(0x00) /** Device Configuration Register */ | 220 | #define DCFG DEV_REG(0x00) /** Device Configuration Register */ |
169 | #define USB_DCTL USB_DEV_REG(0x04) /** Device Control Register */ | 221 | #define DCTL DEV_REG(0x04) /** Device Control Register */ |
170 | #define USB_DSTS USB_DEV_REG(0x08) /** Device Status Register */ | 222 | #define DSTS DEV_REG(0x08) /** Device Status Register */ |
171 | #define USB_DIEPMSK USB_DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */ | 223 | #define DIEPMSK DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */ |
172 | #define USB_DOEPMSK USB_DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */ | 224 | #define DOEPMSK DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */ |
173 | #define USB_DAINT USB_DEV_REG(0x18) /** Device All Endpoints Interrupt Register */ | 225 | #define DAINT DEV_REG(0x18) /** Device All Endpoints Interrupt Register */ |
174 | #define USB_DAINTMSK USB_DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */ | 226 | #define DAINTMSK DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */ |
175 | #define USB_DTKNQR1 USB_DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */ | 227 | #define DTKNQR1 DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */ |
176 | #define USB_DTKNQR2 USB_DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */ | 228 | #define DTKNQR2 DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */ |
177 | #define USB_DTKNQP USB_DEV_REG(0x28) /** Device IN Token Queue Pop register */ | 229 | #define DTKNQP DEV_REG(0x28) /** Device IN Token Queue Pop register */ |
178 | /* fixme: those registers are not present in usb_registers.h but are in dwc_otgh_regs.h. | 230 | /* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h. |
179 | * the previous registers exists but has a different name :( */ | 231 | * the previous registers exists but has a different name :( */ |
180 | #define USB_DVBUSDIS USB_DEV_REG(0x28) /** Device VBUS discharge register*/ | 232 | #define DVBUSDIS DEV_REG(0x28) /** Device VBUS discharge register*/ |
181 | #define USB_DVBUSPULSE USB_DEV_REG(0x2C) /** Device VBUS pulse register */ | 233 | #define DVBUSPULSE DEV_REG(0x2C) /** Device VBUS pulse register */ |
182 | #define USB_DTKNQR3 USB_DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */ | 234 | #define DTKNQR3 DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */ |
183 | #define USB_DTHRCTL USB_DEV_REG(0x30) /** Device Thresholding control register */ | 235 | #define DTHRCTL DEV_REG(0x30) /** Device Thresholding control register */ |
184 | #define USB_DTKNQR4 USB_DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */ | 236 | #define DTKNQR4 DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */ |
185 | #define USB_FFEMPTYMSK USB_DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */ | 237 | #define FFEMPTYMSK DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */ |
186 | 238 | ||
187 | #define USB_DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ | 239 | #define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ |
188 | #define USB_DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ | 240 | #define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ |
189 | #define USB_DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ | 241 | #define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ |
190 | #define USB_DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ | 242 | #define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ |
191 | #define USB_DCTL_tstctl_bit_pos 4 /** Test Control */ | 243 | #define DCTL_tstctl_bit_pos 4 /** Test Control */ |
192 | #define USB_DCTL_tstctl_bits (0x7 << USB_DCTL_tstctl_bit_pos) | 244 | #define DCTL_tstctl_bits (0x7 << DCTL_tstctl_bit_pos) |
193 | #define USB_DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ | 245 | #define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ |
194 | #define USB_DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ | 246 | #define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ |
195 | #define USB_DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ | 247 | #define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ |
196 | #define USB_DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ | 248 | #define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ |
197 | /* "documented" in usb_constants.h only */ | 249 | /* "documented" in constants.h only */ |
198 | #define USB_DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ | 250 | #define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ |
199 | 251 | ||
200 | #define USB_DCFG_devspd_bits 0x3 /** Device Speed */ | 252 | #define DCFG_devspd_bits 0x3 /** Device Speed */ |
201 | #define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ | 253 | #define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ |
202 | #define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ | 254 | #define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ |
203 | #define USB_DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ | 255 | #define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ |
204 | #define USB_DCFG_devadr_bit_pos 4 /** Device Address */ | 256 | #define DCFG_devadr_bit_pos 4 /** Device Address */ |
205 | #define USB_DCFG_devadr_bits (0x7f << USB_DCFG_devadr_bit_pos) | 257 | #define DCFG_devadr_bits (0x7f << DCFG_devadr_bit_pos) |
206 | #define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */ | 258 | #define DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */ |
207 | #define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos) | 259 | #define DCFG_perfrint_bits (0x3 << DCFG_perfrint_bit_pos) |
208 | #define USB_DCFG_FRAME_INTERVAL_80 0 | 260 | #define DCFG_FRAME_INTERVAL_80 0 |
209 | #define USB_DCFG_FRAME_INTERVAL_85 1 | 261 | #define DCFG_FRAME_INTERVAL_85 1 |
210 | #define USB_DCFG_FRAME_INTERVAL_90 2 | 262 | #define DCFG_FRAME_INTERVAL_90 2 |
211 | #define USB_DCFG_FRAME_INTERVAL_95 3 | 263 | #define DCFG_FRAME_INTERVAL_95 3 |
212 | 264 | ||
213 | #define USB_DSTS_suspsts (1 << 0) /** Suspend status */ | 265 | #define DSTS_suspsts (1 << 0) /** Suspend status */ |
214 | #define USB_DSTS_enumspd_bit_pos 1 /** Enumerated speed */ | 266 | #define DSTS_enumspd_bit_pos 1 /** Enumerated speed */ |
215 | #define USB_DSTS_enumspd_bits (0x3 << USB_DSTS_enumspd_bit_pos) | 267 | #define DSTS_enumspd_bits (0x3 << DSTS_enumspd_bit_pos) |
216 | #define USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 | 268 | #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 |
217 | #define USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 | 269 | #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 |
218 | #define USB_DSTS_ENUMSPD_LS_PHY_6MHZ 2 | 270 | #define DSTS_ENUMSPD_LS_PHY_6MHZ 2 |
219 | #define USB_DSTS_ENUMSPD_FS_PHY_48MHZ 3 | 271 | #define DSTS_ENUMSPD_FS_PHY_48MHZ 3 |
220 | #define USB_DSTS_errticerr (1 << 3) /** Erratic errors ? */ | 272 | #define DSTS_errticerr (1 << 3) /** Erratic errors ? */ |
221 | #define USB_DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */ | 273 | #define DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */ |
222 | #define USB_DSTS_soffn_bits (0x3fff << USB_DSTS_soffn_bit_pos) | 274 | #define DSTS_soffn_bits (0x3fff << DSTS_soffn_bit_pos) |
223 | 275 | ||
224 | #define USB_DTHRCTL_non_iso_thr_en (1 << 0) | 276 | #define DTHRCTL_non_iso_thr_en (1 << 0) |
225 | #define USB_DTHRCTL_iso_thr_en (1 << 1) | 277 | #define DTHRCTL_iso_thr_en (1 << 1) |
226 | #define USB_DTHRCTL_tx_thr_len_bit_pos 2 | 278 | #define DTHRCTL_tx_thr_len_bit_pos 2 |
227 | #define USB_DTHRCTL_tx_thr_len_bits (0x1FF << USB_DTHRCTL_tx_thr_len_bit_pos) | 279 | #define DTHRCTL_tx_thr_len_bits (0x1FF << DTHRCTL_tx_thr_len_bit_pos) |
228 | #define USB_DTHRCTL_rx_thr_en (1 << 16) | 280 | #define DTHRCTL_rx_thr_en (1 << 16) |
229 | #define USB_DTHRCTL_rx_thr_len_bit_pos 17 | 281 | #define DTHRCTL_rx_thr_len_bit_pos 17 |
230 | #define USB_DTHRCTL_rx_thr_len_bits (0x1FF << USB_DTHRCTL_rx_thr_len_bit_pos) | 282 | #define DTHRCTL_rx_thr_len_bits (0x1FF << DTHRCTL_rx_thr_len_bit_pos) |
231 | 283 | ||
232 | /* 0<=ep<=15, you can use ep=0 */ | 284 | /* 0<=ep<=15, you can use ep=0 */ |
233 | /** Device IN Endpoint (ep) Control Register */ | 285 | /** Device IN Endpoint (ep) Control Register */ |
234 | #define USB_DIEPCTL(ep) USB_DEV_REG(0x100 + (ep) * 0x20) | 286 | #define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20) |
235 | /** Device IN Endpoint (ep) Interrupt Register */ | 287 | /** Device IN Endpoint (ep) Interrupt Register */ |
236 | #define USB_DIEPINT(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x8) | 288 | #define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8) |
237 | /** Device IN Endpoint (ep) Transfer Size Register */ | 289 | /** Device IN Endpoint (ep) Transfer Size Register */ |
238 | #define USB_DIEPTSIZ(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x10) | 290 | #define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10) |
239 | /** Device IN Endpoint (ep) DMA Address Register */ | 291 | /** Device IN Endpoint (ep) DMA Address Register */ |
240 | #define USB_DIEPDMA(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x14) | 292 | #define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14) |
241 | /** Device IN Endpoint (ep) Transmit FIFO Status Register */ | 293 | /** Device IN Endpoint (ep) Transmit FIFO Status Register */ |
242 | #define USB_DTXFSTS(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x18) | 294 | #define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18) |
243 | 295 | ||
244 | /* the following also apply to DIEPMSK */ | 296 | /* the following also apply to DIEPMSK */ |
245 | #define USB_DIEPINT_xfercompl (1 << 0) /** Transfer complete */ | 297 | #define DIEPINT_xfercompl (1 << 0) /** Transfer complete */ |
246 | #define USB_DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */ | 298 | #define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */ |
247 | #define USB_DIEPINT_ahberr (1 << 2) /** AHB error */ | 299 | #define DIEPINT_ahberr (1 << 2) /** AHB error */ |
248 | #define USB_DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */ | 300 | #define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */ |
249 | #define USB_DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */ | 301 | #define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */ |
250 | #define USB_DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */ | 302 | #define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */ |
251 | #define USB_DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */ | 303 | #define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */ |
252 | #define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ | 304 | #define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ |
253 | #define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ | 305 | #define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ |
254 | 306 | ||
255 | /* the following also apply to DOEPMSK */ | 307 | /* the following also apply to DOEPMSK */ |
256 | #define USB_DOEPINT_xfercompl (1 << 0) /** Transfer complete */ | 308 | #define DOEPINT_xfercompl (1 << 0) /** Transfer complete */ |
257 | #define USB_DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ | 309 | #define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ |
258 | #define USB_DOEPINT_ahberr (1 << 2) /** AHB error */ | 310 | #define DOEPINT_ahberr (1 << 2) /** AHB error */ |
259 | #define USB_DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ | 311 | #define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ |
260 | 312 | ||
261 | /* 0<=ep<=15, you can use ep=0 */ | 313 | /* 0<=ep<=15, you can use ep=0 */ |
262 | /** Device OUT Endpoint (ep) Control Register */ | 314 | /** Device OUT Endpoint (ep) Control Register */ |
263 | #define USB_DOEPCTL(ep) USB_DEV_REG(0x300 + (ep) * 0x20) | 315 | #define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20) |
264 | /** Device OUT Endpoint (ep) Frame number Register */ | 316 | /** Device OUT Endpoint (ep) Frame number Register */ |
265 | #define USB_DOEPFN(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x4) | 317 | #define DOEPFN(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x4) |
266 | /** Device Endpoint (ep) Interrupt Register */ | 318 | /** Device Endpoint (ep) Interrupt Register */ |
267 | #define USB_DOEPINT(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x8) | 319 | #define DOEPINT(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x8) |
268 | /** Device OUT Endpoint (ep) Transfer Size Register */ | 320 | /** Device OUT Endpoint (ep) Transfer Size Register */ |
269 | #define USB_DOEPTSIZ(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x10) | 321 | #define DOEPTSIZ(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x10) |
270 | /** Device Endpoint (ep) DMA Address Register */ | 322 | /** Device Endpoint (ep) DMA Address Register */ |
271 | #define USB_DOEPDMA(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x14) | 323 | #define DOEPDMA(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x14) |
272 | 324 | ||
273 | #define USB_PCGCCTL USB_BASE_REG(0xE00) /** Power and Clock Gating Control Register */ | 325 | #define PCGCCTL BASE_REG(0xE00) /** Power and Clock Gating Control Register */ |
274 | 326 | ||
275 | 327 | ||
276 | /** Maximum Packet Size | 328 | /** Maximum Packet Size |
@@ -280,18 +332,18 @@ | |||
280 | * 2'b01: 32 | 332 | * 2'b01: 32 |
281 | * 2'b10: 16 | 333 | * 2'b10: 16 |
282 | * 2'b11: 8 */ | 334 | * 2'b11: 8 */ |
283 | #define USB_DEPCTL_mps_bits 0x7ff | 335 | #define DEPCTL_mps_bits 0x7ff |
284 | #define USB_DEPCTL_mps_bit_pos 0 | 336 | #define DEPCTL_mps_bit_pos 0 |
285 | #define USB_DEPCTL_MPS_64 0 | 337 | #define DEPCTL_MPS_64 0 |
286 | #define USB_DEPCTL_MPS_32 1 | 338 | #define DEPCTL_MPS_32 1 |
287 | #define USB_DEPCTL_MPS_16 2 | 339 | #define DEPCTL_MPS_16 2 |
288 | #define USB_DEPCTL_MPS_8 3 | 340 | #define DEPCTL_MPS_8 3 |
289 | /** Next Endpoint | 341 | /** Next Endpoint |
290 | * IN EPn/IN EP0 | 342 | * IN EPn/IN EP0 |
291 | * OUT EPn/OUT EP0 - reserved */ | 343 | * OUT EPn/OUT EP0 - reserved */ |
292 | #define USB_DEPCTL_nextep_bit_pos 11 | 344 | #define DEPCTL_nextep_bit_pos 11 |
293 | #define USB_DEPCTL_nextep_bits (0xf << USB_DEPCTL_nextep_bit_pos) | 345 | #define DEPCTL_nextep_bits (0xf << DEPCTL_nextep_bit_pos) |
294 | #define USB_DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ | 346 | #define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ |
295 | /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) | 347 | /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) |
296 | * This field contains the PID of the packet going to | 348 | * This field contains the PID of the packet going to |
297 | * be received or transmitted on this endpoint. The | 349 | * be received or transmitted on this endpoint. The |
@@ -306,28 +358,28 @@ | |||
306 | * - 0: D0 | 358 | * - 0: D0 |
307 | * - 1: D1 | 359 | * - 1: D1 |
308 | */ | 360 | */ |
309 | #define USB_DEPCTL_dpid (1 << 16) | 361 | #define DEPCTL_dpid (1 << 16) |
310 | #define USB_DEPCTL_naksts (1 << 17) /** NAK Status */ | 362 | #define DEPCTL_naksts (1 << 17) /** NAK Status */ |
311 | /** Endpoint Type | 363 | /** Endpoint Type |
312 | * 2'b00: Control | 364 | * 2'b00: Control |
313 | * 2'b01: Isochronous | 365 | * 2'b01: Isochronous |
314 | * 2'b10: Bulk | 366 | * 2'b10: Bulk |
315 | * 2'b11: Interrupt */ | 367 | * 2'b11: Interrupt */ |
316 | #define USB_DEPCTL_eptype_bit_pos 18 | 368 | #define DEPCTL_eptype_bit_pos 18 |
317 | #define USB_DEPCTL_eptype_bits (0x3 << USB_DEPCTL_eptype_bit_pos) | 369 | #define DEPCTL_eptype_bits (0x3 << DEPCTL_eptype_bit_pos) |
318 | /** Snoop Mode | 370 | /** Snoop Mode |
319 | * OUT EPn/OUT EP0 | 371 | * OUT EPn/OUT EP0 |
320 | * IN EPn/IN EP0 - reserved */ | 372 | * IN EPn/IN EP0 - reserved */ |
321 | #define USB_DEPCTL_snp (1 << 20) | 373 | #define DEPCTL_snp (1 << 20) |
322 | #define USB_DEPCTL_stall (1 << 21) /** Stall Handshake */ | 374 | #define DEPCTL_stall (1 << 21) /** Stall Handshake */ |
323 | /** Tx Fifo Number | 375 | /** Tx Fifo Number |
324 | * IN EPn/IN EP0 | 376 | * IN EPn/IN EP0 |
325 | * OUT EPn/OUT EP0 - reserved */ | 377 | * OUT EPn/OUT EP0 - reserved */ |
326 | #define USB_DEPCTL_txfnum_bit_pos 22 | 378 | #define DEPCTL_txfnum_bit_pos 22 |
327 | #define USB_DEPCTL_txfnum_bits (0xf << USB_DEPCTL_txfnum_bit_pos) | 379 | #define DEPCTL_txfnum_bits (0xf << DEPCTL_txfnum_bit_pos) |
328 | 380 | ||
329 | #define USB_DEPCTL_cnak (1 << 26) /** Clear NAK */ | 381 | #define DEPCTL_cnak (1 << 26) /** Clear NAK */ |
330 | #define USB_DEPCTL_snak (1 << 27) /** Set NAK */ | 382 | #define DEPCTL_snak (1 << 27) /** Set NAK */ |
331 | /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) | 383 | /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) |
332 | * Writing to this field sets the Endpoint DPID (DPID) | 384 | * Writing to this field sets the Endpoint DPID (DPID) |
333 | * field in this register to DATA0. Set Even | 385 | * field in this register to DATA0. Set Even |
@@ -336,7 +388,7 @@ | |||
336 | * (micro)frame (EO_FrNum) field to even (micro) | 388 | * (micro)frame (EO_FrNum) field to even (micro) |
337 | * frame. | 389 | * frame. |
338 | */ | 390 | */ |
339 | #define USB_DEPCTL_setd0pid (1 << 28) | 391 | #define DEPCTL_setd0pid (1 << 28) |
340 | /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) | 392 | /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) |
341 | * Writing to this field sets the Endpoint DPID (DPID) | 393 | * Writing to this field sets the Endpoint DPID (DPID) |
342 | * field in this register to DATA1 Set Odd | 394 | * field in this register to DATA1 Set Odd |
@@ -344,52 +396,52 @@ | |||
344 | * Writing to this field sets the Even/Odd | 396 | * Writing to this field sets the Even/Odd |
345 | * (micro)frame (EO_FrNum) field to odd (micro) frame. | 397 | * (micro)frame (EO_FrNum) field to odd (micro) frame. |
346 | */ | 398 | */ |
347 | #define USB_DEPCTL_setd1pid (1 << 29) | 399 | #define DEPCTL_setd1pid (1 << 29) |
348 | #define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */ | 400 | #define DEPCTL_epdis (1 << 30) /** Endpoint disable */ |
349 | #define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */ | 401 | #define DEPCTL_epena (1 << 31) /** Endpoint enable */ |
350 | 402 | ||
351 | 403 | ||
352 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ | 404 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ |
353 | #define USB_DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */ | 405 | #define DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */ |
354 | #define USB_DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */ | 406 | #define DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */ |
355 | #define USB_DEPTSIZ_pkcnt_bits (0x3ff << USB_DEPTSIZ_pkcnt_bit_pos) | 407 | #define DEPTSIZ_pkcnt_bits (0x3ff << DEPTSIZ_pkcnt_bit_pos) |
356 | #define USB_DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */ | 408 | #define DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */ |
357 | #define USB_DEPTSIZ_mc_bits (0x3 << USB_DEPTSIZ_mc_bit_pos) | 409 | #define DEPTSIZ_mc_bits (0x3 << DEPTSIZ_mc_bit_pos) |
358 | 410 | ||
359 | /* idem but for i=0 */ | 411 | /* idem but for i=0 */ |
360 | #define USB_DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */ | 412 | #define DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */ |
361 | #define USB_DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */ | 413 | #define DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */ |
362 | #define USB_DEPTSIZ0_pkcnt_bits (0x1 << USB_DEPTSIZ0_pkcnt_bit_pos) | 414 | #define DEPTSIZ0_pkcnt_bits (0x1 << DEPTSIZ0_pkcnt_bit_pos) |
363 | #define USB_DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ | 415 | #define DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ |
364 | #define USB_DEPTSIZ0_supcnt_bits (0x3 << USB_DEPTSIZ0_supcnt_bit_pos) | 416 | #define DEPTSIZ0_supcnt_bits (0x3 << DEPTSIZ0_supcnt_bit_pos) |
365 | 417 | ||
366 | /* valid for USB_DAINT and USB_DAINTMSK, for 0<=ep<=15 */ | 418 | /* valid for DAINT and DAINTMSK, for 0<=ep<=15 */ |
367 | #define USB_DAINT_IN_EP(i) (1 << (i)) | 419 | #define DAINT_IN_EP(i) (1 << (i)) |
368 | #define USB_DAINT_OUT_EP(i) (1 << ((i) + 16)) | 420 | #define DAINT_OUT_EP(i) (1 << ((i) + 16)) |
369 | 421 | ||
370 | /** | 422 | /** |
371 | * Parameters | 423 | * Parameters |
372 | */ | 424 | */ |
373 | #define USB_USE_CUSTOM_FIFO_LAYOUT | 425 | #define USE_CUSTOM_FIFO_LAYOUT |
374 | 426 | ||
375 | #ifdef USB_USE_CUSTOM_FIFO_LAYOUT | 427 | #ifdef USE_CUSTOM_FIFO_LAYOUT |
376 | /* Data fifo: includes RX fifo, non period TX fifo and periodic fifos | 428 | /* Data fifo: includes RX fifo, non period TX fifo and periodic fifos |
377 | * NOTE: this is a hardware parameter, it cannot be changed ! */ | 429 | * NOTE: this is a hardware parameter, it cannot be changed ! */ |
378 | #define USB_DATA_FIFO_DEPTH 0x535 | 430 | #define DATA_FIFO_DEPTH 0x535 |
379 | /* size of the FX fifo */ | 431 | /* size of the FX fifo */ |
380 | #define USB_RX_FIFO_SIZE 0x100 | 432 | #define RX_FIFO_SIZE 0x100 |
381 | /* size of the non periodic TX fifo */ | 433 | /* size of the non periodic TX fifo */ |
382 | #define USB_NPTX_FIFO_SIZE 0x100 | 434 | #define NPTX_FIFO_SIZE 0x100 |
383 | /* size of each TX ep fifo size */ | 435 | /* size of each TX ep fifo size */ |
384 | #define USB_EPTX_FIFO_SIZE 0x100 | 436 | #define EPTX_FIFO_SIZE 0x100 |
385 | #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ | 437 | #endif /* USE_CUSTOM_FIFO_LAYOUT */ |
386 | 438 | ||
387 | /* Number of IN/OUT endpoints */ | 439 | /* Number of IN/OUT endpoints */ |
388 | #define USB_NUM_IN_EP 3 | 440 | #define NUM_IN_EP 3 |
389 | #define USB_NUM_OUT_EP 2 | 441 | #define NUM_OUT_EP 2 |
390 | 442 | ||
391 | /* List of IN enpoints */ | 443 | /* List of IN enpoints */ |
392 | #define USB_IN_EP_LIST 1, 3, 5 | 444 | #define IN_EP_LIST 1, 3, 5 |
393 | #define USB_OUT_EP_LIST 2, 4 | 445 | #define OUT_EP_LIST 2, 4 |
394 | 446 | ||
395 | #endif /* __USB_DRV_AS3525v2_H__ */ | 447 | #endif /* __USB_DRV_AS3525v2_H__ */ |