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path: root/firmware/target/arm/as3525/usb-drv-as3525v2.c
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Diffstat (limited to 'firmware/target/arm/as3525/usb-drv-as3525v2.c')
-rw-r--r--firmware/target/arm/as3525/usb-drv-as3525v2.c358
1 files changed, 180 insertions, 178 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.c b/firmware/target/arm/as3525/usb-drv-as3525v2.c
index 0149cac653..951e0b0687 100644
--- a/firmware/target/arm/as3525/usb-drv-as3525v2.c
+++ b/firmware/target/arm/as3525/usb-drv-as3525v2.c
@@ -36,16 +36,16 @@
36#include "usb-drv-as3525v2.h" 36#include "usb-drv-as3525v2.h"
37#include "usb_core.h" 37#include "usb_core.h"
38 38
39static int __in_ep_list[USB_NUM_IN_EP] = {USB_IN_EP_LIST}; 39static int __in_ep_list[NUM_IN_EP] = {IN_EP_LIST};
40static int __out_ep_list[USB_NUM_OUT_EP] = {USB_OUT_EP_LIST}; 40static int __out_ep_list[NUM_OUT_EP] = {OUT_EP_LIST};
41 41
42/* iterate through each in/out ep except EP0 42/* iterate through each in/out ep except EP0
43 * 'counter' is the counter, 'ep' is the actual value */ 43 * 'counter' is the counter, 'ep' is the actual value */
44#define FOR_EACH_IN_EP(counter, ep) \ 44#define FOR_EACH_IN_EP(counter, ep) \
45 for(counter = 0, ep = __in_ep_list[0]; counter < USB_NUM_IN_EP; counter++, ep = __in_ep_list[counter]) 45 for(counter = 0, ep = __in_ep_list[0]; counter < NUM_IN_EP; counter++, ep = __in_ep_list[counter])
46 46
47#define FOR_EACH_OUT_EP(counter, ep) \ 47#define FOR_EACH_OUT_EP(counter, ep) \
48 for(counter = 0, ep = __out_ep_list[0]; counter < USB_NUM_OUT_EP; counter++, ep = __out_ep_list[counter]) 48 for(counter = 0, ep = __out_ep_list[0]; counter < NUM_OUT_EP; counter++, ep = __out_ep_list[counter])
49 49
50struct usb_endpoint 50struct usb_endpoint
51{ 51{
@@ -91,29 +91,29 @@ static void as3525v2_connect(void)
91 CGU_USB |= 0x20; 91 CGU_USB |= 0x20;
92 usb_delay(); 92 usb_delay();
93 /* 3) clear "stop pclk" */ 93 /* 3) clear "stop pclk" */
94 USB_PCGCCTL &= ~0x1; 94 PCGCCTL &= ~0x1;
95 usb_delay(); 95 usb_delay();
96 /* 4) clear "power clamp" */ 96 /* 4) clear "power clamp" */
97 USB_PCGCCTL &= ~0x4; 97 PCGCCTL &= ~0x4;
98 usb_delay(); 98 usb_delay();
99 /* 5) clear "reset power down module" */ 99 /* 5) clear "reset power down module" */
100 USB_PCGCCTL &= ~0x8; 100 PCGCCTL &= ~0x8;
101 usb_delay(); 101 usb_delay();
102 /* 6) set "power on program done" */ 102 /* 6) set "power on program done" */
103 USB_DCTL |= USB_DCTL_pwronprgdone; 103 DCTL |= DCTL_pwronprgdone;
104 usb_delay(); 104 usb_delay();
105 /* 7) core soft reset */ 105 /* 7) core soft reset */
106 USB_GRSTCTL |= USB_GRSTCTL_csftrst; 106 GRSTCTL |= GRSTCTL_csftrst;
107 usb_delay(); 107 usb_delay();
108 /* 8) hclk soft reset */ 108 /* 8) hclk soft reset */
109 USB_GRSTCTL |= USB_GRSTCTL_hsftrst; 109 GRSTCTL |= GRSTCTL_hsftrst;
110 usb_delay(); 110 usb_delay();
111 /* 9) flush and reset everything */ 111 /* 9) flush and reset everything */
112 USB_GRSTCTL |= 0x3f; 112 GRSTCTL |= 0x3f;
113 usb_delay(); 113 usb_delay();
114 /* 10) force device mode*/ 114 /* 10) force device mode*/
115 USB_GUSBCFG &= ~USB_GUSBCFG_force_host_mode; 115 GUSBCFG &= ~GUSBCFG_force_host_mode;
116 USB_GUSBCFG |= USB_GUSBCFG_force_device_mode; 116 GUSBCFG |= GUSBCFG_force_device_mode;
117 usb_delay(); 117 usb_delay();
118 /* 11) Do something that is probably CCU related but undocumented*/ 118 /* 11) Do something that is probably CCU related but undocumented*/
119 CCU_USB_THINGY &= ~0x1000; 119 CCU_USB_THINGY &= ~0x1000;
@@ -121,48 +121,48 @@ static void as3525v2_connect(void)
121 CCU_USB_THINGY &= ~0x300000; 121 CCU_USB_THINGY &= ~0x300000;
122 usb_delay(); 122 usb_delay();
123 /* 12) reset usb core parameters (dev addr, speed, ...) */ 123 /* 12) reset usb core parameters (dev addr, speed, ...) */
124 USB_DCFG = 0; 124 DCFG = 0;
125 usb_delay(); 125 usb_delay();
126} 126}
127 127
128static void usb_enable_device_interrupts(void) 128static void enable_device_interrupts(void)
129{ 129{
130 /* Clear any pending interrupt */ 130 /* Clear any pending interrupt */
131 USB_GINTSTS = 0xffffffff; 131 GINTSTS = 0xffffffff;
132 /* Clear any pending otg interrupt */ 132 /* Clear any pending otg interrupt */
133 USB_GOTGINT = 0xffffffff; 133 GOTGINT = 0xffffffff;
134 /* Enable interrupts */ 134 /* Enable interrupts */
135 USB_GINTMSK = USB_GINTMSK_usbreset 135 GINTMSK = GINTMSK_usbreset
136 | USB_GINTMSK_enumdone 136 | GINTMSK_enumdone
137 | USB_GINTMSK_inepintr 137 | GINTMSK_inepintr
138 | USB_GINTMSK_outepintr 138 | GINTMSK_outepintr
139 | USB_GINTMSK_otgintr 139 | GINTMSK_otgintr
140 | USB_GINTMSK_disconnect; 140 | GINTMSK_disconnect;
141} 141}
142 142
143static void usb_flush_tx_fifos(int nums) 143static void flush_tx_fifos(int nums)
144{ 144{
145 unsigned int i = 0; 145 unsigned int i = 0;
146 146
147 USB_GRSTCTL = (USB_GRSTCTL & (~USB_GRSTCTL_txfnum_bits)) 147 GRSTCTL = (GRSTCTL & (~GRSTCTL_txfnum_bits))
148 | (nums << USB_GRSTCTL_txfnum_bit_pos) 148 | (nums << GRSTCTL_txfnum_bit_pos)
149 | USB_GRSTCTL_txfflsh_flush; 149 | GRSTCTL_txfflsh_flush;
150 while(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush && i < 0x300) 150 while(GRSTCTL & GRSTCTL_txfflsh_flush && i < 0x300)
151 i++; 151 i++;
152 if(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush) 152 if(GRSTCTL & GRSTCTL_txfflsh_flush)
153 panicf("usb: hang of flush tx fifos (%x)", nums); 153 panicf("usb: hang of flush tx fifos (%x)", nums);
154 /* wait 3 phy clocks */ 154 /* wait 3 phy clocks */
155 udelay(1); 155 udelay(1);
156} 156}
157 157
158static void usb_flush_rx_fifo(void) 158static void flush_rx_fifo(void)
159{ 159{
160 unsigned int i = 0; 160 unsigned int i = 0;
161 161
162 USB_GRSTCTL = USB_GRSTCTL_rxfflsh_flush; 162 GRSTCTL = GRSTCTL_rxfflsh_flush;
163 while(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush && i < 0x300) 163 while(GRSTCTL & GRSTCTL_rxfflsh_flush && i < 0x300)
164 i++; 164 i++;
165 if(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush) 165 if(GRSTCTL & GRSTCTL_rxfflsh_flush)
166 panicf("usb: hang of flush rx fifo"); 166 panicf("usb: hang of flush rx fifo");
167 /* wait 3 phy clocks */ 167 /* wait 3 phy clocks */
168 udelay(1); 168 udelay(1);
@@ -172,15 +172,15 @@ static void core_reset(void)
172{ 172{
173 unsigned int i = 0; 173 unsigned int i = 0;
174 /* Wait for AHB master IDLE state. */ 174 /* Wait for AHB master IDLE state. */
175 while((USB_GRSTCTL & USB_GRSTCTL_ahbidle) == 0) 175 while((GRSTCTL & GRSTCTL_ahbidle) == 0)
176 udelay(10); 176 udelay(10);
177 /* Core Soft Reset */ 177 /* Core Soft Reset */
178 USB_GRSTCTL |= USB_GRSTCTL_csftrst; 178 GRSTCTL |= GRSTCTL_csftrst;
179 /* Waits for the hardware to clear reset bit */ 179 /* Waits for the hardware to clear reset bit */
180 while(USB_GRSTCTL & USB_GRSTCTL_csftrst && i < 0x300) 180 while(GRSTCTL & GRSTCTL_csftrst && i < 0x300)
181 i++; 181 i++;
182 182
183 if(USB_GRSTCTL & USB_GRSTCTL_csftrst) 183 if(GRSTCTL & GRSTCTL_csftrst)
184 panicf("oops, usb core soft reset hang :("); 184 panicf("oops, usb core soft reset hang :(");
185 185
186 /* Wait for 3 PHY Clocks */ 186 /* Wait for 3 PHY Clocks */
@@ -192,16 +192,16 @@ static void reset_endpoints(void)
192 int i, ep; 192 int i, ep;
193 /* disable all endpoints except EP0 */ 193 /* disable all endpoints except EP0 */
194 FOR_EACH_IN_EP(i, ep) 194 FOR_EACH_IN_EP(i, ep)
195 if(USB_DIEPCTL(ep) & USB_DEPCTL_epena) 195 if(DIEPCTL(ep) & DEPCTL_epena)
196 USB_DIEPCTL(ep) = USB_DEPCTL_epdis | USB_DEPCTL_snak; 196 DIEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak;
197 else 197 else
198 USB_DIEPCTL(ep) = 0; 198 DIEPCTL(ep) = 0;
199 199
200 FOR_EACH_OUT_EP(i, ep) 200 FOR_EACH_OUT_EP(i, ep)
201 if(USB_DOEPCTL(ep) & USB_DEPCTL_epena) 201 if(DOEPCTL(ep) & DEPCTL_epena)
202 USB_DOEPCTL(ep) = USB_DEPCTL_epdis | USB_DEPCTL_snak; 202 DOEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak;
203 else 203 else
204 USB_DOEPCTL(ep) = 0; 204 DOEPCTL(ep) = 0;
205 /* Setup EP0 OUT with the following parameters: 205 /* Setup EP0 OUT with the following parameters:
206 * packet count = 1 206 * packet count = 1
207 * setup packet count = 1 207 * setup packet count = 1
@@ -209,88 +209,90 @@ static void reset_endpoints(void)
209 * Setup EP0 IN/OUT with 64 byte maximum packet size and activate both. Enable transfer on EP0 OUT 209 * Setup EP0 IN/OUT with 64 byte maximum packet size and activate both. Enable transfer on EP0 OUT
210 */ 210 */
211 211
212 USB_DOEPTSIZ(0) = (1 << USB_DEPTSIZ0_supcnt_bit_pos) 212 DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bit_pos)
213 | (1 << USB_DEPTSIZ0_pkcnt_bit_pos) 213 | (1 << DEPTSIZ0_pkcnt_bit_pos)
214 | 8; 214 | 8;
215 215
216 /* setup DMA */ 216 /* setup DMA */
217 clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ 217 clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */
218 USB_DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */ 218 DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */
219 219
220 /* Enable endpoint, clear nak */ 220 /* Enable endpoint, clear nak */
221 USB_DOEPCTL(0) = USB_DEPCTL_epena | USB_DEPCTL_cnak | USB_DEPCTL_usbactep 221 DOEPCTL(0) = DEPCTL_epena | DEPCTL_cnak | DEPCTL_usbactep
222 | (USB_DEPCTL_MPS_8 << USB_DEPCTL_mps_bit_pos); 222 | (DEPCTL_MPS_8 << DEPCTL_mps_bit_pos);
223 223
224 /* 64 bytes packet size, active endpoint */ 224 /* 64 bytes packet size, active endpoint */
225 USB_DIEPCTL(0) = (USB_DEPCTL_MPS_8 << USB_DEPCTL_mps_bit_pos) 225 DIEPCTL(0) = (DEPCTL_MPS_8 << DEPCTL_mps_bit_pos)
226 | USB_DEPCTL_usbactep; 226 | DEPCTL_usbactep;
227 227
228 USB_DCTL = USB_DCTL_cgnpinnak | USB_DCTL_cgoutnak; 228 DCTL = DCTL_cgnpinnak | DCTL_cgoutnak;
229} 229}
230 230
231static void core_dev_init(void) 231static void core_dev_init(void)
232{ 232{
233 unsigned int usb_num_in_ep = 0; 233 unsigned int num_in_ep = 0;
234 unsigned int usb_num_out_ep = 0; 234 unsigned int num_out_ep = 0;
235 unsigned int i; 235 unsigned int i;
236 /* Restart the phy clock */ 236 /* Restart the phy clock */
237 USB_PCGCCTL = 0; 237 PCGCCTL = 0;
238 /* Set phy speed : high speed */ 238 /* Set phy speed : high speed */
239 USB_DCFG = (USB_DCFG & ~USB_DCFG_devspd_bits) | USB_DCFG_devspd_hs_phy_hs; 239 DCFG = (DCFG & ~DCFG_devspd_bits) | DCFG_devspd_hs_phy_hs;
240 240
241 /* Check hardware capabilities */ 241 /* Check hardware capabilities */
242 if(USB_GHWCFG2_ARCH != USB_INT_DMA_ARCH) 242 if(extract(GHWCFG2, ARCH) != INT_DMA_ARCH)
243 panicf("usb: wrong architecture (%ld)", USB_GHWCFG2_ARCH); 243 panicf("usb: wrong architecture (%ld)", extract(GHWCFG2, ARCH));
244 if(USB_GHWCFG2_HS_PHY_TYPE != USB_PHY_TYPE_UTMI) 244 if(extract(GHWCFG2, HS_PHY_TYPE) != PHY_TYPE_UTMI)
245 panicf("usb: wrong HS phy type (%ld)", USB_GHWCFG2_HS_PHY_TYPE); 245 panicf("usb: wrong HS phy type (%ld)", extract(GHWCFG2, HS_PHY_TYPE));
246 if(USB_GHWCFG2_FS_PHY_TYPE != USB_PHY_TYPE_UNSUPPORTED) 246 if(extract(GHWCFG2, FS_PHY_TYPE) != PHY_TYPE_UNSUPPORTED)
247 panicf("usb: wrong FS phy type (%ld)", USB_GHWCFG2_FS_PHY_TYPE); 247 panicf("usb: wrong FS phy type (%ld)", extract(GHWCFG2, FS_PHY_TYPE));
248 if(USB_GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2) 248 if(GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2)
249 panicf("usb: wrong utmi data width (%ld)", USB_GHWCFG4_UTMI_PHY_DATA_WIDTH); 249 panicf("usb: wrong utmi data width (%ld)", GHWCFG4_UTMI_PHY_DATA_WIDTH);
250 if(USB_GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */ 250 if(GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */
251 panicf("usb: no multiple tx fifo"); 251 panicf("usb: no multiple tx fifo");
252 252
253 #ifdef USB_USE_CUSTOM_FIFO_LAYOUT 253 #ifdef USE_CUSTOM_FIFO_LAYOUT
254 if(USB_GHWCFG2_DYN_FIFO != 1) 254 if(!(GHWCFG2 & GHWCFG2_DYN_FIFO))
255 panicf("usb: no dynamic fifo"); 255 panicf("usb: no dynamic fifo");
256 if(USB_GRXFSIZ != USB_DATA_FIFO_DEPTH) 256 if(GRXFSIZ != DATA_FIFO_DEPTH)
257 panicf("usb: wrong data fifo size"); 257 panicf("usb: wrong data fifo size");
258 #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ 258 #endif /* USE_CUSTOM_FIFO_LAYOUT */
259 259
260 /* do some logging */ 260 /* do some logging */
261 logf("hwcfg1: %08lx", USB_GHWCFG1); 261 logf("hwcfg1: %08lx", GHWCFG1);
262 logf("hwcfg2: %08lx", USB_GHWCFG2); 262 logf("hwcfg2: %08lx", GHWCFG2);
263 logf("hwcfg3: %08lx", USB_GHWCFG3); 263 logf("hwcfg3: %08lx", GHWCFG3);
264 logf("hwcfg4: %08lx", USB_GHWCFG4); 264 logf("hwcfg4: %08lx", GHWCFG4);
265 265
266 logf("%ld endpoints", USB_GHWCFG2_NUM_EP); 266 logf("%ld endpoints", extract(GHWCFG2, NUM_EP));
267 usb_num_in_ep = 0; 267 num_in_ep = 0;
268 usb_num_out_ep = 0; 268 num_out_ep = 0;
269 for(i = 0; i < USB_GHWCFG2_NUM_EP; i++) 269 for(i = 0; i < extract(GHWCFG2, NUM_EP); i++)
270 { 270 {
271 if(USB_GHWCFG1_IN_EP(i)) 271 if(GHWCFG1 & GHWCFG1_IN_EP(i))
272 usb_num_in_ep++; 272 num_in_ep++;
273 if(USB_GHWCFG1_OUT_EP(i)) 273 if(GHWCFG1 & GHWCFG1_OUT_EP(i))
274 usb_num_out_ep++; 274 num_out_ep++;
275 logf(" EP%d: IN=%ld OUT=%ld", i, USB_GHWCFG1_IN_EP(i), USB_GHWCFG1_OUT_EP(i)); 275 logf(" EP%d: IN=%s OUT=%s", i,
276 GHWCFG1 & GHWCFG1_IN_EP(i) ? "yes" : "no",
277 GHWCFG1 & GHWCFG1_OUT_EP(i) ? "yes" : "no");
276 } 278 }
277 279
278 if(usb_num_in_ep != USB_GHWCFG4_NUM_IN_EP) 280 if(num_in_ep != GHWCFG4_NUM_IN_EP)
279 panicf("usb: num in ep mismatch(%d,%lu)", usb_num_in_ep, USB_GHWCFG4_NUM_IN_EP); 281 panicf("usb: num in ep mismatch(%d,%lu)", num_in_ep, GHWCFG4_NUM_IN_EP);
280 if(usb_num_in_ep != USB_NUM_IN_EP) 282 if(num_in_ep != NUM_IN_EP)
281 panicf("usb: num in ep static mismatch(%u,%u)", usb_num_in_ep, USB_NUM_IN_EP); 283 panicf("usb: num in ep static mismatch(%u,%u)", num_in_ep, NUM_IN_EP);
282 if(usb_num_out_ep != USB_NUM_OUT_EP) 284 if(num_out_ep != NUM_OUT_EP)
283 panicf("usb: num out ep static mismatch(%u,%u)", usb_num_out_ep, USB_NUM_OUT_EP); 285 panicf("usb: num out ep static mismatch(%u,%u)", num_out_ep, NUM_OUT_EP);
284 286
285 logf("%d in ep, %d out ep", usb_num_in_ep, usb_num_out_ep); 287 logf("%d in ep, %d out ep", num_in_ep, num_out_ep);
286 288
287 logf("initial:"); 289 logf("initial:");
288 logf(" tot fifo sz: %lx", USB_GHWCFG3_DFIFO_LEN); 290 logf(" tot fifo sz: %lx", GHWCFG3_DFIFO_LEN);
289 logf(" rx fifo: [%04x,+%4lx]", 0, USB_GRXFSIZ); 291 logf(" rx fifo: [%04x,+%4lx]", 0, GRXFSIZ);
290 logf(" nptx fifo: [%04lx,+%4lx]", USB_GET_FIFOSIZE_START_ADR(USB_GNPTXFSIZ), 292 logf(" nptx fifo: [%04lx,+%4lx]", GET_FIFOSIZE_START_ADR(GNPTXFSIZ),
291 USB_GET_FIFOSIZE_DEPTH(USB_GNPTXFSIZ)); 293 GET_FIFOSIZE_DEPTH(GNPTXFSIZ));
292 294
293 #ifdef USB_USE_CUSTOM_FIFO_LAYOUT 295 #ifdef USE_CUSTOM_FIFO_LAYOUT
294 /* Setup FIFOs */ 296 /* Setup FIFOs */
295 /* Organize FIFO as follow: 297 /* Organize FIFO as follow:
296 * 0 -> rxfsize : RX fifo 298 * 0 -> rxfsize : RX fifo
@@ -301,38 +303,38 @@ static void core_dev_init(void)
301 */ 303 */
302 304
303 unsigned short adr = 0; 305 unsigned short adr = 0;
304 unsigned short depth = USB_RX_FIFO_SIZE; 306 unsigned short depth = RX_FIFO_SIZE;
305 USB_GRXFSIZ = depth; 307 GRXFSIZ = depth;
306 adr += depth; 308 adr += depth;
307 depth = USB_NPTX_FIFO_SIZE; 309 depth = NPTX_FIFO_SIZE;
308 USB_GNPTXFSIZ = USB_MAKE_FIFOSIZE_DATA(adr, depth); 310 GNPTXFSIZ = MAKE_FIFOSIZE_DATA(adr, depth);
309 adr += depth; 311 adr += depth;
310 312
311 for(i = 1; i <= USB_NUM_IN_EP; i++) 313 for(i = 1; i <= NUM_IN_EP; i++)
312 { 314 {
313 depth = USB_EPTX_FIFO_SIZE; 315 depth = EPTX_FIFO_SIZE;
314 USB_DIEPTXFSIZ(i) = USB_MAKE_FIFOSIZE_DATA(adr, depth); 316 DIEPTXFSIZ(i) = MAKE_FIFOSIZE_DATA(adr, depth);
315 adr += depth; 317 adr += depth;
316 } 318 }
317 319
318 if(adr > USB_DATA_FIFO_DEPTH) 320 if(adr > DATA_FIFO_DEPTH)
319 panicf("usb: total data fifo size exceeded"); 321 panicf("usb: total data fifo size exceeded");
320 #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ 322 #endif /* USE_CUSTOM_FIFO_LAYOUT */
321 323
322 for(i = 1; i <= USB_NUM_IN_EP; i++) 324 for(i = 1; i <= NUM_IN_EP; i++)
323 { 325 {
324 logf(" dieptx fifo(%2u): [%04lx,+%4lx]", i, 326 logf(" dieptx fifo(%2u): [%04lx,+%4lx]", i,
325 USB_GET_FIFOSIZE_START_ADR(USB_DIEPTXFSIZ(i)), 327 GET_FIFOSIZE_START_ADR(DIEPTXFSIZ(i)),
326 USB_GET_FIFOSIZE_DEPTH(USB_DIEPTXFSIZ(i))); 328 GET_FIFOSIZE_DEPTH(DIEPTXFSIZ(i)));
327 } 329 }
328 330
329 /* Setup interrupt masks for endpoints */ 331 /* Setup interrupt masks for endpoints */
330 /* Setup interrupt masks */ 332 /* Setup interrupt masks */
331 USB_DOEPMSK = USB_DOEPINT_setup | USB_DOEPINT_xfercompl | USB_DOEPINT_ahberr 333 DOEPMSK = DOEPINT_setup | DOEPINT_xfercompl | DOEPINT_ahberr
332 | USB_DOEPINT_epdisabled; 334 | DOEPINT_epdisabled;
333 USB_DIEPMSK = USB_DIEPINT_xfercompl | USB_DIEPINT_timeout 335 DIEPMSK = DIEPINT_xfercompl | DIEPINT_timeout
334 | USB_DIEPINT_epdisabled | USB_DIEPINT_ahberr; 336 | DIEPINT_epdisabled | DIEPINT_ahberr;
335 USB_DAINTMSK = 0xffffffff; 337 DAINTMSK = 0xffffffff;
336 338
337 reset_endpoints(); 339 reset_endpoints();
338 340
@@ -340,50 +342,50 @@ static void core_dev_init(void)
340 /* only dump them for now, leave threshold disabled */ 342 /* only dump them for now, leave threshold disabled */
341 /* 343 /*
342 logf("threshold control:"); 344 logf("threshold control:");
343 logf(" non_iso_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_non_iso_thr_en) ? 1 : 0); 345 logf(" non_iso_thr_en: %d", (DTHRCTL & DTHRCTL_non_iso_thr_en) ? 1 : 0);
344 logf(" iso_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_iso_thr_en) ? 1 : 0); 346 logf(" iso_thr_en: %d", (DTHRCTL & DTHRCTL_iso_thr_en) ? 1 : 0);
345 logf(" tx_thr_len: %lu", (USB_DTHRCTL & USB_DTHRCTL_tx_thr_len_bits) >> USB_DTHRCTL_tx_thr_len_bit_pos); 347 logf(" tx_thr_len: %lu", (DTHRCTL & DTHRCTL_tx_thr_len_bits) >> DTHRCTL_tx_thr_len_bit_pos);
346 logf(" rx_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_rx_thr_en) ? 1 : 0); 348 logf(" rx_thr_en: %d", (DTHRCTL & DTHRCTL_rx_thr_en) ? 1 : 0);
347 logf(" rx_thr_len: %lu", (USB_DTHRCTL & USB_DTHRCTL_rx_thr_len_bits) >> USB_DTHRCTL_rx_thr_len_bit_pos); 349 logf(" rx_thr_len: %lu", (DTHRCTL & DTHRCTL_rx_thr_len_bits) >> DTHRCTL_rx_thr_len_bit_pos);
348 */ 350 */
349 351
350 USB_DTHRCTL = 0; 352 DTHRCTL = 0;
351 353
352 /* enable USB interrupts */ 354 /* enable USB interrupts */
353 usb_enable_device_interrupts(); 355 enable_device_interrupts();
354} 356}
355 357
356static void core_init(void) 358static void core_init(void)
357{ 359{
358 /* Disconnect */ 360 /* Disconnect */
359 USB_DCTL |= USB_DCTL_sftdiscon; 361 DCTL |= DCTL_sftdiscon;
360 /* Select UTMI+ 16 */ 362 /* Select UTMI+ 16 */
361 USB_GUSBCFG |= USB_GUSBCFG_phy_if; 363 GUSBCFG |= GUSBCFG_phy_if;
362 364
363 /* fixme: the current code is for internal DMA only, the clip+ architecture 365 /* fixme: the current code is for internal DMA only, the clip+ architecture
364 * define the internal DMA model */ 366 * define the internal DMA model */
365 /* Set burstlen and enable DMA*/ 367 /* Set burstlen and enable DMA*/
366 USB_GAHBCFG = (USB_GAHBCFG_INT_DMA_BURST_INCR4 << USB_GAHBCFG_hburstlen_bit_pos) 368 GAHBCFG = (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bit_pos)
367 | USB_GAHBCFG_dma_enable; 369 | GAHBCFG_dma_enable;
368 /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */ 370 /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */
369 USB_GUSBCFG &= ~(USB_GUSBCFG_srpcap | USB_GUSBCFG_hnpcapp); 371 GUSBCFG &= ~(GUSBCFG_srpcap | GUSBCFG_hnpcapp);
370 372
371 /* perform device model specific init */ 373 /* perform device model specific init */
372 core_dev_init(); 374 core_dev_init();
373 375
374 /* Reconnect */ 376 /* Reconnect */
375 USB_DCTL &= ~USB_DCTL_sftdiscon; 377 DCTL &= ~DCTL_sftdiscon;
376} 378}
377 379
378static void usb_enable_global_interrupts(void) 380static void enable_global_interrupts(void)
379{ 381{
380 VIC_INT_ENABLE = INTERRUPT_USB; 382 VIC_INT_ENABLE = INTERRUPT_USB;
381 USB_GAHBCFG |= USB_GAHBCFG_glblintrmsk; 383 GAHBCFG |= GAHBCFG_glblintrmsk;
382} 384}
383 385
384static void usb_disable_global_interrupts(void) 386static void disable_global_interrupts(void)
385{ 387{
386 USB_GAHBCFG &= ~USB_GAHBCFG_glblintrmsk; 388 GAHBCFG &= ~GAHBCFG_glblintrmsk;
387 VIC_INT_EN_CLEAR = INTERRUPT_USB; 389 VIC_INT_EN_CLEAR = INTERRUPT_USB;
388} 390}
389 391
@@ -392,11 +394,11 @@ void usb_drv_init(void)
392 logf("usb_drv_init"); 394 logf("usb_drv_init");
393 /* Enable PHY and clocks (but leave pullups disabled) */ 395 /* Enable PHY and clocks (but leave pullups disabled) */
394 as3525v2_connect(); 396 as3525v2_connect();
395 logf("usb: synopsis id: %lx", USB_GSNPSID); 397 logf("usb: synopsis id: %lx", GSNPSID);
396 /* Core init */ 398 /* Core init */
397 core_init(); 399 core_init();
398 /* Enable global interrupts */ 400 /* Enable global interrupts */
399 usb_enable_global_interrupts(); 401 enable_global_interrupts();
400} 402}
401 403
402void usb_drv_exit(void) 404void usb_drv_exit(void)
@@ -404,23 +406,23 @@ void usb_drv_exit(void)
404 logf("usb_drv_exit"); 406 logf("usb_drv_exit");
405} 407}
406 408
407static bool handle_usb_reset(void) 409static bool handle_reset(void)
408{ 410{
409 logf("usb: bus reset"); 411 logf("usb: bus reset");
410 412
411 /* Clear the Remote Wakeup Signalling */ 413 /* Clear the Remote Wakeup Signalling */
412 USB_DCTL &= ~USB_DCTL_rmtwkupsig; 414 DCTL &= ~DCTL_rmtwkupsig;
413 415
414 /* Flush FIFOs */ 416 /* Flush FIFOs */
415 usb_flush_tx_fifos(0x10); 417 flush_tx_fifos(0x10);
416 418
417 /* Flush the Learning Queue */ 419 /* Flush the Learning Queue */
418 USB_GRSTCTL = USB_GRSTCTL_intknqflsh; 420 GRSTCTL = GRSTCTL_intknqflsh;
419 421
420 reset_endpoints(); 422 reset_endpoints();
421 423
422 /* Reset Device Address */ 424 /* Reset Device Address */
423 USB_DCFG &= ~USB_DCFG_devadr_bits; 425 DCFG &= ~DCFG_devadr_bits;
424 426
425 usb_core_bus_reset(); 427 usb_core_bus_reset();
426 428
@@ -432,51 +434,51 @@ static bool handle_enum_done(void)
432 logf("usb: enum done"); 434 logf("usb: enum done");
433 435
434 /* read speed */ 436 /* read speed */
435 logf("DSTS: %lx", USB_DSTS); 437 logf("DSTS: %lx", DSTS);
436 logf("DOEPCTL0=%lx", USB_DOEPCTL(0)); 438 logf("DOEPCTL0=%lx", DOEPCTL(0));
437 logf("DOEPTSIZ=%lx", USB_DOEPTSIZ(0)); 439 logf("DOEPTSIZ=%lx", DOEPTSIZ(0));
438 logf("DIEPCTL0=%lx", USB_DIEPCTL(0)); 440 logf("DIEPCTL0=%lx", DIEPCTL(0));
439 logf("DOEPMSK=%lx", USB_DOEPMSK); 441 logf("DOEPMSK=%lx", DOEPMSK);
440 logf("DIEPMSK=%lx", USB_DIEPMSK); 442 logf("DIEPMSK=%lx", DIEPMSK);
441 logf("DAINTMSK=%lx", USB_DAINTMSK); 443 logf("DAINTMSK=%lx", DAINTMSK);
442 logf("DAINT=%lx", USB_DAINT); 444 logf("DAINT=%lx", DAINT);
443 logf("GINTSTS=%lx", USB_GINTSTS); 445 logf("GINTSTS=%lx", GINTSTS);
444 logf("GINTMSK=%lx", USB_GINTMSK); 446 logf("GINTMSK=%lx", GINTMSK);
445 logf("DCTL=%lx", USB_DCTL); 447 logf("DCTL=%lx", DCTL);
446 logf("GAHBCFG=%lx", USB_GAHBCFG); 448 logf("GAHBCFG=%lx", GAHBCFG);
447 logf("GUSBCFG=%lx", USB_GUSBCFG); 449 logf("GUSBCFG=%lx", GUSBCFG);
448 logf("DCFG=%lx", USB_DCFG); 450 logf("DCFG=%lx", DCFG);
449 logf("DTHRCTL=%lx", USB_DTHRCTL); 451 logf("DTHRCTL=%lx", DTHRCTL);
450 452
451 switch((USB_DSTS & USB_DSTS_enumspd_bits) >> USB_DSTS_enumspd_bit_pos) 453 switch((DSTS & DSTS_enumspd_bits) >> DSTS_enumspd_bit_pos)
452 { 454 {
453 case USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: 455 case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
454 logf("usb: HS"); 456 logf("usb: HS");
455 break; 457 break;
456 case USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: 458 case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
457 case USB_DSTS_ENUMSPD_FS_PHY_48MHZ: 459 case DSTS_ENUMSPD_FS_PHY_48MHZ:
458 logf("usb: FS"); 460 logf("usb: FS");
459 break; 461 break;
460 case USB_DSTS_ENUMSPD_LS_PHY_6MHZ: 462 case DSTS_ENUMSPD_LS_PHY_6MHZ:
461 panicf("usb: LS is not supported"); 463 panicf("usb: LS is not supported");
462 } 464 }
463 465
464 USB_DOEPCTL(0) = (USB_DOEPCTL(0) & ~USB_DEPCTL_mps_bits) 466 DOEPCTL(0) = (DOEPCTL(0) & ~DEPCTL_mps_bits)
465 | (USB_DEPCTL_MPS_64 << USB_DEPCTL_mps_bit_pos); 467 | (DEPCTL_MPS_64 << DEPCTL_mps_bit_pos);
466 USB_DIEPCTL(0) = (USB_DIEPCTL(0) & ~USB_DEPCTL_mps_bits) 468 DIEPCTL(0) = (DIEPCTL(0) & ~DEPCTL_mps_bits)
467 | (USB_DEPCTL_MPS_64 << USB_DEPCTL_mps_bit_pos); 469 | (DEPCTL_MPS_64 << DEPCTL_mps_bit_pos);
468 470
469 unsigned i, ep; 471 unsigned i, ep;
470 FOR_EACH_IN_EP(i, ep) 472 FOR_EACH_IN_EP(i, ep)
471 USB_DIEPCTL(ep) = (USB_DIEPCTL(ep) & ~USB_DEPCTL_mps_bits) 473 DIEPCTL(ep) = (DIEPCTL(ep) & ~DEPCTL_mps_bits)
472 | (512 << USB_DEPCTL_mps_bit_pos); 474 | (512 << DEPCTL_mps_bit_pos);
473 475
474 FOR_EACH_OUT_EP(i, ep) 476 FOR_EACH_OUT_EP(i, ep)
475 USB_DOEPCTL(ep) = (USB_DOEPCTL(ep) & ~USB_DEPCTL_mps_bits) 477 DOEPCTL(ep) = (DOEPCTL(ep) & ~DEPCTL_mps_bits)
476 | (512 << USB_DEPCTL_mps_bit_pos); 478 | (512 << DEPCTL_mps_bit_pos);
477 479
478 USB_DOEPTSIZ(0) = (1 << USB_DEPTSIZ0_supcnt_bit_pos) 480 DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bit_pos)
479 | (1 << USB_DEPTSIZ0_pkcnt_bit_pos) 481 | (1 << DEPTSIZ0_pkcnt_bit_pos)
480 | 64; 482 | 64;
481 483
482 return true; 484 return true;
@@ -499,7 +501,7 @@ static void dump_intsts(char *buffer, size_t size, unsigned long sts)
499 (void) size; 501 (void) size;
500 buffer[0] = 0; 502 buffer[0] = 0;
501 #define DUMP_CASE(name) \ 503 #define DUMP_CASE(name) \
502 if(sts & USB_GINTMSK_##name) strcat(buffer, #name " "); 504 if(sts & GINTMSK_##name) strcat(buffer, #name " ");
503 505
504 DUMP_CASE(modemismatch) 506 DUMP_CASE(modemismatch)
505 DUMP_CASE(otgintr) 507 DUMP_CASE(otgintr)
@@ -536,7 +538,7 @@ void INT_USB(void)
536{ 538{
537 /* some bits in GINTSTS can be set even though we didn't enable the interrupt source 539 /* some bits in GINTSTS can be set even though we didn't enable the interrupt source
538 * so AND it with the actual mask */ 540 * so AND it with the actual mask */
539 unsigned long sts = USB_GINTSTS & USB_GINTMSK; 541 unsigned long sts = GINTSTS & GINTMSK;
540 unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */ 542 unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */
541 543
542 #define HANDLED_CASE(bitmask, callfn) \ 544 #define HANDLED_CASE(bitmask, callfn) \
@@ -553,25 +555,25 @@ void INT_USB(void)
553 goto Lunhandled; 555 goto Lunhandled;
554 556
555 /* device part */ 557 /* device part */
556 HANDLED_CASE(USB_GINTMSK_usbreset, handle_usb_reset) 558 HANDLED_CASE(GINTMSK_usbreset, handle_reset)
557 HANDLED_CASE(USB_GINTMSK_enumdone, handle_enum_done) 559 HANDLED_CASE(GINTMSK_enumdone, handle_enum_done)
558 /* 560 /*
559 HANDLED_CASE(USB_GINTMSK_inepintr, handle_in_ep_int) 561 HANDLED_CASE(GINTMSK_inepintr, handle_in_ep_int)
560 HANDLED_CASE(USB_GINTMSK_outepintr, handle_out_ep_int) 562 HANDLED_CASE(GINTMSK_outepintr, handle_out_ep_int)
561 */ 563 */
562 UNHANDLED_CASE(USB_GINTMSK_outepintr) 564 UNHANDLED_CASE(GINTMSK_outepintr)
563 UNHANDLED_CASE(USB_GINTMSK_inepintr) 565 UNHANDLED_CASE(GINTMSK_inepintr)
564 566
565 /* common part */ 567 /* common part */
566 UNHANDLED_CASE(USB_GINTMSK_otgintr) 568 UNHANDLED_CASE(GINTMSK_otgintr)
567 UNHANDLED_CASE(USB_GINTMSK_conidstschng) 569 UNHANDLED_CASE(GINTMSK_conidstschng)
568 UNHANDLED_CASE(USB_GINTMSK_disconnect) 570 UNHANDLED_CASE(GINTMSK_disconnect)
569 571
570 /* unlisted ones */ 572 /* unlisted ones */
571 if(sts & ~handled_one) 573 if(sts & ~handled_one)
572 goto Lunhandled; 574 goto Lunhandled;
573 575
574 USB_GINTSTS = USB_GINTSTS; 576 GINTSTS = GINTSTS;
575 577
576 return; 578 return;
577 579