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authorRafaël Carré <rafael.carre@gmail.com>2009-06-29 14:29:02 +0000
committerRafaël Carré <rafael.carre@gmail.com>2009-06-29 14:29:02 +0000
commit15a7f5e5e9495667e204cde8852b33587427911f (patch)
treebbb3f4f926b3bab2f91b2b07ac23f3634ff12e5e
parente0640c3c4b6d238e38155c863e542335ce57a425 (diff)
downloadrockbox-15a7f5e5e9495667e204cde8852b33587427911f.tar.gz
rockbox-15a7f5e5e9495667e204cde8852b33587427911f.zip
Move PNX0101 timer code in the target tree
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21554 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/SOURCES1
-rw-r--r--firmware/export/timer.h4
-rw-r--r--firmware/target/arm/pnx0101/timer-pnx0101.c82
-rw-r--r--firmware/target/arm/pnx0101/timer-target.h39
-rw-r--r--firmware/timer.c51
5 files changed, 125 insertions, 52 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 11f09e7062..8e3f1ea549 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -367,6 +367,7 @@ target/arm/s5l8700/i2c-s5l8700.c
367#if CONFIG_CPU == PNX0101 367#if CONFIG_CPU == PNX0101
368target/arm/pnx0101/kernel-pnx0101.c 368target/arm/pnx0101/kernel-pnx0101.c
369target/arm/pnx0101/system-pnx0101.c 369target/arm/pnx0101/system-pnx0101.c
370target/arm/pnx0101/timer-pnx0101.c
370#endif 371#endif
371 372
372#if CONFIG_CPU == AS3525 373#if CONFIG_CPU == AS3525
diff --git a/firmware/export/timer.h b/firmware/export/timer.h
index 27a8ace409..e36baa1e1f 100644
--- a/firmware/export/timer.h
+++ b/firmware/export/timer.h
@@ -31,11 +31,9 @@
31#elif defined(CPU_COLDFIRE) 31#elif defined(CPU_COLDFIRE)
32 /* timer is based on busclk == cpuclk/2 */ 32 /* timer is based on busclk == cpuclk/2 */
33 #define TIMER_FREQ (CPU_FREQ/2) 33 #define TIMER_FREQ (CPU_FREQ/2)
34#elif CONFIG_CPU == PNX0101
35 #define TIMER_FREQ 3000000
36#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320 || CONFIG_CPU == TCC7801 \ 34#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320 || CONFIG_CPU == TCC7801 \
37 || defined(CPU_TCC77X) || CONFIG_CPU == AS3525 || CONFIG_CPU == IMX31L \ 35 || defined(CPU_TCC77X) || CONFIG_CPU == AS3525 || CONFIG_CPU == IMX31L \
38 || CONFIG_CPU == JZ4732 36 || CONFIG_CPU == JZ4732 || CONFIG_CPU == PNX0101
39 #include "timer-target.h" 37 #include "timer-target.h"
40#elif defined(SIMULATOR) 38#elif defined(SIMULATOR)
41 #define TIMER_FREQ 1000000 39 #define TIMER_FREQ 1000000
diff --git a/firmware/target/arm/pnx0101/timer-pnx0101.c b/firmware/target/arm/pnx0101/timer-pnx0101.c
new file mode 100644
index 0000000000..6e685aa20f
--- /dev/null
+++ b/firmware/target/arm/pnx0101/timer-pnx0101.c
@@ -0,0 +1,82 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id$
9*
10* Copyright (C) 2007 Tomasz Malesinski
11*
12* This program is free software; you can redistribute it and/or
13* modify it under the terms of the GNU General Public License
14* as published by the Free Software Foundation; either version 2
15* of the License, or (at your option) any later version.
16*
17* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18* KIND, either express or implied.
19*
20****************************************************************************/
21
22#include "timer-target.h"
23#include "system.h"
24#include "timer.h"
25
26static long cycles_new = 0;
27
28void TIMER1_ISR(void)
29{
30 if (cycles_new > 0)
31 {
32 TIMER1.load = cycles_new - 1;
33 cycles_new = 0;
34 }
35 if (pfn_timer != NULL)
36 {
37 cycles_new = -1;
38 /* "lock" the variable, in case timer_set_period()
39 * is called within pfn_timer() */
40 pfn_timer();
41 cycles_new = 0;
42 }
43 TIMER1.clr = 1; /* clear the interrupt */
44}
45
46bool __timer_set(long cycles, bool start)
47{
48 if (start)
49 {
50 if (pfn_unregister != NULL)
51 {
52 pfn_unregister();
53 pfn_unregister = NULL;
54 }
55 TIMER1.ctrl &= ~0x80; /* disable the counter */
56 TIMER1.ctrl |= 0x40; /* reload after counting down to zero */
57 TIMER1.ctrl &= ~0xc; /* no prescaler */
58 TIMER1.clr = 1; /* clear an interrupt event */
59 }
60 if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
61 { /* enable timer */
62 TIMER1.load = cycles - 1;
63 TIMER1.ctrl |= 0x80; /* enable the counter */
64 }
65 else
66 cycles_new = cycles;
67
68 return true;
69}
70
71bool __timer_start(void)
72{
73 irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
74 irq_enable_int(IRQ_TIMER1);
75 return true;
76}
77
78void __timer_stop(void)
79{
80 TIMER1.ctrl &= ~0x80; /* disable timer 1 */
81 irq_disable_int(IRQ_TIMER1);
82}
diff --git a/firmware/target/arm/pnx0101/timer-target.h b/firmware/target/arm/pnx0101/timer-target.h
new file mode 100644
index 0000000000..853da07838
--- /dev/null
+++ b/firmware/target/arm/pnx0101/timer-target.h
@@ -0,0 +1,39 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id$
9*
10* Copyright (C) 2007 Tomasz Malesinski
11*
12* This program is free software; you can redistribute it and/or
13* modify it under the terms of the GNU General Public License
14* as published by the Free Software Foundation; either version 2
15* of the License, or (at your option) any later version.
16*
17* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18* KIND, either express or implied.
19*
20****************************************************************************/
21#ifndef TIMER_TARGET_H
22#define TIMER_TARGET_H
23
24bool __timer_set(long cycles, bool start);
25bool __timer_start(void);
26void __timer_stop(void);
27
28#define TIMER_FREQ 3000000
29
30#define __TIMER_SET(cycles, set) \
31 __timer_set(cycles, set)
32
33#define __TIMER_START() \
34 __timer_start()
35
36#define __TIMER_STOP(...) \
37 __timer_stop()
38
39#endif /* TIMER_TARGET_H */
diff --git a/firmware/timer.c b/firmware/timer.c
index e5a60902b6..089deffbd4 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -31,7 +31,7 @@ void SHAREDBSS_ATTR (*pfn_timer)(void) = NULL; /* timer callback */
31void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */ 31void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
32#ifdef CPU_COLDFIRE 32#ifdef CPU_COLDFIRE
33static int base_prescale; 33static int base_prescale;
34#elif defined CPU_PP || CONFIG_CPU == PNX0101 34#elif defined CPU_PP
35static long SHAREDBSS_ATTR cycles_new = 0; 35static long SHAREDBSS_ATTR cycles_new = 0;
36#endif 36#endif
37 37
@@ -78,24 +78,6 @@ void TIMER2(void)
78 cycles_new = 0; 78 cycles_new = 0;
79 } 79 }
80} 80}
81#elif CONFIG_CPU == PNX0101
82void TIMER1_ISR(void)
83{
84 if (cycles_new > 0)
85 {
86 TIMER1.load = cycles_new - 1;
87 cycles_new = 0;
88 }
89 if (pfn_timer != NULL)
90 {
91 cycles_new = -1;
92 /* "lock" the variable, in case timer_set_period()
93 * is called within pfn_timer() */
94 pfn_timer();
95 cycles_new = 0;
96 }
97 TIMER1.clr = 1; /* clear the interrupt */
98}
99#endif /* CONFIG_CPU */ 81#endif /* CONFIG_CPU */
100 82
101static bool timer_set(long cycles, bool start) 83static bool timer_set(long cycles, bool start)
@@ -114,29 +96,7 @@ static bool timer_set(long cycles, bool start)
114 } 96 }
115#endif 97#endif
116 98
117#if CONFIG_CPU == PNX0101 99#if CONFIG_CPU == SH7034
118 if (start)
119 {
120 if (pfn_unregister != NULL)
121 {
122 pfn_unregister();
123 pfn_unregister = NULL;
124 }
125 TIMER1.ctrl &= ~0x80; /* disable the counter */
126 TIMER1.ctrl |= 0x40; /* reload after counting down to zero */
127 TIMER1.ctrl &= ~0xc; /* no prescaler */
128 TIMER1.clr = 1; /* clear an interrupt event */
129 }
130 if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
131 { /* enable timer */
132 TIMER1.load = cycles - 1;
133 TIMER1.ctrl |= 0x80; /* enable the counter */
134 }
135 else
136 cycles_new = cycles;
137
138 return true;
139#elif CONFIG_CPU == SH7034
140 if (prescale > 8) 100 if (prescale > 8)
141 return false; 101 return false;
142 102
@@ -282,10 +242,6 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
282#endif 242#endif
283 CPU_INT_EN = TIMER2_MASK; 243 CPU_INT_EN = TIMER2_MASK;
284 return true; 244 return true;
285#elif CONFIG_CPU == PNX0101
286 irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
287 irq_enable_int(IRQ_TIMER1);
288 return true;
289#else 245#else
290 return __TIMER_START(); 246 return __TIMER_START();
291#endif 247#endif
@@ -315,9 +271,6 @@ void timer_unregister(void)
315 TIMER2_CFG = 0; /* stop timer 2 */ 271 TIMER2_CFG = 0; /* stop timer 2 */
316 CPU_INT_DIS = TIMER2_MASK; 272 CPU_INT_DIS = TIMER2_MASK;
317 COP_INT_DIS = TIMER2_MASK; 273 COP_INT_DIS = TIMER2_MASK;
318#elif CONFIG_CPU == PNX0101
319 TIMER1.ctrl &= ~0x80; /* disable timer 1 */
320 irq_disable_int(IRQ_TIMER1);
321#else 274#else
322 __TIMER_STOP(); 275 __TIMER_STOP();
323#endif 276#endif