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Diffstat (limited to 'firmware/timer.c')
-rw-r--r--firmware/timer.c51
1 files changed, 2 insertions, 49 deletions
diff --git a/firmware/timer.c b/firmware/timer.c
index e5a60902b6..089deffbd4 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -31,7 +31,7 @@ void SHAREDBSS_ATTR (*pfn_timer)(void) = NULL; /* timer callback */
31void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */ 31void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
32#ifdef CPU_COLDFIRE 32#ifdef CPU_COLDFIRE
33static int base_prescale; 33static int base_prescale;
34#elif defined CPU_PP || CONFIG_CPU == PNX0101 34#elif defined CPU_PP
35static long SHAREDBSS_ATTR cycles_new = 0; 35static long SHAREDBSS_ATTR cycles_new = 0;
36#endif 36#endif
37 37
@@ -78,24 +78,6 @@ void TIMER2(void)
78 cycles_new = 0; 78 cycles_new = 0;
79 } 79 }
80} 80}
81#elif CONFIG_CPU == PNX0101
82void TIMER1_ISR(void)
83{
84 if (cycles_new > 0)
85 {
86 TIMER1.load = cycles_new - 1;
87 cycles_new = 0;
88 }
89 if (pfn_timer != NULL)
90 {
91 cycles_new = -1;
92 /* "lock" the variable, in case timer_set_period()
93 * is called within pfn_timer() */
94 pfn_timer();
95 cycles_new = 0;
96 }
97 TIMER1.clr = 1; /* clear the interrupt */
98}
99#endif /* CONFIG_CPU */ 81#endif /* CONFIG_CPU */
100 82
101static bool timer_set(long cycles, bool start) 83static bool timer_set(long cycles, bool start)
@@ -114,29 +96,7 @@ static bool timer_set(long cycles, bool start)
114 } 96 }
115#endif 97#endif
116 98
117#if CONFIG_CPU == PNX0101 99#if CONFIG_CPU == SH7034
118 if (start)
119 {
120 if (pfn_unregister != NULL)
121 {
122 pfn_unregister();
123 pfn_unregister = NULL;
124 }
125 TIMER1.ctrl &= ~0x80; /* disable the counter */
126 TIMER1.ctrl |= 0x40; /* reload after counting down to zero */
127 TIMER1.ctrl &= ~0xc; /* no prescaler */
128 TIMER1.clr = 1; /* clear an interrupt event */
129 }
130 if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
131 { /* enable timer */
132 TIMER1.load = cycles - 1;
133 TIMER1.ctrl |= 0x80; /* enable the counter */
134 }
135 else
136 cycles_new = cycles;
137
138 return true;
139#elif CONFIG_CPU == SH7034
140 if (prescale > 8) 100 if (prescale > 8)
141 return false; 101 return false;
142 102
@@ -282,10 +242,6 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
282#endif 242#endif
283 CPU_INT_EN = TIMER2_MASK; 243 CPU_INT_EN = TIMER2_MASK;
284 return true; 244 return true;
285#elif CONFIG_CPU == PNX0101
286 irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
287 irq_enable_int(IRQ_TIMER1);
288 return true;
289#else 245#else
290 return __TIMER_START(); 246 return __TIMER_START();
291#endif 247#endif
@@ -315,9 +271,6 @@ void timer_unregister(void)
315 TIMER2_CFG = 0; /* stop timer 2 */ 271 TIMER2_CFG = 0; /* stop timer 2 */
316 CPU_INT_DIS = TIMER2_MASK; 272 CPU_INT_DIS = TIMER2_MASK;
317 COP_INT_DIS = TIMER2_MASK; 273 COP_INT_DIS = TIMER2_MASK;
318#elif CONFIG_CPU == PNX0101
319 TIMER1.ctrl &= ~0x80; /* disable timer 1 */
320 irq_disable_int(IRQ_TIMER1);
321#else 274#else
322 __TIMER_STOP(); 275 __TIMER_STOP();
323#endif 276#endif