diff options
author | Cástor Muñoz <cmvidal@gmail.com> | 2015-12-17 02:37:18 +0100 |
---|---|---|
committer | Cástor Muñoz <cmvidal@gmail.com> | 2015-12-17 10:52:49 +0100 |
commit | 00bda90a21d2c976cabd1926c96a81ad4a319b4e (patch) | |
tree | 1fb805f7100e17413eb4928eaa11b8c486615270 | |
parent | 348bfc5c8f6633d40d3708e826aa7e9b0360729f (diff) | |
download | rockbox-00bda90a21d2c976cabd1926c96a81ad4a319b4e.tar.gz rockbox-00bda90a21d2c976cabd1926c96a81ad4a319b4e.zip |
iPod Classic: add non-cached memory region
Configures uncached memory region and adds some defines for misc HW,
for compability with the bootloader and other future use, current
functionality should not be affected.
Change-Id: I390e79bea1aef5b10dfbc72ad327d7fe438ec6f5
-rw-r--r-- | firmware/export/s5l8702.h | 45 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/crt0.S | 96 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/system-s5l8702.c | 21 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/system-target.h | 3 |
4 files changed, 97 insertions, 68 deletions
diff --git a/firmware/export/s5l8702.h b/firmware/export/s5l8702.h index 83d754d537..00d92a58b1 100644 --- a/firmware/export/s5l8702.h +++ b/firmware/export/s5l8702.h | |||
@@ -31,13 +31,13 @@ | |||
31 | #define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */ | 31 | #define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */ |
32 | 32 | ||
33 | #define DRAM_ORIG 0x08000000 | 33 | #define DRAM_ORIG 0x08000000 |
34 | #define IRAM_ORIG 0 | 34 | #define IRAM_ORIG 0x22000000 |
35 | 35 | ||
36 | #define DRAM_SIZE (MEMORYSIZE * 0x100000) | 36 | #define DRAM_SIZE (MEMORYSIZE * 0x100000) |
37 | #define IRAM_SIZE 0x40000 | 37 | #define IRAM_SIZE 0x40000 |
38 | 38 | ||
39 | #define TTB_SIZE 0x4000 | 39 | #define TTB_SIZE 0x4000 |
40 | #define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE) | 40 | #define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE) |
41 | 41 | ||
42 | #define IRAM0_ORIG 0x22000000 | 42 | #define IRAM0_ORIG 0x22000000 |
43 | #define IRAM0_SIZE 0x20000 | 43 | #define IRAM0_SIZE 0x20000 |
@@ -66,6 +66,29 @@ | |||
66 | ((i) == 2 ? 0x58 : \ | 66 | ((i) == 2 ? 0x58 : \ |
67 | ((i) == 1 ? 0x4C : \ | 67 | ((i) == 1 ? 0x4C : \ |
68 | 0x48))))))) | 68 | 0x48))))))) |
69 | /* SW Reset Control Register */ | ||
70 | #define SWRCON (*((volatile uint32_t*)(0x3C500050))) | ||
71 | /* Reset Status Register */ | ||
72 | #define RSTSR (*((volatile uint32_t*)(0x3C500054))) | ||
73 | #define RSTSR_WDR_BIT (1 << 2) | ||
74 | #define RSTSR_SWR_BIT (1 << 1) | ||
75 | #define RSTSR_HWR_BIT (1 << 0) | ||
76 | |||
77 | |||
78 | /////WATCHDOG///// | ||
79 | #define WDTCON (*((volatile uint32_t*)(0x3C800000))) | ||
80 | #define WDTCNT (*((volatile uint32_t*)(0x3C800004))) | ||
81 | |||
82 | |||
83 | /////MEMCONTROLLER///// | ||
84 | #define MIU_BASE (0x38100000) | ||
85 | #define MIU_REG(off) (*((uint32_t volatile*)(MIU_BASE + (off)))) | ||
86 | /* following registers are similar to s5l8700x */ | ||
87 | #define MIUCON (*((uint32_t volatile*)(0x38100000))) | ||
88 | #define MIUCOM (*((uint32_t volatile*)(0x38100004))) | ||
89 | #define MIUAREF (*((uint32_t volatile*)(0x38100008))) | ||
90 | #define MIUMRS (*((uint32_t volatile*)(0x3810000C))) | ||
91 | #define MIUSDPARA (*((uint32_t volatile*)(0x38100010))) | ||
69 | 92 | ||
70 | 93 | ||
71 | /////TIMER///// | 94 | /////TIMER///// |
@@ -160,10 +183,13 @@ | |||
160 | #define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \ | 183 | #define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \ |
161 | CLOCKGATE_I2C0) | 184 | CLOCKGATE_I2C0) |
162 | 185 | ||
163 | #define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus)))) | 186 | #define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus)))) |
164 | #define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus)))) | 187 | #define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus)))) |
165 | #define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus)))) | 188 | #define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus)))) |
166 | #define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus)))) | 189 | #define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus)))) |
190 | #define IICUNK10(bus) (*((uint32_t volatile*)(0x3C600010 + 0x300000 * (bus)))) | ||
191 | #define IICUNK14(bus) (*((uint32_t volatile*)(0x3C600014 + 0x300000 * (bus)))) | ||
192 | #define IICUNK18(bus) (*((uint32_t volatile*)(0x3C600018 + 0x300000 * (bus)))) | ||
167 | 193 | ||
168 | 194 | ||
169 | /////INTERRUPT CONTROLLERS///// | 195 | /////INTERRUPT CONTROLLERS///// |
@@ -344,6 +370,7 @@ | |||
344 | #define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5)))) | 370 | #define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5)))) |
345 | #define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5)))) | 371 | #define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5)))) |
346 | #define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5)))) | 372 | #define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5)))) |
373 | #define PUNC(i) (*((uint32_t volatile*)(0x3cf00010 + ((i) << 5)))) | ||
347 | #define PCON0 (*((uint32_t volatile*)(0x3cf00000))) | 374 | #define PCON0 (*((uint32_t volatile*)(0x3cf00000))) |
348 | #define PDAT0 (*((uint32_t volatile*)(0x3cf00004))) | 375 | #define PDAT0 (*((uint32_t volatile*)(0x3cf00004))) |
349 | #define PCON1 (*((uint32_t volatile*)(0x3cf00020))) | 376 | #define PCON1 (*((uint32_t volatile*)(0x3cf00020))) |
@@ -392,12 +419,12 @@ | |||
392 | #define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i)))) | 419 | #define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i)))) |
393 | #define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4))) | 420 | #define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4))) |
394 | #define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8))) | 421 | #define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8))) |
395 | #define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc))) | 422 | #define SPIPIN(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc))) |
396 | #define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10))) | 423 | #define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10))) |
397 | #define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20))) | 424 | #define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20))) |
398 | #define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30))) | 425 | #define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30))) |
399 | #define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34))) | 426 | #define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34))) |
400 | #define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38))) | 427 | #define SPIDD(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38))) /* TBC */ |
401 | 428 | ||
402 | 429 | ||
403 | /////AES///// | 430 | /////AES///// |
diff --git a/firmware/target/arm/s5l8702/crt0.S b/firmware/target/arm/s5l8702/crt0.S index 563e863a66..3d1ee2bdfd 100644 --- a/firmware/target/arm/s5l8702/crt0.S +++ b/firmware/target/arm/s5l8702/crt0.S | |||
@@ -23,9 +23,6 @@ | |||
23 | #include "config.h" | 23 | #include "config.h" |
24 | #include "cpu.h" | 24 | #include "cpu.h" |
25 | 25 | ||
26 | #define CACHE_NONE 0 | ||
27 | #define CACHE_ALL 0x0C | ||
28 | |||
29 | .section .intvect,"ax",%progbits | 26 | .section .intvect,"ax",%progbits |
30 | .global start | 27 | .global start |
31 | .global _newstart | 28 | .global _newstart |
@@ -50,65 +47,48 @@ newstart2: | |||
50 | 47 | ||
51 | #ifdef BOOTLOADER | 48 | #ifdef BOOTLOADER |
52 | /* Relocate ourself to IRAM - we have been loaded to DRAM */ | 49 | /* Relocate ourself to IRAM - we have been loaded to DRAM */ |
53 | mov r0, #0x08000000 /* source (DRAM) */ | 50 | mov r0, #0x08000000 /* source (DRAM) */ |
54 | mov r1, #0x22000000 /* dest (IRAM) */ | 51 | mov r1, #0x22000000 /* dest (IRAM) */ |
55 | ldr r2, =_dataend | 52 | ldr r2, =_dataend |
56 | 1: | 53 | 1: |
57 | cmp r2, r1 | 54 | cmp r2, r1 |
58 | ldrhi r3, [r0], #4 | 55 | ldrhi r3, [r0], #4 |
59 | strhi r3, [r1], #4 | 56 | strhi r3, [r1], #4 |
60 | bhi 1b | 57 | bhi 1b |
61 | 58 | ||
62 | ldr pc, =start_loc /* jump to the relocated start_loc: */ | 59 | ldr pc, =start_loc /* jump to the relocated start_loc: */ |
63 | start_loc: | 60 | start_loc: |
64 | #endif | 61 | #endif |
65 | 62 | ||
66 | mrc 15, 0, r0, c1, c0, 0 | 63 | mrc p15, 0, r0, c1, c0, 0 |
67 | bic r0, r0, #0x1000 | 64 | bic r0, r0, #0x1000 |
68 | bic r0, r0, #0x5 | 65 | bic r0, r0, #0x5 |
69 | mcr 15, 0, r0, c1, c0, 0 // disable caches and protection unit | 66 | mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */ |
70 | 67 | ||
71 | .cleancache: | 68 | .cleancache: |
72 | mrc p15, 0, r15,c7,c10,3 | 69 | mrc p15, 0, r15,c7,c10,3 |
73 | bne .cleancache | 70 | bne .cleancache |
74 | mov r0, #0 | 71 | mov r0, #0 |
75 | mcr p15, 0, r0,c7,c10,4 | 72 | mcr p15, 0, r0,c7,c10,4 |
76 | mcr p15, 0, r0,c7,c5,0 | 73 | mcr p15, 0, r0,c7,c5,0 |
77 | bl ttb_init | 74 | |
78 | 75 | /* reset VIC controller */ | |
79 | mov r0, #0 @ physical address | 76 | ldr r1, =0x38e00000 |
80 | mov r1, #0 @ virtual address | 77 | add r2, r1, #0x00001000 |
81 | mov r2, #0x380 @ size (all memory) | 78 | add r3, r1, #0x00002000 |
82 | mov r3, #CACHE_ALL | 79 | sub r4, r0, #1 |
83 | bl map_section | 80 | str r4, [r1,#0x14] |
84 | 81 | str r4, [r2,#0x14] | |
85 | mov r0, #0x38000000 @ physical address | 82 | str r4, [r1,#0xf00] |
86 | mov r1, #0x38000000 @ virtual address | 83 | str r4, [r2,#0xf00] |
87 | mov r2, #0x80 @ size (AHB/APB) | 84 | str r4, [r3,#0x08] |
88 | mov r3, #CACHE_NONE | 85 | str r4, [r3,#0x0c] |
89 | bl map_section | 86 | str r0, [r1,#0x14] |
90 | 87 | str r0, [r2,#0x14] | |
91 | bl enable_mmu | 88 | |
92 | |||
93 | mrc 15, 0, r0, c1, c0, 0 | ||
94 | orr r0, r0, #0x5 | ||
95 | orr r0, r0, #0x1000 | ||
96 | mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches | ||
97 | |||
98 | ldr r1, =0x38e00000 | ||
99 | add r2, r1, #0x00001000 | ||
100 | add r3, r1, #0x00002000 | ||
101 | sub r4, r0, #1 | ||
102 | str r4, [r1,#0x14] | ||
103 | str r4, [r2,#0x14] | ||
104 | str r4, [r1,#0xf00] | ||
105 | str r4, [r2,#0xf00] | ||
106 | str r4, [r3,#0x08] | ||
107 | str r4, [r3,#0x0c] | ||
108 | str r0, [r1,#0x14] | ||
109 | str r0, [r2,#0x14] | ||
110 | |||
111 | #if !defined(BOOTLOADER) | 89 | #if !defined(BOOTLOADER) |
90 | bl memory_init | ||
91 | |||
112 | /* Copy interrupt vectors to iram */ | 92 | /* Copy interrupt vectors to iram */ |
113 | ldr r2, =_intvectstart | 93 | ldr r2, =_intvectstart |
114 | ldr r3, =_intvectend | 94 | ldr r3, =_intvectend |
@@ -139,7 +119,7 @@ start_loc: | |||
139 | ldrhi r1, [r4], #4 | 119 | ldrhi r1, [r4], #4 |
140 | strhi r1, [r2], #4 | 120 | strhi r1, [r2], #4 |
141 | bhi 1b | 121 | bhi 1b |
142 | 122 | ||
143 | /* Initialise ibss section to zero */ | 123 | /* Initialise ibss section to zero */ |
144 | ldr r2, =_iedata | 124 | ldr r2, =_iedata |
145 | ldr r3, =_iend | 125 | ldr r3, =_iend |
@@ -150,11 +130,11 @@ start_loc: | |||
150 | bhi 1b | 130 | bhi 1b |
151 | #endif | 131 | #endif |
152 | 132 | ||
153 | /* Set up stack for IRQ mode */ | 133 | /* Set up stack for IRQ mode */ |
154 | msr cpsr_c, #0xd2 | 134 | msr cpsr_c, #0xd2 |
155 | ldr sp, =_irqstackend | 135 | ldr sp, =_irqstackend |
156 | 136 | ||
157 | /* Set up stack for FIQ mode */ | 137 | /* Set up stack for FIQ mode */ |
158 | msr cpsr_c, #0xd1 | 138 | msr cpsr_c, #0xd1 |
159 | ldr sp, =_fiqstackend | 139 | ldr sp, =_fiqstackend |
160 | 140 | ||
@@ -178,4 +158,4 @@ start_loc: | |||
178 | strhi r3, [r2], #4 | 158 | strhi r3, [r2], #4 |
179 | bhi 1b | 159 | bhi 1b |
180 | 160 | ||
181 | bl main | 161 | b main |
diff --git a/firmware/target/arm/s5l8702/system-s5l8702.c b/firmware/target/arm/s5l8702/system-s5l8702.c index 3e84e5cf54..6b20f44acb 100644 --- a/firmware/target/arm/s5l8702/system-s5l8702.c +++ b/firmware/target/arm/s5l8702/system-s5l8702.c | |||
@@ -168,7 +168,7 @@ void irq_handler(void) | |||
168 | irqvector[current_irq](); | 168 | irqvector[current_irq](); |
169 | VIC0ADDRESS = NULL; | 169 | VIC0ADDRESS = NULL; |
170 | VIC1ADDRESS = NULL; | 170 | VIC1ADDRESS = NULL; |
171 | 171 | ||
172 | asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */ | 172 | asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */ |
173 | "ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */ | 173 | "ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */ |
174 | "subs pc, lr, #4 \n"); /* Return from IRQ */ | 174 | "subs pc, lr, #4 \n"); /* Return from IRQ */ |
@@ -258,3 +258,22 @@ void set_cpu_frequency(long frequency) | |||
258 | cpu_frequency = frequency; | 258 | cpu_frequency = frequency; |
259 | } | 259 | } |
260 | #endif | 260 | #endif |
261 | |||
262 | static void set_page_tables(void) | ||
263 | { | ||
264 | /* map RAM to itself and enable caching for it */ | ||
265 | map_section(0, 0, 0x380, CACHE_ALL); | ||
266 | |||
267 | /* disable caching for I/O area */ | ||
268 | map_section(0x38000000, 0x38000000, 0x80, CACHE_NONE); | ||
269 | |||
270 | /* map RAM uncached addresses */ | ||
271 | map_section(0, S5L8702_UNCACHED_ADDR(0x0), 0x380, CACHE_NONE); | ||
272 | } | ||
273 | |||
274 | void memory_init(void) | ||
275 | { | ||
276 | ttb_init(); | ||
277 | set_page_tables(); | ||
278 | enable_mmu(); | ||
279 | } | ||
diff --git a/firmware/target/arm/s5l8702/system-target.h b/firmware/target/arm/s5l8702/system-target.h index 43ab28d37b..235e68e8ca 100644 --- a/firmware/target/arm/s5l8702/system-target.h +++ b/firmware/target/arm/s5l8702/system-target.h | |||
@@ -31,6 +31,9 @@ | |||
31 | 31 | ||
32 | #define STORAGE_WANTS_ALIGN | 32 | #define STORAGE_WANTS_ALIGN |
33 | 33 | ||
34 | #define S5L8702_UNCACHED_ADDR(a) ((typeof(a)) ((uintptr_t)(a) + 0x40000000)) | ||
35 | #define S5L8702_PHYSICAL_ADDR(a) ((typeof(a)) ((uintptr_t)(a))) | ||
36 | |||
34 | #define inl(a) (*(volatile unsigned long *) (a)) | 37 | #define inl(a) (*(volatile unsigned long *) (a)) |
35 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) | 38 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) |
36 | #define inb(a) (*(volatile unsigned char *) (a)) | 39 | #define inb(a) (*(volatile unsigned char *) (a)) |