1 files changed, 38 insertions, 58 deletions

diff --git a/firmware/target/arm/s5l8702/crt0.S b/firmware/target/arm/s5l8702/crt0.S
index 563e863a66..3d1ee2bdfd 100644
--- a/firmware/target/arm/s5l8702/crt0.S
+++ b/firmware/target/arm/s5l8702/crt0.S
@@ -23,9 +23,6 @@
 #include "config.h"
 #include "cpu.h"
 
-#define CACHE_NONE  0
-#define CACHE_ALL   0x0C
-
     .section .intvect,"ax",%progbits
     .global    start
     .global    _newstart
@@ -50,65 +47,48 @@ newstart2:
 
 #ifdef BOOTLOADER
     /* Relocate ourself to IRAM - we have been loaded to DRAM */
-    mov    r0, #0x08000000   /* source (DRAM) */
-    mov    r1, #0x22000000   /* dest (IRAM) */
-    ldr    r2, =_dataend
+    mov     r0, #0x08000000   /* source (DRAM) */
+    mov     r1, #0x22000000   /* dest (IRAM) */
+    ldr     r2, =_dataend
 1:
-    cmp    r2, r1
-    ldrhi  r3, [r0], #4
-    strhi  r3, [r1], #4
-    bhi    1b
+    cmp     r2, r1
+    ldrhi   r3, [r0], #4
+    strhi   r3, [r1], #4
+    bhi     1b
 
-    ldr    pc, =start_loc    /* jump to the relocated start_loc:  */
+    ldr     pc, =start_loc    /* jump to the relocated start_loc: */
 start_loc:
 #endif
 
-    mrc 15, 0, r0, c1, c0, 0
-    bic r0, r0, #0x1000
-    bic r0, r0, #0x5
-    mcr 15, 0, r0, c1, c0, 0 // disable caches and protection unit
+    mrc     p15, 0, r0, c1, c0, 0
+    bic     r0, r0, #0x1000
+    bic     r0, r0, #0x5
+    mcr     p15, 0, r0, c1, c0, 0   /* disable caches and protection unit */
 
 .cleancache:
-    mrc p15, 0, r15,c7,c10,3
-    bne .cleancache
-    mov r0, #0
-    mcr p15, 0, r0,c7,c10,4
-    mcr p15, 0, r0,c7,c5,0
-    bl      ttb_init
-
-    mov     r0, #0                          @ physical address
-    mov     r1, #0                          @ virtual address
-    mov     r2, #0x380                      @ size (all memory)
-    mov     r3, #CACHE_ALL
-    bl      map_section
-
-    mov     r0, #0x38000000                 @ physical address
-    mov     r1, #0x38000000                 @ virtual address
-    mov     r2, #0x80                       @ size (AHB/APB)
-    mov     r3, #CACHE_NONE
-    bl      map_section
-
-    bl      enable_mmu
-
-    mrc 15, 0, r0, c1, c0, 0
-    orr r0, r0, #0x5
-    orr r0, r0, #0x1000
-    mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches
-
-    ldr r1, =0x38e00000
-    add r2, r1, #0x00001000
-    add r3, r1, #0x00002000
-    sub r4, r0, #1
-    str r4, [r1,#0x14]
-    str r4, [r2,#0x14]
-    str r4, [r1,#0xf00]
-    str r4, [r2,#0xf00]
-    str r4, [r3,#0x08]
-    str r4, [r3,#0x0c]
-    str r0, [r1,#0x14]
-    str r0, [r2,#0x14]
-    
+    mrc     p15, 0, r15,c7,c10,3
+    bne     .cleancache
+    mov     r0, #0
+    mcr     p15, 0, r0,c7,c10,4
+    mcr     p15, 0, r0,c7,c5,0
+
+    /* reset VIC controller */
+    ldr     r1, =0x38e00000
+    add     r2, r1, #0x00001000
+    add     r3, r1, #0x00002000
+    sub     r4, r0, #1
+    str     r4, [r1,#0x14]
+    str     r4, [r2,#0x14]
+    str     r4, [r1,#0xf00]
+    str     r4, [r2,#0xf00]
+    str     r4, [r3,#0x08]
+    str     r4, [r3,#0x0c]
+    str     r0, [r1,#0x14]
+    str     r0, [r2,#0x14]
+
 #if !defined(BOOTLOADER)
+    bl      memory_init
+
     /* Copy interrupt vectors to iram */
     ldr     r2, =_intvectstart
     ldr     r3, =_intvectend
@@ -139,7 +119,7 @@ start_loc:
     ldrhi   r1, [r4], #4
     strhi   r1, [r2], #4
     bhi     1b
-    
+
     /* Initialise ibss section to zero */
     ldr     r2, =_iedata
     ldr     r3, =_iend
@@ -150,11 +130,11 @@ start_loc:
     bhi     1b
 #endif
 
-    /* Set up stack for IRQ mode */ 
+    /* Set up stack for IRQ mode */
     msr     cpsr_c, #0xd2
     ldr     sp, =_irqstackend
 
-    /* Set up stack for FIQ mode */ 
+    /* Set up stack for FIQ mode */
     msr     cpsr_c, #0xd1
     ldr     sp, =_fiqstackend
 
@@ -178,4 +158,4 @@ start_loc:
     strhi   r3, [r2], #4
     bhi     1b
 
-    bl      main
+    b       main