diff options
Diffstat (limited to 'utils/regtools')
-rw-r--r-- | utils/regtools/desc/regs-atj213x.xml | 163 | ||||
-rw-r--r-- | utils/regtools/qeditor/std_analysers.cpp | 229 | ||||
-rw-r--r-- | utils/regtools/qeditor/std_analysers.h | 1 |
3 files changed, 377 insertions, 16 deletions
diff --git a/utils/regtools/desc/regs-atj213x.xml b/utils/regtools/desc/regs-atj213x.xml index f43c6287bd..27b348f80d 100644 --- a/utils/regtools/desc/regs-atj213x.xml +++ b/utils/regtools/desc/regs-atj213x.xml | |||
@@ -70,41 +70,96 @@ | |||
70 | <addr name="CMU" addr="0xb0010000"/> | 70 | <addr name="CMU" addr="0xb0010000"/> |
71 | <reg name="COREPLL" desc=""> | 71 | <reg name="COREPLL" desc=""> |
72 | <addr name="COREPLL" addr="0x0"/> | 72 | <addr name="COREPLL" addr="0x0"/> |
73 | <field name="RESERVED31_11" desc="" bitrange="31:11"/> | ||
74 | <field name="CPBY" desc="Core PLL Bypass " bitrange="10:10"/> | ||
75 | <field name="CPBI" desc="Core PLL Bias " bitrange="9:8"/> | ||
76 | <field name="CPEN" desc="Core PLL Enable " bitrange="7:7"/> | ||
77 | <field name="HOEN" desc="High Oscillator Enable" bitrange="6:6"/> | ||
78 | <field name="CPCK" desc="COREPLLout = CPCK * 6 (MHz) (in range 12 - 378MHz)" bitrange="5:0"/> | ||
73 | </reg> | 79 | </reg> |
74 | <reg name="DSPPLL" desc=""> | 80 | <reg name="DSPPLL" desc=""> |
75 | <addr name="DSPPLL" addr="0x4"/> | 81 | <addr name="DSPPLL" addr="0x4"/> |
82 | <field name="RESERVED31_9" desc="" bitrange="31:9"/> | ||
83 | <field name="DPBI" desc="DSP PLL Bias" bitrange="8:7"/> | ||
84 | <field name="DPEN" desc="DSP PLL Enable" bitrange="6:6"/> | ||
85 | <field name="DPCK" desc="DSPPLLout = DPCK * 6 (MHz) (in range 12-378MHz)" bitrange="5:0"/> | ||
76 | </reg> | 86 | </reg> |
77 | <reg name="AUDIOPLL" desc=""> | 87 | <reg name="AUDIOPLL" desc=""> |
78 | <addr name="AUDIOPLL" addr="0x8"/> | 88 | <addr name="AUDIOPLL" addr="0x8"/> |
89 | <field name="RESERVED31_12" desc="" bitrange="31:12"/> | ||
90 | <field name="ADCPLL" desc="Audio PLL CLk Control" bitrange="11:11"/> | ||
91 | <field name="ADCCLK" desc="ADC Clock Divisor, output is FS*256" bitrange="10:8"/> | ||
92 | <field name="RESERVED7" desc="" bitrange="7:7"/> | ||
93 | <field name="APBI" desc="Audio PLL Bias" bitrange="6:5"/> | ||
94 | <field name="APEN" desc="Audio PLL Enable" bitrange="4:4"/> | ||
95 | <field name="DACPLL" desc="DAC PLL CLk Control" bitrange="3:3"/> | ||
96 | <field name="DACCLK" desc="DAC Clock Divisor, output is FS*256" bitrange="2:0"/> | ||
79 | </reg> | 97 | </reg> |
80 | <reg name="BUSCLK" desc=""> | 98 | <reg name="BUSCLK" desc="Bus CLK Control Register"> |
81 | <addr name="BUSCLK" addr="0xc"/> | 99 | <addr name="BUSCLK" addr="0xc"/> |
82 | </reg> | 100 | <field name="KEYE" desc="Key Wakeup Enable" bitrange="31:31"/> |
83 | <reg name="SDRCLK" desc=""> | 101 | <field name="ALME" desc="Alarm Wakeup Enable" bitrange="30:30"/> |
102 | <field name="SIRE" desc="SIRQ Wakeup Enable" bitrange="29:29"/> | ||
103 | <field name="RESERVED28" desc="" bitrange="28:28"/> | ||
104 | <field name="USBE" desc="Usb Wakeup Enable" bitrange="27:27"/> | ||
105 | <field name="RESERVED26:12" desc="" bitrange="26:12"/> | ||
106 | <field name="PCLKDIV" desc="Peripheral CLK Divisor" bitrange="11:8"/> | ||
107 | <field name="CORECLKS" desc="CPU Clock Selection" bitrange="7:6"/> | ||
108 | <field name="SCLKDIV" desc="System Clock Divisor" bitrange="5:4"/> | ||
109 | <field name="CCLKDIV" desc="CPU Clock Divisor" bitrange="3:2"/> | ||
110 | <field name="DCEN" desc="Core CLK DC Enable" bitrange="1:1"/> | ||
111 | </reg> | ||
112 | <reg name="SDRCLK" desc="SDRAM Interface CLK Control Register"> | ||
84 | <addr name="SDRCLK" addr="0x10"/> | 113 | <addr name="SDRCLK" addr="0x10"/> |
114 | <field name="RESERVED31_2" desc="" bitrange="31:2"/> | ||
115 | <field name="SDRDIV" desc="" bitrange="1:0"/> | ||
85 | </reg> | 116 | </reg> |
86 | <reg name="NANDCLK" desc=""> | 117 | <reg name="NANDCLK" desc="NAND Interface CLK Control Register"> |
87 | <addr name="NANDCLK" addr="0x18"/> | 118 | <addr name="NANDCLK" addr="0x18"/> |
119 | <field name="RESERVED31_4" desc="" bitrange="31:4"/> | ||
120 | <field name="NANDDIV" desc="" bitrange="3:0"/> | ||
88 | </reg> | 121 | </reg> |
89 | <reg name="SDCLK" desc=""> | 122 | <reg name="SDCLK" desc="SD Interface CLK Control Register "> |
90 | <addr name="SDCLK" addr="0x1c"/> | 123 | <addr name="SDCLK" addr="0x1c"/> |
124 | <field name="RESERVED31_6" desc="" bitrange="31:6"/> | ||
125 | <field name="CKEN" desc="SD Interface Clock Enable" bitrange="5:5"/> | ||
126 | <field name="D128" desc="Enable Divide 128 circuit" bitrange="4:4"/> | ||
127 | <field name="SDDIV" desc="" bitrange="3:0"/> | ||
91 | </reg> | 128 | </reg> |
92 | <reg name="MHACLK" desc=""> | 129 | <reg name="MHACLK" desc="MHA CLK Control Register"> |
93 | <addr name="MHACLK" addr="0x20"/> | 130 | <addr name="MHACLK" addr="0x20"/> |
131 | <field name="RESERVED31_4" desc="" bitrange="31:4"/> | ||
132 | <field name="MHADIV" desc="" bitrange="3:0"/> | ||
94 | </reg> | 133 | </reg> |
95 | <reg name="UART2CLK" desc=""> | 134 | <reg name="UART2CLK" desc="Uart2 CLK Control Register"> |
96 | <addr name="UART2CLK" addr="0x2c"/> | 135 | <addr name="UART2CLK" addr="0x2c"/> |
136 | <field name="RESERVED31_17" desc="" bitrange="31:17"/> | ||
137 | <field name="U2EN" desc="Uart2 Clock Enable " bitrange="16:16"/> | ||
138 | <field name="UART2DIV" desc="" bitrange="15:0"/> | ||
97 | </reg> | 139 | </reg> |
98 | <reg name="DMACLK" desc=""> | 140 | <reg name="DMACLK" desc="DMA CLK Control Register"> |
99 | <addr name="DMACLK" addr="0x30"/> | 141 | <addr name="DMACLK" addr="0x30"/> |
142 | <field name="RESERVED31_4" desc="" bitrange="31:4"/> | ||
143 | <field name="D7EN" desc="DMA 7 (Special Channel) Clock Enable" bitrange="3:3"/> | ||
144 | <field name="D6EN" desc="DMA 6 (Special Channel) Clock Enable" bitrange="2:2"/> | ||
145 | <field name="D5EN" desc="DMA 5 (Special Channel) Clock Enable" bitrange="1:1"/> | ||
146 | <field name="D4EN" desc="DMA 4 (Special Channel) Clock Enable" bitrange="0:0"/> | ||
100 | </reg> | 147 | </reg> |
101 | <reg name="FMCLK" desc=""> | 148 | <reg name="FMCLK" desc="FM CLK Control Register"> |
102 | <addr name="FMCLK" addr="0x34"/> | 149 | <addr name="FMCLK" addr="0x34"/> |
103 | </reg> | 150 | <field name="RESERVED31_6" desc="" bitrange="31:6"/> |
104 | <reg name="MCACLK" desc=""> | 151 | <field name="BCKE" desc="PWM Back Light clock Enable" bitrange="5:5"/> |
152 | <field name="BCKS" desc="Back Light CLK source select" bitrange="4:4"/> | ||
153 | <field name="BCKCON" desc="Divided PWM Back Light Special Clock Control" bitrange="3:2"/> | ||
154 | <field name="CLKS" desc="FM Clock Output Selection" bitrange="1:1"/> | ||
155 | <field name="OUTE" desc="FM Clock Output Enable (From Test Pin)" bitrange="0:0"/> | ||
156 | </reg> | ||
157 | <reg name="MCACLK" desc="MCA CLK Control Register"> | ||
105 | <addr name="MCACLK" addr="0x38"/> | 158 | <addr name="MCACLK" addr="0x38"/> |
159 | <field name="RESERVED31_4" desc="" bitrange="31:4"/> | ||
160 | <field name="MCADIV" desc="" bitrange="3:0"/> | ||
106 | </reg> | 161 | </reg> |
107 | <reg name="DEVCLKEN" desc=""> | 162 | <reg name="DEVCLKEN" desc="Device CLK Control Register"> |
108 | <addr name="DEVCLKEN" addr="0x80"/> | 163 | <addr name="DEVCLKEN" addr="0x80"/> |
109 | <field name="RESERVED31_27" desc="" bitrange="31:27"/> | 164 | <field name="RESERVED31_27" desc="" bitrange="31:27"/> |
110 | <field name="GPIO" desc="" bitrange="26:26"/> | 165 | <field name="GPIO" desc="" bitrange="26:26"/> |
@@ -133,8 +188,36 @@ | |||
133 | <field name="YUV" desc="" bitrange="1:1"/> | 188 | <field name="YUV" desc="" bitrange="1:1"/> |
134 | <field name="RESERVED0" desc="" bitrange="0:0"/> | 189 | <field name="RESERVED0" desc="" bitrange="0:0"/> |
135 | </reg> | 190 | </reg> |
136 | <reg name="DEVRST" desc=""> | 191 | <reg name="DEVRST" desc="Device Reset Control Register"> |
137 | <addr name="DEVRST" addr="0x84"/> | 192 | <addr name="DEVRST" addr="0x84"/> |
193 | <field name="RESERVED31" desc="" bitrange="31:31"/> | ||
194 | <field name="GPIO" desc="" bitrange="30:30"/> | ||
195 | <field name="KEY" desc="" bitrange="29:29"/> | ||
196 | <field name="RESERVED28" desc="" bitrange="28:28"/> | ||
197 | <field name="I2C" desc="" bitrange="27:27"/> | ||
198 | <field name="UART" desc="" bitrange="26:26"/> | ||
199 | <field name="RESERVED25_23" desc="" bitrange="25:23"/> | ||
200 | <field name="ADC" desc="" bitrange="22:22"/> | ||
201 | <field name="DAC" desc="" bitrange="21:21"/> | ||
202 | <field name="DSPC" desc="DSP control block reset" bitrange="20:20"/> | ||
203 | <field name="INTC" desc="" bitrange="19:19"/> | ||
204 | <field name="RTC" desc="" bitrange="18:18"/> | ||
205 | <field name="PMU" desc="" bitrange="17:17"/> | ||
206 | <field name="RESERVED16_14" desc="" bitrange="16:14"/> | ||
207 | <field name="DSPM" desc="SRAM DSP MEM reset" bitrange="13:13"/> | ||
208 | <field name="TVENC" desc="" bitrange="12:12"/> | ||
209 | <field name="YUV" desc="" bitrange="11:11"/> | ||
210 | <field name="MCA" desc="" bitrange="10:10"/> | ||
211 | <field name="USB" desc="" bitrange="9:9"/> | ||
212 | <field name="RESERVED8" desc="" bitrange="8:8"/> | ||
213 | <field name="MHA" desc="" bitrange="7:7"/> | ||
214 | <field name="SD" desc="" bitrange="6:6"/> | ||
215 | <field name="NAND" desc="" bitrange="5:5"/> | ||
216 | <field name="RESERVED4" desc="" bitrange="4:4"/> | ||
217 | <field name="DMAC" desc="" bitrange="3:3"/> | ||
218 | <field name="PCNT" desc="" bitrange="2:2"/> | ||
219 | <field name="RESERVED1" desc="" bitrange="1:1"/> | ||
220 | <field name="SDR" desc="SDRAM Control register and SDRAM block Reset" bitrange="0:0"/> | ||
138 | </reg> | 221 | </reg> |
139 | </dev> | 222 | </dev> |
140 | <dev name="DAC" long_name="Digital Analog Converter" desc="" version="1.0"> | 223 | <dev name="DAC" long_name="Digital Analog Converter" desc="" version="1.0"> |
@@ -369,8 +452,56 @@ | |||
369 | </reg> | 452 | </reg> |
370 | </dev> | 453 | </dev> |
371 | <dev name="I2C" long_name="" desc="" version="1.0"> | 454 | <dev name="I2C" long_name="" desc="" version="1.0"> |
372 | <addr name="I2C0" addr="0xb0180000"/> | 455 | <addr name="I2C1" addr="0xb0180000"/> |
373 | <addr name="I2C1" addr="0xb0180020"/> | 456 | <addr name="I2C2" addr="0xb0180020"/> |
457 | <reg name="CTL" desc=""> | ||
458 | <addr name="CTL" addr="0x0"/> | ||
459 | <field name="RESERVED31_9" desc="" bitrange="31:9"/> | ||
460 | <field name="PUEN" desc="nternal Pull-up Resistor (4.7k) Enable" bitrange="8:8"/> | ||
461 | <field name="EN" desc="Block enable" bitrange="7:7"/> | ||
462 | <field name="SIE" desc="START Condition Generates IRQ Enable (only for slave mode)" bitrange="6:6"/> | ||
463 | <field name="IRQE" desc="IRQ Enable" bitrange="5:5"/> | ||
464 | <field name="MS" desc="Mode select" bitrange="4:4"> | ||
465 | <value name="MASTER" value="0x0" desc=""/> | ||
466 | <value name="SLAVE" value="0x0" desc=""/> | ||
467 | </field> | ||
468 | <field name="GBCC" desc="Generating Bus Control Condition (only for master mode)" bitrange="3:2"> | ||
469 | <value name="NOP" value="0x0" desc=""/> | ||
470 | <value name="START" value="0x1" desc=""/> | ||
471 | <value name="STOP" value="0x2" desc=""/> | ||
472 | <value name="REPEATED_START" value="0x3" desc=""/> | ||
473 | </field> | ||
474 | <field name="RB" desc="Release Bus. Writing 1 to this bit will release the clock and data line to idle. MCU should write 1 to this bit after transmitting or receiving the last bit of the whole transfer. " bitrange="1:1"/> | ||
475 | <field name="GRAS" desc="Generating/Receiving Acknowledge Signal" bitrange="0:0"/> | ||
476 | </reg> | ||
477 | <reg name="CLKDIV" desc=""> | ||
478 | <addr name="CLKDIV" addr="0x4"/> | ||
479 | <field name="RESERVED31_8" desc="" bitrange="31:8"/> | ||
480 | <field name="CLKDIV" desc="Clock Divider Factor (only for master mode). I2Cx clock (SCL) can select standard (100kbps) mode and fast (400kbps) mode. Calculating SCL is as follows: SCL=PCLK/(CLKDIV*16) " bitrange="7:0"/> | ||
481 | </reg> | ||
482 | <reg name="STAT" desc=""> | ||
483 | <addr name="STAT" addr="0x8"/> | ||
484 | <field name="RESERVED31_8" desc="" bitrange="31:8"/> | ||
485 | <field name="TRC" desc="Transmit/Receive Complete Bit" bitrange="7:7"/> | ||
486 | <field name="STPD" desc="STOP Detect Bit " bitrange="6:6"/> | ||
487 | <field name="STAD" desc="START Detect Bit" bitrange="5:5"/> | ||
488 | <field name="RWST" desc="Read/Write Status Bit (only for Slave mode)" bitrange="4:4"/> | ||
489 | <field name="LBST" desc="Last Byte Status Bit" bitrange="3:3"/> | ||
490 | <field name="IRQP" desc="IRQ Pending Bit" bitrange="2:2"/> | ||
491 | <field name="OVST" desc="Overflow Status Bit" bitrange="1:1"/> | ||
492 | <field name="WCO" desc="Writing Collision Bit" bitrange="0:0"/> | ||
493 | </reg> | ||
494 | <reg name="ADDR" desc=""> | ||
495 | <addr name="ADDR" addr="0xc"/> | ||
496 | <field name="RESERVED31_8" desc="" bitrange="31:8"/> | ||
497 | <field name="SDAD" desc="Slave Device Address" bitrange="7:1"/> | ||
498 | <field name="RWCM" desc="Read/Write Control or Match" bitrange="0:0"/> | ||
499 | </reg> | ||
500 | <reg name="DAT" desc=""> | ||
501 | <addr name="DAT" addr="0x10"/> | ||
502 | <field name="RESERVED31_8" desc="" bitrange="31:8"/> | ||
503 | <field name="TXRXDAT" desc="Transmit/Receive Data" bitrange="7:0"/> | ||
504 | </reg> | ||
374 | </dev> | 505 | </dev> |
375 | <dev name="INTC" long_name="Interrupt Controller" desc="" version="1.0"> | 506 | <dev name="INTC" long_name="Interrupt Controller" desc="" version="1.0"> |
376 | <addr name="INTC" addr="0xb0020000"/> | 507 | <addr name="INTC" addr="0xb0020000"/> |
@@ -688,6 +819,8 @@ | |||
688 | </reg> | 819 | </reg> |
689 | <reg name="EN" desc=""> | 820 | <reg name="EN" desc=""> |
690 | <addr name="EN" addr="0x8"/> | 821 | <addr name="EN" addr="0x8"/> |
822 | <field name="RESERVED31_1" desc="" bitrange="31:1"/> | ||
823 | <field name="EN" desc="" bitrange="0:0"/> | ||
691 | </reg> | 824 | </reg> |
692 | <reg name="CMD" desc=""> | 825 | <reg name="CMD" desc=""> |
693 | <addr name="CMD" addr="0xc"/> | 826 | <addr name="CMD" addr="0xc"/> |
diff --git a/utils/regtools/qeditor/std_analysers.cpp b/utils/regtools/qeditor/std_analysers.cpp index 8aae007093..6dcefb344f 100644 --- a/utils/regtools/qeditor/std_analysers.cpp +++ b/utils/regtools/qeditor/std_analysers.cpp | |||
@@ -33,7 +33,7 @@ QWidget *ClockAnalyser::GetWidget() | |||
33 | 33 | ||
34 | bool ClockAnalyser::SupportSoc(const QString& soc_name) | 34 | bool ClockAnalyser::SupportSoc(const QString& soc_name) |
35 | { | 35 | { |
36 | return soc_name == "imx233" || soc_name == "rk27xx"; | 36 | return (soc_name == "imx233" || soc_name == "rk27xx" || soc_name == "atj213x"); |
37 | } | 37 | } |
38 | 38 | ||
39 | QString ClockAnalyser::GetFreq(unsigned freq) | 39 | QString ClockAnalyser::GetFreq(unsigned freq) |
@@ -84,10 +84,237 @@ void ClockAnalyser::FillTree() | |||
84 | m_tree_widget->clear(); | 84 | m_tree_widget->clear(); |
85 | if(m_soc.GetSoc().name == "imx233") FillTreeIMX233(); | 85 | if(m_soc.GetSoc().name == "imx233") FillTreeIMX233(); |
86 | else if(m_soc.GetSoc().name == "rk27xx") FillTreeRK27XX(); | 86 | else if(m_soc.GetSoc().name == "rk27xx") FillTreeRK27XX(); |
87 | else if(m_soc.GetSoc().name == "atj213x") FillTreeATJ213X(); | ||
87 | m_tree_widget->expandAll(); | 88 | m_tree_widget->expandAll(); |
88 | m_tree_widget->resizeColumnToContents(0); | 89 | m_tree_widget->resizeColumnToContents(0); |
89 | } | 90 | } |
90 | 91 | ||
92 | void ClockAnalyser::FillTreeATJ213X() | ||
93 | { | ||
94 | soc_word_t pllbypass, pllclk, en, coreclks, tmp0, tmp1, tmp2, tmp3; | ||
95 | |||
96 | BackendHelper helper(m_io_backend, m_soc); | ||
97 | |||
98 | // system oscillators 32.768k and 24M | ||
99 | QTreeWidgetItem *losc_clk = AddClock(0, "losc clk", 32768); | ||
100 | QTreeWidgetItem *hosc_clk = AddClock(0, "hosc clk", 24000000); | ||
101 | |||
102 | // core pll | ||
103 | QTreeWidgetItem *corepll = 0; | ||
104 | if (helper.ReadRegisterField("CMU", "COREPLL", "CPEN", en) && | ||
105 | helper.ReadRegisterField("CMU", "COREPLL", "CPBY", pllbypass) && | ||
106 | helper.ReadRegisterField("CMU", "COREPLL", "CPCK", pllclk)) | ||
107 | { | ||
108 | corepll = AddClock(hosc_clk, "core pll", en ? FROM_PARENT : DISABLED, | ||
109 | pllbypass ? 1 : pllclk, pllbypass ? 1 : 4); | ||
110 | } | ||
111 | else | ||
112 | { | ||
113 | corepll = AddClock(hosc_clk, "core pll", INVALID); | ||
114 | } | ||
115 | |||
116 | // dsp pll | ||
117 | QTreeWidgetItem *dsppll = 0; | ||
118 | if (helper.ReadRegisterField("CMU", "DSPPLL", "DPEN", en) && | ||
119 | helper.ReadRegisterField("CMU", "DSPPLL", "DPCK", pllclk)) | ||
120 | { | ||
121 | dsppll = AddClock(hosc_clk, "dsp pll", en ? FROM_PARENT : DISABLED, | ||
122 | pllbypass ? 1 : pllclk, pllbypass ? 1 : 4); | ||
123 | } | ||
124 | else | ||
125 | { | ||
126 | dsppll = AddClock(hosc_clk, "dsp pll", INVALID); | ||
127 | } | ||
128 | |||
129 | // audio pll | ||
130 | QTreeWidgetItem *adcpll = 0; | ||
131 | QTreeWidgetItem *dacpll = 0; | ||
132 | if (helper.ReadRegisterField("CMU", "AUDIOPLL", "APEN", en) && | ||
133 | helper.ReadRegisterField("CMU", "AUDIOPLL", "ADCCLK", tmp0) && | ||
134 | helper.ReadRegisterField("CMU", "AUDIOPLL", "DACCLK", tmp1)) | ||
135 | { | ||
136 | if (en) | ||
137 | { | ||
138 | adcpll = AddClock(hosc_clk, "audio adc pll", tmp0 ? 22579200 : 24576000); | ||
139 | dacpll = AddClock(hosc_clk, "audio dac pll", tmp1 ? 22579200 : 24576000); | ||
140 | } | ||
141 | else | ||
142 | { | ||
143 | adcpll = AddClock(hosc_clk, "audio adc pll", DISABLED); | ||
144 | dacpll = AddClock(hosc_clk, "audio dac pll", DISABLED); | ||
145 | } | ||
146 | } | ||
147 | else | ||
148 | { | ||
149 | adcpll = AddClock(hosc_clk, "audio adc pll", INVALID); | ||
150 | dacpll = AddClock(hosc_clk, "audio dac pll", INVALID); | ||
151 | } | ||
152 | |||
153 | // audio clocks | ||
154 | QTreeWidgetItem *adcclk = 0; | ||
155 | QTreeWidgetItem *dacclk = 0; | ||
156 | if (helper.ReadRegisterField("CMU", "AUDIOPLL", "ADCCLK", tmp0) && | ||
157 | helper.ReadRegisterField("CMU", "AUDIOPLL", "DACCLK", tmp1)) | ||
158 | { | ||
159 | adcclk = AddClock(adcpll, "audio adc clk", FROM_PARENT, 1, tmp0+1); | ||
160 | dacclk = AddClock(dacpll, "audio dac clk", FROM_PARENT, 1, tmp1+1); | ||
161 | } | ||
162 | else | ||
163 | { | ||
164 | adcclk = AddClock(adcpll, "audio adc clk", INVALID); | ||
165 | dacclk = AddClock(adcpll, "audio dac clk", INVALID); | ||
166 | } | ||
167 | |||
168 | // cpu clock | ||
169 | QTreeWidgetItem *cpuclk = 0; | ||
170 | if (helper.ReadRegisterField("CMU", "BUSCLK", "CORECLKS", coreclks) && | ||
171 | helper.ReadRegisterField("CMU", "BUSCLK", "CCLKDIV", tmp0)) | ||
172 | { | ||
173 | if (coreclks == 0) | ||
174 | cpuclk = AddClock(losc_clk, "cpu clk", FROM_PARENT, 1, tmp0+1); | ||
175 | else if (coreclks == 1) | ||
176 | cpuclk = AddClock(hosc_clk, "cpu clk", FROM_PARENT, 1, tmp0+1); | ||
177 | else if (coreclks == 2) | ||
178 | cpuclk = AddClock(corepll, "cpu clk", FROM_PARENT, 1, tmp0+1); | ||
179 | else | ||
180 | cpuclk = AddClock(corepll, "cpu clk", INVALID); | ||
181 | } | ||
182 | else | ||
183 | { | ||
184 | cpuclk = AddClock(corepll, "cpu clk", INVALID); | ||
185 | } | ||
186 | |||
187 | // system clock | ||
188 | QTreeWidgetItem *sysclk = 0; | ||
189 | if (helper.ReadRegisterField("CMU", "BUSCLK", "SCLKDIV", tmp0)) | ||
190 | sysclk = AddClock(cpuclk, "system clk", FROM_PARENT, 1, tmp0+1); | ||
191 | else | ||
192 | sysclk = AddClock(cpuclk, "system clk", INVALID); | ||
193 | |||
194 | // peripherial clk | ||
195 | QTreeWidgetItem *pclk = 0; | ||
196 | if (helper.ReadRegisterField("CMU", "BUSCLK", "PCLKDIV", tmp0)) | ||
197 | pclk = AddClock(sysclk, "peripherial clk", FROM_PARENT, 1, tmp0 ? tmp0+1 : 2); | ||
198 | else | ||
199 | pclk = AddClock(sysclk, "peripherial clk", INVALID); | ||
200 | |||
201 | // sdram clk | ||
202 | QTreeWidgetItem *sdrclk = 0; | ||
203 | if (helper.ReadRegisterField("CMU", "DEVCLKEN", "SDRC", en) && | ||
204 | helper.ReadRegisterField("CMU", "DEVCLKEN", "SDRM", tmp0) && | ||
205 | helper.ReadRegisterField("SDR", "EN", "EN", tmp1) && | ||
206 | helper.ReadRegisterField("CMU", "SDRCLK", "SDRDIV", tmp2)) | ||
207 | { | ||
208 | en &= tmp0 & tmp1; | ||
209 | sdrclk = AddClock(sysclk, "sdram clk", en ? FROM_PARENT: DISABLED, 1, tmp2+1); | ||
210 | } | ||
211 | else | ||
212 | sdrclk = AddClock(sysclk, "sdram clk", INVALID); | ||
213 | |||
214 | // nand clk | ||
215 | QTreeWidgetItem *nandclk = 0; | ||
216 | if (helper.ReadRegisterField("CMU", "DEVCLKEN", "NAND", en) && | ||
217 | helper.ReadRegisterField("CMU", "NANDCLK", "NANDDIV", tmp0)) | ||
218 | nandclk = AddClock(corepll, "nand clk", en ? FROM_PARENT : DISABLED, 1, tmp0+1); | ||
219 | else | ||
220 | nandclk = AddClock(corepll, "nand clk", INVALID); | ||
221 | |||
222 | // sd clk | ||
223 | QTreeWidgetItem *sdclk = 0; | ||
224 | if (helper.ReadRegisterField("CMU", "DEVCLKEN", "SD", tmp0) && | ||
225 | helper.ReadRegisterField("CMU", "SDCLK", "CKEN" , tmp1) && | ||
226 | helper.ReadRegisterField("CMU", "SDCLK", "D128" , tmp2) && | ||
227 | helper.ReadRegisterField("CMU", "SDCLK", "SDDIV" , tmp3)) | ||
228 | { | ||
229 | en = tmp0 & tmp1; | ||
230 | sdclk = AddClock(corepll, "sd clk", en ? FROM_PARENT : DISABLED, | ||
231 | 1, tmp2 ? 128*(tmp3+1) : (tmp3)); | ||
232 | } | ||
233 | else | ||
234 | sdclk = AddClock(corepll, "sd clk", INVALID); | ||
235 | |||
236 | // mha clk | ||
237 | QTreeWidgetItem *mhaclk = 0; | ||
238 | if (helper.ReadRegisterField("CMU", "DEVCLKEN", "MHA", en) && | ||
239 | helper.ReadRegisterField("CMU", "MHACLK", "MHADIV", tmp1)) | ||
240 | mhaclk = AddClock(corepll, "mha clk", en ? FROM_PARENT : DISABLED, | ||
241 | 1, tmp1+1); | ||
242 | else | ||
243 | mhaclk = AddClock(corepll, "mha clk", INVALID); | ||
244 | |||
245 | // mca clk | ||
246 | QTreeWidgetItem *mcaclk = 0; | ||
247 | if (helper.ReadRegisterField("CMU", "DEVCLKEN", "MCA", en) && | ||
248 | helper.ReadRegisterField("CMU", "MCACLK", "MCADIV", tmp1)) | ||
249 | mcaclk = AddClock(corepll, "mca clk", en ? FROM_PARENT : DISABLED, | ||
250 | 1, tmp1+1); | ||
251 | else | ||
252 | mcaclk = AddClock(corepll, "mca clk", INVALID); | ||
253 | |||
254 | // backlight pwm | ||
255 | QTreeWidgetItem *pwmclk = 0; | ||
256 | if (helper.ReadRegisterField("CMU", "FMCLK", "BCKE", en) && | ||
257 | helper.ReadRegisterField("CMU", "FMCLK", "BCKS", tmp1) && | ||
258 | helper.ReadRegisterField("CMU", "FMCLK", "BCKCON", tmp2)) | ||
259 | { | ||
260 | if (tmp1) | ||
261 | { | ||
262 | // HOSC/8 input clk | ||
263 | pwmclk = AddClock(hosc_clk, "pwm clk", en ? FROM_PARENT : DISABLED, | ||
264 | 1, 3*(tmp2+1)); | ||
265 | } | ||
266 | else | ||
267 | { | ||
268 | // LOSC input clk | ||
269 | pwmclk = AddClock(losc_clk, "pwm clk", en ? FROM_PARENT : DISABLED, | ||
270 | 1, tmp2+1); | ||
271 | } | ||
272 | } | ||
273 | else | ||
274 | pwmclk = AddClock(losc_clk, "pwm clk", INVALID); | ||
275 | |||
276 | // i2c clk | ||
277 | QTreeWidgetItem *i2c1clk = 0; | ||
278 | QTreeWidgetItem *i2c2clk = 0; | ||
279 | if (helper.ReadRegisterField("CMU", "DEVCLKEN", "I2C", en) && | ||
280 | helper.ReadRegisterField("I2C1", "CTL", "EN", tmp0) && | ||
281 | helper.ReadRegisterField("I2C1", "CLKDIV", "CLKDIV", tmp1)) | ||
282 | { | ||
283 | en &= tmp0; | ||
284 | i2c1clk = AddClock(pclk, "i2c1 clk", en ? FROM_PARENT : DISABLED, | ||
285 | 1, 16*(tmp1+1)); | ||
286 | } | ||
287 | else | ||
288 | { | ||
289 | i2c1clk = AddClock(pclk, "i2c1 clk", INVALID); | ||
290 | } | ||
291 | |||
292 | if (helper.ReadRegisterField("CMU", "DEVCLKEN", "I2C", en) && | ||
293 | helper.ReadRegisterField("I2C2", "CTL", "EN", tmp0) && | ||
294 | helper.ReadRegisterField("I2C2", "CLKDIV", "CLKDIV", tmp1)) | ||
295 | { | ||
296 | en &= tmp0; | ||
297 | i2c2clk = AddClock(pclk, "i2c2 clk", en ? FROM_PARENT : DISABLED, | ||
298 | 1, 16*(tmp1+1)); | ||
299 | } | ||
300 | else | ||
301 | { | ||
302 | i2c2clk = AddClock(pclk, "i2c2 clk", INVALID); | ||
303 | } | ||
304 | |||
305 | Q_UNUSED(dsppll); | ||
306 | Q_UNUSED(adcclk); | ||
307 | Q_UNUSED(dacclk); | ||
308 | Q_UNUSED(sdrclk); | ||
309 | Q_UNUSED(nandclk); | ||
310 | Q_UNUSED(sdclk); | ||
311 | Q_UNUSED(mhaclk); | ||
312 | Q_UNUSED(mcaclk); | ||
313 | Q_UNUSED(pwmclk); | ||
314 | Q_UNUSED(i2c1clk); | ||
315 | Q_UNUSED(i2c2clk); | ||
316 | } | ||
317 | |||
91 | void ClockAnalyser::FillTreeRK27XX() | 318 | void ClockAnalyser::FillTreeRK27XX() |
92 | { | 319 | { |
93 | soc_word_t value, value2, value3, value4; | 320 | soc_word_t value, value2, value3, value4; |
diff --git a/utils/regtools/qeditor/std_analysers.h b/utils/regtools/qeditor/std_analysers.h index a9b3022b41..ee95c88f3c 100644 --- a/utils/regtools/qeditor/std_analysers.h +++ b/utils/regtools/qeditor/std_analysers.h | |||
@@ -42,6 +42,7 @@ private: | |||
42 | void FillTree(); | 42 | void FillTree(); |
43 | void FillTreeIMX233(); | 43 | void FillTreeIMX233(); |
44 | void FillTreeRK27XX(); | 44 | void FillTreeRK27XX(); |
45 | void FillTreeATJ213X(); | ||
45 | 46 | ||
46 | private: | 47 | private: |
47 | QGroupBox *m_group; | 48 | QGroupBox *m_group; |