diff options
Diffstat (limited to 'utils/reggen-ng/x1000.reggen')
-rw-r--r-- | utils/reggen-ng/x1000.reggen | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/utils/reggen-ng/x1000.reggen b/utils/reggen-ng/x1000.reggen index 39ad26e782..0d971c59f8 100644 --- a/utils/reggen-ng/x1000.reggen +++ b/utils/reggen-ng/x1000.reggen | |||
@@ -435,6 +435,17 @@ node CPM { | |||
435 | fld 7 0 CLKDIV | 435 | fld 7 0 CLKDIV |
436 | } | 436 | } |
437 | 437 | ||
438 | reg USBCDR 0x50 { | ||
439 | fld 31 30 CLKSRC { enum EXCLK 0; enum SCLK_A 2; enum MPLL 3; } | ||
440 | bit 29 CE | ||
441 | bit 28 BUSY | ||
442 | bit 27 STOP | ||
443 | # PHY_GATE bit undocumented but present in Ingenic kernel sources, | ||
444 | # it's not clear it does anything. | ||
445 | bit 26 PHY_GATE | ||
446 | fld 7 0 CLKDIV | ||
447 | } | ||
448 | |||
438 | reg SSICDR 0x74 { | 449 | reg SSICDR 0x74 { |
439 | bit 31 SFC_CS { enum SCLK_A 0; enum MPLL 1 } | 450 | bit 31 SFC_CS { enum SCLK_A 0; enum MPLL 1 } |
440 | bit 30 SSI_CS { enum EXCLK 0; enum HALF_SFC 1 } | 451 | bit 30 SSI_CS { enum EXCLK 0; enum HALF_SFC 1 } |
@@ -444,8 +455,60 @@ node CPM { | |||
444 | fld 7 0 CLKDIV | 455 | fld 7 0 CLKDIV |
445 | } | 456 | } |
446 | 457 | ||
458 | reg INTR 0xb0 { | ||
459 | bit 1 VBUS | ||
460 | bit 0 ADEV | ||
461 | } | ||
462 | |||
463 | reg INTR_EN 0xb4 { | ||
464 | bit 1 VBUS | ||
465 | bit 0 ADEV | ||
466 | } | ||
467 | |||
447 | reg DRCG 0xd0 | 468 | reg DRCG 0xd0 |
448 | 469 | ||
470 | reg USBPCR 0x3c { | ||
471 | bit 31 USB_MODE { enum USB 0; enum OTG 1; } | ||
472 | bit 30 AVLD_REG | ||
473 | fld 29 28 IDPULLUP_MASK { enum ALWAYS 2; enum ALWAYS_SUSPEND 1; enum FROM_OTG 0; } | ||
474 | bit 27 INCR_MASK | ||
475 | bit 26 TXRISETUNE | ||
476 | bit 25 COMMONONN | ||
477 | bit 24 VBUSVLDEXT | ||
478 | bit 23 VBUSVLDEXTSEL | ||
479 | bit 22 POR | ||
480 | bit 21 SIDDQ | ||
481 | bit 20 OTG_DISABLE | ||
482 | fld 19 17 COMPDISTUNE | ||
483 | fld 16 14 OTGTUNE | ||
484 | fld 13 11 SQRXTUNE | ||
485 | fld 10 7 TXFSLSTUNE | ||
486 | bit 6 TXPREEMPHTUNE | ||
487 | fld 5 4 TXHSXVTUNE | ||
488 | fld 3 0 TXVREFTUNE | ||
489 | } | ||
490 | |||
491 | reg USBRDT 0x40 { | ||
492 | bit 26 HB_MASK | ||
493 | bit 25 VBFIL_LD_EN | ||
494 | bit 24 IDDIG_EN | ||
495 | bit 23 IDDIG_REG | ||
496 | fld 22 0 RDT | ||
497 | } | ||
498 | |||
499 | reg USBVBFIL 0x44 { | ||
500 | fld 31 16 IDDIGFIL | ||
501 | fld 15 0 VBFIL | ||
502 | } | ||
503 | |||
504 | reg USBPCR1 0x48 { | ||
505 | bit 31 BVLD_REG | ||
506 | fld 27 26 REFCLK_SEL { enum CLKCORE 2; enum EXTERNAL 1; enum CRYSTAL 0 } | ||
507 | fld 25 24 REFCLK_DIV { enum 48MHZ 2; enum 24MHZ 1; enum 12MHZ 0 } | ||
508 | bit 21 PORT_RST | ||
509 | bit 19 WORD_IF { enum 16BIT 1; enum 8BIT 0 } | ||
510 | } | ||
511 | |||
449 | reg APCR 0x10 { | 512 | reg APCR 0x10 { |
450 | bit 31 BS | 513 | bit 31 BS |
451 | fld 30 24 PLLM | 514 | fld 30 24 PLLM |
@@ -512,6 +575,24 @@ node CPM { | |||
512 | bit 1 EFUSE | 575 | bit 1 EFUSE |
513 | } | 576 | } |
514 | 577 | ||
578 | reg SRBC 0xc4 { | ||
579 | bit 31 JPEG_SR | ||
580 | bit 30 JPEG_STOP | ||
581 | bit 29 JPEG_ACK | ||
582 | bit 25 LCD_SR | ||
583 | bit 24 LCD_STOP | ||
584 | bit 23 LCD_ACK | ||
585 | bit 21 CIM_STOP | ||
586 | bit 20 CIM_ACK | ||
587 | bit 15 CPU_STOP | ||
588 | bit 14 CPU_ACK | ||
589 | bit 12 OTG_SR | ||
590 | bit 8 AHB2_STOP | ||
591 | bit 7 AHB2_ACK | ||
592 | bit 6 DDR_STOP | ||
593 | bit 5 DDR_ACK | ||
594 | } | ||
595 | |||
515 | reg OPCR 0x24 { | 596 | reg OPCR 0x24 { |
516 | bit 31 IDLE_DIS | 597 | bit 31 IDLE_DIS |
517 | bit 30 MASK_INT | 598 | bit 30 MASK_INT |