diff options
Diffstat (limited to 'utils/reggen-ng/x1000.reggen')
-rw-r--r-- | utils/reggen-ng/x1000.reggen | 364 |
1 files changed, 355 insertions, 9 deletions
diff --git a/utils/reggen-ng/x1000.reggen b/utils/reggen-ng/x1000.reggen index 3e5d976a0b..39ad26e782 100644 --- a/utils/reggen-ng/x1000.reggen +++ b/utils/reggen-ng/x1000.reggen | |||
@@ -121,6 +121,77 @@ node LCD { | |||
121 | reg SMWT 0xbc | 121 | reg SMWT 0xbc |
122 | } | 122 | } |
123 | 123 | ||
124 | node AIC { | ||
125 | title "Audio interface controller" | ||
126 | addr 0xb0020000 | ||
127 | |||
128 | reg CFG 0x00 { | ||
129 | fld 27 24 RFTH | ||
130 | fld 20 16 TFTH | ||
131 | bit 12 MSB | ||
132 | bit 10 IBCKD | ||
133 | bit 9 ISYNCD | ||
134 | bit 8 DMODE | ||
135 | bit 7 CDC_SLAVE | ||
136 | bit 6 LSMP | ||
137 | bit 5 ICDC | ||
138 | bit 4 AUSEL | ||
139 | bit 3 RST | ||
140 | bit 2 BCKD | ||
141 | bit 1 SYNCD | ||
142 | bit 0 ENABLE | ||
143 | } | ||
144 | |||
145 | reg CCR 0x04 { | ||
146 | bit 28 PACK16 | ||
147 | fld 26 24 CHANNEL | ||
148 | fld 21 19 OSS | ||
149 | fld 18 16 ISS | ||
150 | bit 15 RDMS | ||
151 | bit 14 TDMS | ||
152 | bit 11 M2S | ||
153 | bit 10 ENDSW | ||
154 | bit 9 ASVTSU | ||
155 | bit 8 TFLUSH | ||
156 | bit 7 RFLUSH | ||
157 | bit 6 EROR | ||
158 | bit 5 ETUR | ||
159 | bit 4 ERFS | ||
160 | bit 3 ETFS | ||
161 | bit 2 ENLBF | ||
162 | bit 1 ERPL | ||
163 | bit 0 EREC | ||
164 | } | ||
165 | |||
166 | reg I2SCR 0x10 { | ||
167 | bit 17 RFIRST | ||
168 | bit 16 SWLH | ||
169 | bit 13 ISTPBK | ||
170 | bit 12 STPBK | ||
171 | bit 4 ESCLK | ||
172 | bit 0 AMSL | ||
173 | } | ||
174 | |||
175 | reg SR 0x14 { | ||
176 | fld 29 24 RFL | ||
177 | bit 13 8 TFL | ||
178 | bit 6 ROR | ||
179 | bit 5 TUR | ||
180 | bit 4 RFS | ||
181 | bit 3 TFS | ||
182 | } | ||
183 | |||
184 | reg I2SSR 0x1c { | ||
185 | bit 5 CHBSY | ||
186 | bit 4 TBSY | ||
187 | bit 3 RBSY | ||
188 | bit 2 BSY | ||
189 | } | ||
190 | |||
191 | reg I2SDIV 0x30 | ||
192 | reg DR 0x34 | ||
193 | } | ||
194 | |||
124 | node DDRC { | 195 | node DDRC { |
125 | title "DDR controller AHB2 group" | 196 | title "DDR controller AHB2 group" |
126 | desc "note: incomplete, only lists registers used by DDR init code" | 197 | desc "note: incomplete, only lists registers used by DDR init code" |
@@ -185,6 +256,108 @@ node DDRPHY { | |||
185 | reg DXGCR { instance 0x1c0 0x40 4 } | 256 | reg DXGCR { instance 0x1c0 0x40 4 } |
186 | } | 257 | } |
187 | 258 | ||
259 | node SFC { | ||
260 | title "SPI flash controller" | ||
261 | addr 0xb3440000 | ||
262 | |||
263 | reg GLB 0x00 { | ||
264 | bit 13 TRAN_DIR { enum READ 0; enum WRITE 1 } | ||
265 | fld 12 7 THRESHOLD | ||
266 | bit 6 OP_MODE { enum SLAVE 0; enum DMA 1 } | ||
267 | fld 5 3 PHASE_NUM | ||
268 | bit 2 WP_EN | ||
269 | bit 1 0 BURST_MD { enum INCR4 0; enum INCR8 1; | ||
270 | enum INCR16 2; enum INCR32 3 } | ||
271 | } | ||
272 | |||
273 | reg DEV_CONF 0x04 { | ||
274 | fld 17 16 SMP_DELAY | ||
275 | bit 15 CMD_TYPE { enum 8BITS 0; enum 16BITS 1 } | ||
276 | fld 14 13 STA_TYPE { enum 1BYTE 0; enum 2BYTE 1; | ||
277 | enum 3BYTE 2; enum 4BYTE 3 } | ||
278 | fld 12 11 THOLD | ||
279 | fld 10 9 TSETUP | ||
280 | fld 8 5 TSH | ||
281 | bit 4 CPHA | ||
282 | bit 3 CPOL | ||
283 | bit 2 CE_DL | ||
284 | bit 1 HOLD_DL | ||
285 | bit 0 WP_DL | ||
286 | } | ||
287 | |||
288 | reg DEV_STA_EXP 0x08 | ||
289 | reg DEV_STA_RT 0x0c | ||
290 | reg DEV_STA_MSK 0x10 | ||
291 | |||
292 | reg TRAN_CONF { | ||
293 | instance 0x14 0x04 6 | ||
294 | fld 31 29 MODE | ||
295 | fld 28 26 ADDR_WIDTH | ||
296 | bit 25 POLL_EN | ||
297 | bit 24 CMD_EN | ||
298 | bit 23 PHASE_FMT | ||
299 | fld 22 17 DUMMY_BITS | ||
300 | bit 16 DATA_EN | ||
301 | fld 15 0 COMMAND | ||
302 | } | ||
303 | |||
304 | reg TRAN_LENGTH 0x2c | ||
305 | reg DEV_ADDR { instance 0x30 0x04 6 } | ||
306 | reg DEV_PLUS { instance 0x48 0x40 6 } | ||
307 | reg MEM_ADDR 0x60 | ||
308 | |||
309 | reg TRIG 0x64 { | ||
310 | bit 2 FLUSH | ||
311 | bit 1 STOP | ||
312 | bit 0 START | ||
313 | } | ||
314 | |||
315 | reg SR 0x68 { | ||
316 | fld 22 16 FIFO_NUM | ||
317 | fld 6 5 BUSY | ||
318 | bit 4 END | ||
319 | bit 3 TREQ | ||
320 | bit 2 RREQ | ||
321 | bit 1 OVER | ||
322 | bit 0 UNDER | ||
323 | } | ||
324 | |||
325 | reg SCR 0x6c { | ||
326 | bit 4 CLR_END | ||
327 | bit 3 CLR_TREQ | ||
328 | bit 2 CLR_RREQ | ||
329 | bit 1 CLR_OVER | ||
330 | bit 0 CLR_UNDER | ||
331 | } | ||
332 | |||
333 | reg INTC 0x70 { | ||
334 | bit 4 MSK_END | ||
335 | bit 3 MSK_TREQ | ||
336 | bit 2 MSK_RREQ | ||
337 | bit 1 MSK_OVER | ||
338 | bit 0 MSK_UNDER | ||
339 | } | ||
340 | |||
341 | reg FSM 0x74 { | ||
342 | fld 19 16 STATE_AHB | ||
343 | fld 15 11 STATE_SPI | ||
344 | fld 9 6 STATE_CLK | ||
345 | fld 5 3 STATE_DMAC | ||
346 | bit 2 0 STATE_RMC | ||
347 | } | ||
348 | |||
349 | reg CGE 0x78 { | ||
350 | bit 5 SFC | ||
351 | bit 4 FIFO | ||
352 | bit 3 DMA | ||
353 | bit 2 RMC | ||
354 | bit 1 SPI | ||
355 | bit 0 REG | ||
356 | } | ||
357 | |||
358 | reg DATA 0x1000 | ||
359 | } | ||
360 | |||
188 | node CPM { | 361 | node CPM { |
189 | title "Clock, Reset and Power Manager" | 362 | title "Clock, Reset and Power Manager" |
190 | addr 0xb0000000 | 363 | addr 0xb0000000 |
@@ -227,6 +400,16 @@ node CPM { | |||
227 | fld 3 0 CLKDIV | 400 | fld 3 0 CLKDIV |
228 | } | 401 | } |
229 | 402 | ||
403 | reg I2SCDR 0x60 { | ||
404 | bit 31 PCS { enum SCLK_A 0; enum MPLL 1; } | ||
405 | bit 30 CS { enum EXCLK 0; enum PLL 1; } | ||
406 | bit 29 CE | ||
407 | fld 21 13 DIV_M | ||
408 | fld 12 0 DIV_N | ||
409 | } | ||
410 | |||
411 | reg I2SCDR1 0x70 | ||
412 | |||
230 | reg LPCDR 0x64 { | 413 | reg LPCDR 0x64 { |
231 | bit 31 CLKSRC { enum SCLK_A 0; enum MPLL 1; } | 414 | bit 31 CLKSRC { enum SCLK_A 0; enum MPLL 1; } |
232 | bit 28 CE | 415 | bit 28 CE |
@@ -252,6 +435,15 @@ node CPM { | |||
252 | fld 7 0 CLKDIV | 435 | fld 7 0 CLKDIV |
253 | } | 436 | } |
254 | 437 | ||
438 | reg SSICDR 0x74 { | ||
439 | bit 31 SFC_CS { enum SCLK_A 0; enum MPLL 1 } | ||
440 | bit 30 SSI_CS { enum EXCLK 0; enum HALF_SFC 1 } | ||
441 | bit 29 CE | ||
442 | bit 28 BUSY | ||
443 | bit 27 STOP | ||
444 | fld 7 0 CLKDIV | ||
445 | } | ||
446 | |||
255 | reg DRCG 0xd0 | 447 | reg DRCG 0xd0 |
256 | 448 | ||
257 | reg APCR 0x10 { | 449 | reg APCR 0x10 { |
@@ -319,6 +511,25 @@ node CPM { | |||
319 | bit 2 SFC | 511 | bit 2 SFC |
320 | bit 1 EFUSE | 512 | bit 1 EFUSE |
321 | } | 513 | } |
514 | |||
515 | reg OPCR 0x24 { | ||
516 | bit 31 IDLE_DIS | ||
517 | bit 30 MASK_INT | ||
518 | bit 29 MASK_VPU | ||
519 | bit 28 GATE_SCLK_A_BUS | ||
520 | bit 25 L2C_PD | ||
521 | bit 24 REQ_MODE | ||
522 | bit 23 GATE_USBPHY_CLK | ||
523 | bit 22 DIS_STOP_MUX | ||
524 | fld 19 8 O1ST | ||
525 | bit 7 SPENDN0 | ||
526 | bit 6 SPENDN1 | ||
527 | bit 5 CPU_MODE | ||
528 | bit 4 O1SE | ||
529 | bit 3 PD | ||
530 | bit 2 ERCS | ||
531 | bit 1 BUS_MODE | ||
532 | } | ||
322 | } | 533 | } |
323 | 534 | ||
324 | node TCU { | 535 | node TCU { |
@@ -412,21 +623,150 @@ node WDT { | |||
412 | } | 623 | } |
413 | } | 624 | } |
414 | 625 | ||
626 | node DMA { | ||
627 | title "DMA controller" | ||
628 | addr 0xb3421000 | ||
629 | |||
630 | reg CTRL 0x00 { | ||
631 | bit 31 FMSC | ||
632 | bit 30 FSSI | ||
633 | bit 29 FTSSI | ||
634 | bit 28 FUART | ||
635 | bit 27 FAIC | ||
636 | bit 3 HALT | ||
637 | bit 2 AR | ||
638 | bit 0 ENABLE | ||
639 | } | ||
640 | |||
641 | reg IRQP 0x04 | ||
642 | reg DB 0x08 { variant set 4 } | ||
643 | reg DIP 0x10 | ||
644 | reg DIC 0x14 | ||
645 | } | ||
646 | |||
647 | node DMA_CHN { | ||
648 | title "DMA channel registers" | ||
649 | instance 0xb3420000 0x20 8 | ||
650 | |||
651 | reg SA 0x00 | ||
652 | reg TA 0x04 | ||
653 | reg TC 0x08 { | ||
654 | fld 31 24 DOA | ||
655 | fld 23 0 CNT | ||
656 | } | ||
657 | |||
658 | reg RT 0x0c { | ||
659 | field 5 0 TYPE { | ||
660 | enum DMIC_RX 5 | ||
661 | enum I2S_TX 6 | ||
662 | enum I2S_RX 7 | ||
663 | enum AUTO 8 | ||
664 | enum UART2_TX 16 | ||
665 | enum UART2_RX 17 | ||
666 | enum UART1_TX 18 | ||
667 | enum UART1_RX 19 | ||
668 | enum UART0_TX 20 | ||
669 | enum UART0_RX 21 | ||
670 | enum SSI_TX 22 | ||
671 | enum SSI_RX 23 | ||
672 | enum MSC0_TX 26 | ||
673 | enum MSC0_RX 27 | ||
674 | enum MSC1_TX 28 | ||
675 | enum MSC1_RX 29 | ||
676 | enum PCM_TX 32 | ||
677 | enum PCM_RX 33 | ||
678 | enum I2C0_TX 36 | ||
679 | enum I2C0_RX 37 | ||
680 | enum I2C1_TX 38 | ||
681 | enum I2C1_RX 39 | ||
682 | enum I2C2_TX 40 | ||
683 | enum I2C2_RX 41 | ||
684 | } | ||
685 | } | ||
686 | |||
687 | reg CS 0x10 { | ||
688 | bit 31 NDES | ||
689 | bit 30 DES8 | ||
690 | fld 15 8 CDOA | ||
691 | bit 4 AR | ||
692 | bit 3 TT | ||
693 | bit 2 HLT | ||
694 | bit 0 CTE | ||
695 | } | ||
696 | |||
697 | reg CM 0x14 { | ||
698 | bit 23 SAI | ||
699 | bit 22 DAI | ||
700 | fld 19 16 RDIL | ||
701 | fld 15 14 SP { enum 32BIT 0; enum 8BIT 1; enum 16BIT 2 } | ||
702 | fld 13 12 DP { enum 32BIT 0; enum 8BIT 1; enum 16BIT 2 } | ||
703 | fld 10 8 TSZ { enum 32BIT 0; enum 8BIT 1; enum 16BIT 2; | ||
704 | enum 16BYTE 3; enum 32BYTE 4; enum 64BYTE 5; | ||
705 | enum 128BYTE 6; enum AUTO 7; } | ||
706 | bit 2 STDE | ||
707 | bit 1 TIE | ||
708 | bit 0 LINK | ||
709 | } | ||
710 | |||
711 | reg DA 0x18 { | ||
712 | fld 31 12 DBA | ||
713 | fld 11 4 DOA | ||
714 | } | ||
715 | |||
716 | reg SD 0x1c { | ||
717 | fld 31 16 TSD | ||
718 | fld 15 0 SSD | ||
719 | } | ||
720 | } | ||
721 | |||
415 | node RTC { | 722 | node RTC { |
416 | title "Realtime clock" | 723 | title "Realtime clock" |
417 | addr 0xb0003000 | 724 | addr 0xb0003000 |
418 | 725 | ||
419 | reg CR 0x00 | 726 | reg CR 0x00 { |
727 | bit 7 WRDY | ||
728 | bit 6 1HZ | ||
729 | bit 5 1HZIE | ||
730 | bit 4 AF | ||
731 | bit 3 AIE | ||
732 | bit 2 AE | ||
733 | bit 1 SELEXC | ||
734 | bit 0 ENABLE | ||
735 | } | ||
736 | |||
420 | reg SR 0x04 | 737 | reg SR 0x04 |
421 | reg SAR 0x08 | 738 | reg SAR 0x08 |
422 | reg GR 0x0c | 739 | |
740 | reg GR 0x0c { | ||
741 | bit 31 LOCK | ||
742 | fld 25 16 ADJC | ||
743 | fld 15 0 NC1HZ | ||
744 | } | ||
745 | |||
423 | reg HCR 0x20 | 746 | reg HCR 0x20 |
424 | reg WFCR 0x24 | 747 | reg HWFCR 0x24 |
425 | reg RCR 0x28 | 748 | reg HRCR 0x28 |
426 | reg WCR 0x2c | 749 | |
427 | reg RSR 0x30 | 750 | reg HWCR 0x2c { |
428 | reg SPR 0x34 | 751 | fld 31 3 EPDET |
429 | reg WENR 0x3c | 752 | bit 1 EALM |
753 | } | ||
754 | |||
755 | reg HWRSR 0x30 { | ||
756 | bit 8 APD | ||
757 | bit 5 HR | ||
758 | bit 4 PPR | ||
759 | bit 1 PIN | ||
760 | bit 0 ALM | ||
761 | } | ||
762 | |||
763 | reg HSPR 0x34 | ||
764 | |||
765 | reg WENR 0x3c { | ||
766 | bit 31 WEN | ||
767 | bit 15 0 WENPAT | ||
768 | } | ||
769 | |||
430 | reg WKUPPINCR 0x48 | 770 | reg WKUPPINCR 0x48 |
431 | } | 771 | } |
432 | 772 | ||
@@ -544,7 +884,13 @@ node I2C { | |||
544 | bit 0 ACTIVE | 884 | bit 0 ACTIVE |
545 | } | 885 | } |
546 | 886 | ||
547 | reg TAR 0x04 | 887 | reg TAR 0x04 { |
888 | bit 12 10BITS | ||
889 | bit 11 SPECIAL | ||
890 | bit 10 GC_OR_START | ||
891 | fld 9 0 ADDR | ||
892 | } | ||
893 | |||
548 | reg SAR 0x08 | 894 | reg SAR 0x08 |
549 | reg SHCNT 0x14 | 895 | reg SHCNT 0x14 |
550 | reg SLCNT 0x18 | 896 | reg SLCNT 0x18 |