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Diffstat (limited to 'utils/hwstub/stub/atj213x/atj213x.h')
-rw-r--r--utils/hwstub/stub/atj213x/atj213x.h385
1 files changed, 385 insertions, 0 deletions
diff --git a/utils/hwstub/stub/atj213x/atj213x.h b/utils/hwstub/stub/atj213x/atj213x.h
new file mode 100644
index 0000000000..cc5c4fef3e
--- /dev/null
+++ b/utils/hwstub/stub/atj213x/atj213x.h
@@ -0,0 +1,385 @@
1#define PMU_BASE 0xB0000000
2#define PMU_CTL (*(volatile uint32_t *)(PMU_BASE + 0x00))
3#define PMU_CTL_BL_EN (1<<15)
4#define PMU_LRADC (*(volatile uint32_t *)(PMU_BASE + 0x04))
5#define PMU_CHG (*(volatile uint32_t *)(PMU_BASE + 0x08))
6#define PMU_CHG_PBLS (1<<15)
7#define PMU_CHG_PBLS_PWM (1<<15)
8#define PMU_CHG_PBLS_BL_NDR (0<<15)
9#define PMU_CHG_PPHS (1<<14)
10#define PMU_CHG_PPHS_HIGH (1<<14)
11#define PMU_CHG_PPHS_LOW (0<<14)
12#define PMU_CHG_PDUT(x) (((x) & 0x1f) << 8)
13#define PMU_CHG_PDOUT_MASK (0x1f << 8)
14
15#define CMU_BASE 0xB0010000
16#define CMU_COREPLL (*(volatile uint32_t *)(CMU_BASE + 0x00))
17#define CMU_DSPPLL (*(volatile uint32_t *)(CMU_BASE + 0x04))
18#define CMU_AUDIOPLL (*(volatile uint32_t *)(CMU_BASE + 0x08))
19#define CMU_BUSCLK (*(volatile uint32_t *)(CMU_BASE + 0x0C))
20#define CMU_SDRCLK (*(volatile uint32_t *)(CMU_BASE + 0x10))
21#define CMU_ATACLK (*(volatile uint32_t *)(CMU_BASE + 0x04))
22#define CMU_NANDCLK (*(volatile uint32_t *)(CMU_BASE + 0x18))
23#define CMU_SDCLK (*(volatile uint32_t *)(CMU_BASE + 0x1C))
24#define CMU_MHACLK (*(volatile uint32_t *)(CMU_BASE + 0x20))
25#define CMU_BTCLK (*(volatile uint32_t *)(CMU_BASE + 0x24))
26#define CMU_IRCLK (*(volatile uint32_t *)(CMU_BASE + 0x28))
27#define CMU_UART2CLK (*(volatile uint32_t *)(CMU_BASE + 0x2C))
28#define CMU_DMACLK (*(volatile uint32_t *)(CMU_BASE + 0x30))
29#define CMU_FMCLK (*(volatile uint32_t *)(CMU_BASE + 0x34))
30#define CMU_FMCLK_BCKE (1<<5)
31#define CMI_FMCLK_BCKS (1<<4)
32#define CMU_FMCLK_BCKS_32K (0<<4)
33#define CMU_FMCLK_BCKS_3M (1<<4)
34
35#define CMU_FMCLK_BCLK_MASK (CMI_FMCLK_BCKS | (3<<2))
36#define CMU_FMCLK_BCLK_3M (CMU_FMCLK_BCKS_3M | (0<<2))
37#define CMU_FMCLK_BCLK_1_5M (CMU_FMCLK_BCKS_3M | (1<<2))
38#define CMU_FMCLK_BCLK_750K (CMU_FMCLK_BCKS_3M | (2<<2))
39#define CMU_FMCLK_BCLK_375K (CMU_FMCLK_BCKS_3M | (3<<2))
40
41#define CMU_FMCLK_BCLK_32K (0<<2)
42#define CMU_FMCLK_BCLK_16K (1<<2)
43#define CMU_FMCLK_BCLK_8K (2<<2)
44#define CMU_FMCLK_BCLK_4K (3<<2)
45
46#define CMU_MCACLK (*(volatile uint32_t *)(CMU_BASE + 0x38))
47
48#define CMU_DEVCLKEN (*(volatile uint32_t *)(CMU_BASE + 0x80))
49#define CMU_DEVRST (*(volatile uint32_t *)(CMU_BASE + 0x84))
50
51#define RTC_BASE 0xB0018000
52#define RTC_CTL (*(volatile uint32_t *)(RTC_BASE + 0x00))
53#define RTC_DHMS (*(volatile uint32_t *)(RTC_BASE + 0x04))
54#define RTC_YMD (*(volatile uint32_t *)(RTC_BASE + 0x08))
55#define RTC_DHMSALM (*(volatile uint32_t *)(RTC_BASE + 0x0C))
56#define RTC_YMDALM (*(volatile uint32_t *)(RTC_BASE + 0x10))
57#define RTC_WDCTL (*(volatile uint32_t *)(RTC_BASE + 0x14))
58#define RTC_WDCTL_CLR (1<<0)
59
60#define RTC_T0CTL (*(volatile uint32_t *)(RTC_BASE + 0x18))
61#define RTC_T0 (*(volatile uint32_t *)(RTC_BASE + 0x1C))
62#define RTC_T1CTL (*(volatile uint32_t *)(RTC_BASE + 0x20))
63#define RTC_T1 (*(volatile uint32_t *)(RTC_BASE + 0x24))
64
65#define INTC_BASE 0xB0020000
66#define INTC_PD (*(volatile uint32_t *)(INTC_BASE + 0x00))
67#define INTC_MSK (*(volatile uint32_t *)(INTC_BASE + 0x04))
68#define INTC_CFG0 (*(volatile uint32_t *)(INTC_BASE + 0x08))
69#define INTC_CFG1 (*(volatile uint32_t *)(INTC_BASE + 0x0C))
70#define INTC_CFG2 (*(volatile uint32_t *)(INTC_BASE + 0x10))
71#define INTC_EXTCTL (*(volatile uint32_t *)(INTC_BASE + 0x14))
72
73#define SRAMOC_BASE 0xB0030000
74#define SRAMOC_CTL (*(volatile uint32_t *)(SRAMOC_BASE + 0x00))
75#define SRAMOC_STAT (*(volatile uint32_t *)(SRAMOC_BASE + 0x04))
76
77#define BOOT_BASE 0xB00380000
78#define BOOT_NORCTL (*(volatile uint32_t *)(BOOT_BASE + 0x00))
79#define BOOT_BROMCTL (*(volatile uint32_t *)(BOOT_BASE + 0x04))
80#define BOOT_CHIPID (*(volatile uint32_t *)(BOOT_BASE + 0x08))
81
82#define PCNT_BASE 0xB0040000
83#define PCNT_CTL (*(volatile uint32_t *)(PCNT_BASE + 0x00))
84#define PCNT_PC0 (*(volatile uint32_t *)(PCNT_BASE + 0x04))
85#define PCNT_PC1 (*(volatile uint32_t *)(PCNT_BASE + 0x08))
86
87#define DSP_BASE 0xB0050000
88#define DSP_HDR0 (*(volatile uint32_t *)(DSP_BASE + 0x00))
89#define DSP_HDR1 (*(volatile uint32_t *)(DSP_BASE + 0x04))
90#define DSP_HDR2 (*(volatile uint32_t *)(DSP_BASE + 0x08))
91#define DSP_HDR3 (*(volatile uint32_t *)(DSP_BASE + 0x0C))
92#define DSP_HDR4 (*(volatile uint32_t *)(DSP_BASE + 0x10))
93#define DSP_HDR5 (*(volatile uint32_t *)(DSP_BASE + 0x14))
94#define DSP_HSR6 (*(volatile uint32_t *)(DSP_BASE + 0x18))
95#define DSP_HSR7 (*(volatile uint32_t *)(DSP_BASE + 0x1C))
96#define DSP_CTL (*(volatile uint32_t *)(DSP_BASE + 0x20))
97
98#define DMAC_BASE(n) (0xB0060000 + (n<<5))
99#define DMAC_CTL (*(volatile uint32_t *)(DMAC_BASE(0) + 0x00))
100#define DMAC_IRQEN (*(volatile uint32_t *)(DMAC_BASE(0) + 0x04))
101#define DMAC_IRQPD (*(volatile uint32_t *)(DMAC_BASE(0) + 0x08))
102
103/* n in range 0-7 */
104#define DMA_MODE(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x100))
105#define DMA_SRC(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x104))
106#define DMA_DST(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x108))
107#define DMA_CNT(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x10C))
108#define DMA_REM(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x110))
109#define DMA_CMD(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x114))
110
111#define SDR_BASE 0xB0070000
112#define SDR_CTL (*(volatile uint32_t *)(SDR_BASE + 0x00))
113#define SDR_ADDRCFG (*(volatile uint32_t *)(SDR_BASE + 0x04))
114#define SDR_EN (*(volatile uint32_t *)(SDR_BASE + 0x08))
115#define SDR_CMD (*(volatile uint32_t *)(SDR_BASE + 0x0C))
116#define SDR_STAT (*(volatile uint32_t *)(SDR_BASE + 0x10))
117#define SDR_RFSH (*(volatile uint32_t *)(SDR_BASE + 0x14))
118#define SDR_MODE (*(volatile uint32_t *)(SDR_BASE + 0x18))
119#define SDR_MOBILE (*(volatile uint32_t *)(SDR_BASE + 0x1C))
120
121#define MCA_BASE 0xB0080000
122#define MCA_CTL (*(volatile uint32_t *)(MCA_BASE + 0x00))
123
124#define ATA_BASE 0xB0090000
125#define ATA_CONFIG (*(volatile uint32_t *)(ATA_BASE + 0x00))
126#define ATA_UDMACTL (*(volatile uint32_t *)(ATA_BASE + 0x04))
127#define ATA_DATA (*(volatile uint32_t *)(ATA_BASE + 0x08))
128#define ATA_FEATURE (*(volatile uint32_t *)(ATA_BASE + 0x0C))
129#define ATA_SECCNT (*(volatile uint32_t *)(ATA_BASE + 0x10))
130#define ATA_SECNUM (*(volatile uint32_t *)(ATA_BASE + 0x14))
131#define ATA_CLDLOW (*(volatile uint32_t *)(ATA_BASE + 0x18))
132#define ATA_CLDHI (*(volatile uint32_t *)(ATA_BASE + 0x1C))
133#define ATA_HEAD (*(volatile uint32_t *)(ATA_BASE + 0x20))
134#define ATA_CMD (*(volatile uint32_t *)(ATA_BASE + 0x24))
135#define ATA_BYTECNT (*(volatile uint32_t *)(ATA_BASE + 0x28))
136#define ATA_FIFOCTL (*(volatile uint32_t *)(ATA_BASE + 0x2C))
137#define ATA_FIFOCFG (*(volatile uint32_t *)(ATA_BASE + 0x30))
138#define ATA_ADDRDEC (*(volatile uint32_t *)(ATA_BASE + 0x34))
139#define ATA_IRQCTL (*(volatile uint32_t *)(ATA_BASE + 0x38))
140
141#define NAND_BASE 0xB00A0000
142#define NAND_CTL (*(volatile uint32_t *)(NAND_BASE + 0x00))
143#define NAND_STATUS (*(volatile uint32_t *)(NAND_BASE + 0x04))
144#define NAND_FIFOTIM (*(volatile uint32_t *)(NAND_BASE + 0x08))
145#define NAND_CLKCTL (*(volatile uint32_t *)(NAND_BASE + 0x0C))
146#define NAND_BYTECNT (*(volatile uint32_t *)(NAND_BASE + 0x10))
147#define NAND_ADDRLO1234 (*(volatile uint32_t *)(NAND_BASE + 0x14))
148#define NAND_ADDRLO56 (*(volatile uint32_t *)(NAND_BASE + 0x18))
149#define NAND_ADDRHI1234 (*(volatile uint32_t *)(NAND_BASE + 0x1C))
150#define NAND_ADDRHI56 (*(volatile uint32_t *)(NAND_BASE + 0x20))
151#define NAND_BUF0 (*(volatile uint32_t *)(NAND_BASE + 0x24))
152#define NAND_BUF1 (*(volatile uint32_t *)(NAND_BASE + 0x28))
153#define NAND_CMD (*(volatile uint32_t *)(NAND_BASE + 0x2C))
154#define NAND_ECCCTL (*(volatile uint32_t *)(NAND_BASE + 0x30))
155#define NAND_HAMECC0 (*(volatile uint32_t *)(NAND_BASE + 0x34))
156#define NAND_HAMECC1 (*(volatile uint32_t *)(NAND_BASE + 0x38))
157#define NAND_HAMECC2 (*(volatile uint32_t *)(NAND_BASE + 0x3C))
158#define NAND_HAMCEC (*(volatile uint32_t *)(NAND_BASE + 0x40))
159#define NAND_RSE0 (*(volatile uint32_t *)(NAND_BASE + 0x44))
160#define NAND_RSE1 (*(volatile uint32_t *)(NAND_BASE + 0x48))
161#define NAND_RSE2 (*(volatile uint32_t *)(NAND_BASE + 0x4C))
162#define NAND_RSE3 (*(volatile uint32_t *)(NAND_BASE + 0x50))
163#define NAND_RSPS0 (*(volatile uint32_t *)(NAND_BASE + 0x54))
164#define NAND_RSPS1 (*(volatile uint32_t *)(NAND_BASE + 0x58))
165#define NAND_RSPS2 (*(volatile uint32_t *)(NAND_BASE + 0x5C))
166#define NAND_FIFODATA (*(volatile uint32_t *)(NAND_BASE + 0x60))
167#define NAND_DEBUG (*(volatile uint32_t *)(NAND_BASE + 0x70))
168
169#define SD_BASE 0xB00B0000
170#define SD_CTL (*(volatile uint32_t *)(SD_BASE + 0x00))
171#define SD_CMDRSP (*(volatile uint32_t *)(SD_BASE + 0x04))
172#define SD_RW (*(volatile uint32_t *)(SD_BASE + 0x08))
173#define SD_FIFOCTL (*(volatile uint32_t *)(SD_BASE + 0x0C))
174#define SD_CMD (*(volatile uint32_t *)(SD_BASE + 0x10))
175#define SD_ARG (*(volatile uint32_t *)(SD_BASE + 0x14))
176#define SD_CRC7 (*(volatile uint32_t *)(SD_BASE + 0x18))
177#define SD_RSPBUF0 (*(volatile uint32_t *)(SD_BASE + 0x1C))
178#define SD_RSPBUF1 (*(volatile uint32_t *)(SD_BASE + 0x20))
179#define SD_RSPBUF2 (*(volatile uint32_t *)(SD_BASE + 0x24))
180#define SD_RSPBUF3 (*(volatile uint32_t *)(SD_BASE + 0x28))
181#define SD_RSPBUF4 (*(volatile uint32_t *)(SD_BASE + 0x2C))
182#define SD_DAT (*(volatile uint32_t *)(SD_BASE + 0x30))
183#define SD_CLK (*(volatile uint32_t *)(SD_BASE + 0x34))
184#define SD_BYTECNT (*(volatile uint32_t *)(SD_BASE + 0x38))
185
186#define MHA_BASE 0xB00C0000
187#define MHA_CTL (*(volatile uint32_t *)(MHA_BASE + 0x00))
188#define MHA_CFG (*(volatile uint32_t *)(MHA_BASE + 0x04))
189#define MHA_DCSCL01 (*(volatile uint32_t *)(MHA_BASE + 0x10))
190#define MHA_DCSCL23 (*(volatile uint32_t *)(MHA_BASE + 0x14))
191#define MHA_DCSCL45 (*(volatile uint32_t *)(MHA_BASE + 0x18))
192#define MHA_DCSCL67 (*(volatile uint32_t *)(MHA_BASE + 0x1C))
193#define MHA_QSCL (*(volatile uint32_t *)(MHA_BASE + 0x20))
194
195#define BT_BASE 0xB00D0000
196#define BT_MODESEL (*(volatile uint32_t *)(BT_BASE + 0x00))
197#define BT_FIFODAT (*(volatile uint32_t *)(BT_BASE + 0x04))
198
199/* video Encoder */
200#define BT_VEICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
201#define BT_VEIVSEPOF (*(volatile uint32_t *)(BT_BASE + 0x14))
202#define BT_VEIVSEPEF (*(volatile uint32_t *)(BT_BASE + 0x18))
203#define BT_VEIFTP (*(volatile uint32_t *)(BT_BASE + 0x24))
204#define BT_VEIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
205
206/* Video Decoder */
207#define BT_VDICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
208#define BT_VDIHSPOS (*(volatile uint32_t *)(BT_BASE + 0x0C))
209#define BT_VDIHEPOS (*(volatile uint32_t *)(BT_BASE + 0x10))
210#define BT_VDIVSEPOF (*(volatile uint32_t *)(BT_BASE + 0x14))
211#define BT_VDIVSEPEF (*(volatile uint32_t *)(BT_BASE + 0x18))
212#define BT_VDIIRQSTA (*(volatile uint32_t *)(BT_BASE + 0x28))
213#define BT_VDIXYDAT (*(volatile uint32_t *)(BT_BASE + 0x2C))
214#define BT_VDIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
215
216/* CMOS Sensor Interface */
217#define BT_CSICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
218#define BT_CSIHSPOS (*(volatile uint32_t *)(BT_BASE + 0x0C))
219#define BT_CSIHEPOS (*(volatile uint32_t *)(BT_BASE + 0x10))
220#define BT_CSIVSPOS (*(volatile uint32_t *)(BT_BASE + 0x1C))
221#define BT_CSIVEPOS (*(volatile uint32_t *)(BT_BASE + 0x20))
222#define BT_CSIIRQSTA (*(volatile uint32_t *)(BT_BASE + 0x28))
223#define BT_CSIXYDAT (*(volatile uint32_t *)(BT_BASE + 0x2C))
224#define BT_CSIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
225
226/* TS */
227#define BT_TSICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
228#define BT_TSIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
229
230/* Integrated Video Encoder */
231#define BT_IVECTL (*(volatile uint32_t *)(BT_BASE + 0x34))
232#define BT_IVEOUTCTL (*(volatile uint32_t *)(BT_BASE + 0x38))
233#define BT_IVECOTCTL (*(volatile uint32_t *)(BT_BASE + 0x3C))
234#define BT_IVEBRGCTL (*(volatile uint32_t *)(BT_BASE + 0x40))
235#define BT_IVECSATCTL (*(volatile uint32_t *)(BT_BASE + 0x44))
236#define BT_IVECBURCTL (*(volatile uint32_t *)(BT_BASE + 0x48))
237#define BT_IVESYNCAMCTL (*(volatile uint32_t *)(BT_BASE + 0x4C))
238
239#define OTG_BASE 0xB00E0000
240#define OTG_OUT0BC (*(volatile uint8_t *)(OTG_BASE + 0x00)) // ok (byte count?)
241#define OTG_IN0BC (*(volatile uint8_t *)(OTG_BASE + 0x01)) // ok (byte count?)
242#define OTG_EP0CS (*(volatile uint8_t *)(OTG_BASE + 0x02)) // ok
243#define EP_NAK (1<<1) // from rt source
244#define EP0_IN_BUSY (1<<2)
245#define EP0_OUT_BUSY (1<<3)
246
247#define OTG_OUT1CON (*(volatile uint8_t *)(OTG_BASE + 0x0A)) // ok
248#define OTG_OUT1CS (*(volatile uint8_t *)(OTG_BASE + 0x0B)) // missing in rt
249
250#define OTG_OUT2CON (*(volatile uint8_t *)(OTG_BASE + 0x12)) // missing in sdk
251#define OTG_OUT2CS (*(volatile uint8_t *)(OTG_BASE + 0x13)) // deduced
252
253#define OTG_IN2BCL (*(volatile uint8_t *)(OTG_BASE + 0x14)) // missing in rt
254#define OTG_IN2BCH (*(volatile uint8_t *)(OTG_BASE + 0x15)) // missing in rt
255#define OTG_IN2CON (*(volatile uint8_t *)(OTG_BASE + 0x16)) // ok
256#define OTG_IN2CS (*(volatile uint8_t *)(OTG_BASE + 0x17)) //
257
258#define OTG_FIFO1DAT (*(volatile uint32_t *)(OTG_BASE + 0x84)) // missing in rt
259#define OTG_FIFO2DAT (*(volatile uint32_t *)(OTG_BASE + 0x88)) // missing in rt
260
261#define OTG_EP0INDAT (*(volatile uint32_t *)(OTG_BASE + 0x100)) // ok
262
263#define OTG_EP0OUTDAT (*(volatile uint32_t *)(OTG_BASE + 0x140)) // ok
264
265#define OTG_SETUPDAT (*(volatile uint32_t *)(OTG_BASE + 0x180)) // ok
266#define OTG_IN04IRQ (*(volatile uint8_t *)(OTG_BASE + 0x188))
267#define OTG_OUT04IRQ (*(volatile uint8_t *)(OTG_BASE + 0x18a))
268#define OTG_USBIRQ (*(volatile uint8_t *)(OTG_BASE + 0x18C)) // ok
269
270#define OTG_IN04IEN (*(volatile uint8_t *)(OTG_BASE + 0x194))
271#define OTG_OUT04IEN (*(volatile uint8_t *)(OTG_BASE + 0x196))
272#define OTG_USBIEN (*(volatile uint8_t *)(OTG_BASE + 0x198)) // ok
273
274#define OTG_IVECT (*(volatile uint8_t *)(OTG_BASE + 0x1A0)) // missing in rt
275#define OTG_ENDPRST (*(volatile uint8_t *)(OTG_BASE + 0x1A2)) // ok
276#define OTG_USBCS (*(volatile uint8_t *)(OTG_BASE + 0x1A3)) // ok
277#define SOFT_DISCONN (1<<6) // set for soft disconnect
278
279#define OTG_FIFOCTL (*(volatile uint8_t *)(OTG_BASE + 0x1A8)) // ok
280
281
282#define OTG_OTGIRQ (*(volatile uint8_t *)(OTG_BASE + 0x1BC))
283#define OTG_FSMSTAT (*(volatile uint8_t *)(OTG_BASE + 0x1BD))
284#define OTG_CTRL (*(volatile uint8_t *)(OTG_BASE + 0x1BE))
285#define OTG_STAT (*(volatile uint8_t *)(OTG_BASE + 0x1BF))
286#define OTG_OTGIEN (*(volatile uint8_t *)(OTG_BASE + 0x1C0))
287
288#define OTG_TAAIDLBDIS (*(volatile uint8_t *)(OTG_BASE + 0x1C1))
289#define OTG_TAWAITBCON (*(volatile uint8_t *)(OTG_BASE + 0x1C2))
290#define OTG_TBVBUSPLS (*(volatile uint8_t *)(OTG_BASE + 0x1C3))
291#define OTG_TBVBUSDISPLS (*(volatile uint8_t *)(OTG_BASE + 0x1C7))
292
293#define OTG_HCIN1MAXPCKL (*(volatile uint8_t *)(OTG_BASE + 0x1E2))
294#define OTG_HCIN1MAXPCKH (*(volatile uint8_t *)(OTG_BASE + 0x1E3))
295
296#define OTG_OUT1STADDR (*(volatile uint8_t *)(OTG_BASE + 0x304))
297
298#define OTG_IN2STADDR (*(volatile uint8_t *)(OTG_BASE + 0x348))
299
300#define OTG_HCOUT2MAXPCKL (*(volatile uint8_t *)(OTG_BASE + 0x3E4))
301#define OTG_HCOUT2MAXPCKH (*(volatile uint8_t *)(OTG_BASE + 0x3E5))
302
303#define OTG_USBEIRQ (*(volatile uint8_t *)(OTG_BASE + 0x400))
304
305#define OTG_DMAEPSEL (*(volatile uint8_t *)(OTG_BASE + 0x40C))
306
307#define YUV2RGB_BASE 0xB00F0000
308#define YUV2RGB_CTL (*(volatile uint32_t *)(YUV2RGB_BASE + 0x00))
309#define YUV2RGB_FIFODATA (*(volatile uint32_t *)(YUV2RGB_BASE + 0x04))
310#define YUV2RGB_CLKCTL (*(volatile uint32_t *)(YUV2RGB_BASE + 0x08))
311#define YUV2RGB_FRAMECOUNT (*(volatile uint32_t *)(YUV2RGB_BASE + 0x0C))
312
313#define DAC_BASE 0xB0100000
314#define DAC_CTL (*(volatile uint32_t *)(DAC_BASE + 0x00))
315#define DAC_FIFOCTL (*(volatile uint32_t *)(DAC_BASE + 0x04))
316#define DAC_DAT (*(volatile uint32_t *)(DAC_BASE + 0x08))
317#define DAC_DEBUG (*(volatile uint32_t *)(DAC_BASE + 0x0C))
318#define DAC_ANALOG (*(volatile uint32_t *)(DAC_BASE + 0x10))
319
320#define ADC_BASE 0xB0110000
321#define ADC_CTL (*(volatile uint32_t *)(ADC_BASE + 0x00))
322#define ADC_FIFOCTL (*(volatile uint32_t *)(ADC_BASE + 0x04))
323#define ADC_DAT (*(volatile uint32_t *)(ADC_BASE + 0x08))
324#define ADC_DEBUG (*(volatile uint32_t *)(ADC_BASE + 0x0C))
325#define ADC_ANALOG (*(volatile uint32_t *)(ADC_BASE + 0x10))
326
327#define TP_BASE 0xB0120000
328#define TP_CTL (*(volatile uint32_t *)(TP_BASE + 0x00))
329#define TP_DAT (*(volatile uint32_t *)(TP_BASE + 0x04))
330
331#define SPDIF_BASE 0xB0140000
332#define SPDIF_CTL (*(volatile uint32_t *)(SPDIF_BASE + 0x00))
333#define SPDIF_STAT (*(volatile uint32_t *)(SPDIF_BASE + 0x04))
334#define SPDIF_TXDAT (*(volatile uint32_t *)(SPDIF_BASE + 0x08))
335#define SPDIF_RXDAT (*(volatile uint32_t *)(SPDIF_BASE + 0x0C))
336#define SPDIF_TXCSTAT (*(volatile uint32_t *)(SPDIF_BASE + 0x10))
337#define SPDIF_RXCSTAT (*(volatile uint32_t *)(SPDIF_BASE + 0x14))
338
339#define PCM_BASE 0xB0150000
340#define PCM_CTL (*(volatile uint32_t *)(PCM_BASE + 0x00))
341#define PCM_STAT (*(volatile uint32_t *)(PCM_BASE + 0x04))
342#define PCM_RXDAT (*(volatile uint32_t *)(PCM_BASE + 0x08))
343#define PCM_TXDAT (*(volatile uint32_t *)(PCM_BASE + 0x0C))
344
345/* n = 0,1 */
346#define UART_BASE(n) (0xB0160000 + (n<<5))
347#define UART_CTL(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x00))
348#define UART_RXDAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x04))
349#define UART_TXDAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x08))
350#define UART_STAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x0C))
351
352#define IR_PL (*(volatile uint32_t *)(UART_BASE(0) + 0x10))
353#define IR_RBC (*(volatile uint32_t *)(UART_BASE(0) + 0x14))
354
355/* n = 0,1 */
356#define I2C_BASE(n) (0xB0180000 + (n<<5))
357#define I2C_CTL(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x00))
358#define I2C_CLKDIV(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x04))
359#define I2C_STAT(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x08))
360#define I2C_ADDR(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x0C))
361#define I2C_DAT(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x10))
362
363#define SPI_BASE 0xB0190000
364#define SPI_CTL (*(volatile uint32_t *)(SPI_BASE + 0x00))
365#define SPI_CLKDIV (*(volatile uint32_t *)(SPI_BASE + 0x04))
366#define SPI_STAT (*(volatile uint32_t *)(SPI_BASE + 0x08))
367#define SPI_RXDAT (*(volatile uint32_t *)(SPI_BASE + 0x0C))
368#define SPI_TXDAT (*(volatile uint32_t *)(SPI_BASE + 0x10))
369
370#define KEY_BASE 0xB01A0000
371#define KEY_CTL (*(volatile uint32_t *)(KEY_BASE + 0x00))
372#define KEY_DAT0 (*(volatile uint32_t *)(KEY_BASE + 0x04))
373#define KEY_DAT1 (*(volatile uint32_t *)(KEY_BASE + 0x08))
374#define KEY_DAT2 (*(volatile uint32_t *)(KEY_BASE + 0x0C))
375#define KEY_DAT3 (*(volatile uint32_t *)(KEY_BASE + 0x10))
376
377#define GPIO_BASE 0xB01C0000
378#define GPIO_AOUTEN (*(volatile uint32_t *)(GPIO_BASE + 0x00))
379#define GPIO_AINEN (*(volatile uint32_t *)(GPIO_BASE + 0x04))
380#define GPIO_ADAT (*(volatile uint32_t *)(GPIO_BASE + 0x08))
381#define GPIO_BOUTEN (*(volatile uint32_t *)(GPIO_BASE + 0x0C))
382#define GPIO_BINEN (*(volatile uint32_t *)(GPIO_BASE + 0x10))
383#define GPIO_BDAT (*(volatile uint32_t *)(GPIO_BASE + 0x14))
384#define GPIO_MFCTL0 (*(volatile uint32_t *)(GPIO_BASE + 0x18))
385#define GPIO_MFCTL1 (*(volatile uint32_t *)(GPIO_BASE + 0x1C))
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-25 12:37:09 +0000