diff options
Diffstat (limited to 'utils/atj2137/adfuload/test_binary/timer_irq/crt0.S')
-rw-r--r-- | utils/atj2137/adfuload/test_binary/timer_irq/crt0.S | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/utils/atj2137/adfuload/test_binary/timer_irq/crt0.S b/utils/atj2137/adfuload/test_binary/timer_irq/crt0.S new file mode 100644 index 0000000000..7b46164ab4 --- /dev/null +++ b/utils/atj2137/adfuload/test_binary/timer_irq/crt0.S | |||
@@ -0,0 +1,98 @@ | |||
1 | #include "mips.h" | ||
2 | |||
3 | .extern main | ||
4 | .global start | ||
5 | |||
6 | .set mips32r2 | ||
7 | .set noreorder | ||
8 | .set noat | ||
9 | |||
10 | .section .init.text,"ax",%progbits | ||
11 | |||
12 | start: | ||
13 | di # disable interrupts | ||
14 | bltzal zero, load_addr # ra = PC + 8, branch not taken | ||
15 | nop | ||
16 | |||
17 | load_addr: | ||
18 | addiu v0, ra, -12 # calc real load address | ||
19 | # account for branch delay slot | ||
20 | # and very first 'di' instruction | ||
21 | la t0, relocstart | ||
22 | la t1, relocend | ||
23 | beq t0, v0, entry_point # no relocation needed | ||
24 | nop | ||
25 | |||
26 | reloc_loop: | ||
27 | lw t2, 0(v0) # src | ||
28 | addiu v0, 4 # inc src addr | ||
29 | sw t2, 0(t0) # dst | ||
30 | bne t0, t1, reloc_loop | ||
31 | addiu t0, 4 # inc dst addr | ||
32 | |||
33 | entry_point_jump: | ||
34 | la t0, entry_point | ||
35 | jr t0 | ||
36 | nop | ||
37 | |||
38 | entry_point: | ||
39 | # setup caches | ||
40 | # 4-way, 256 sets, 16 bytes cacheline I/D | ||
41 | li t0, 3 # enable cache for kseg0 accesses | ||
42 | mtc0 t0, C0_CONFIG | ||
43 | |||
44 | la t0, 0x80000000 # an idx op should use an unmappable address | ||
45 | ori t1, t0, 0x4000 # 16kB cache | ||
46 | mtc0 zero, C0_TAGLO | ||
47 | mtc0 zero, C0_TAGHI | ||
48 | |||
49 | cache_init_loop: | ||
50 | cache 8, 0(t0) # index store icache tag | ||
51 | cache 9, 0(t0) # index store dcache tag | ||
52 | bne t0, t1, cache_init_loop | ||
53 | addiu t0, t0, 0x10 | ||
54 | |||
55 | intc_setup: | ||
56 | li t0, 0xb0020000 # INTC base | ||
57 | lw zero, 4(t0) # INTC_MSK mask all interrupt sources | ||
58 | |||
59 | core_irq_setup: | ||
60 | li t0, 0x00404000 # BEV=1 for C0_EBASE setup, IM6=1, IE=0 | ||
61 | mtc0 t0, C0_STATUS | ||
62 | |||
63 | la t0, _irqbase # vectors base address must be 4k aligned | ||
64 | mtc0 t0, C0_EBASE | ||
65 | |||
66 | li t0, 0x00004000 | ||
67 | mtc0 t0, C0_STATUS # BEV=0, IM6=1, IE=0 | ||
68 | |||
69 | li t1, 0x08800000 | ||
70 | mtc0 t1, C0_CAUSE # DC=1, IV=1 | ||
71 | mtc0 zero,C0_INTCTL # VS = 0 | ||
72 | |||
73 | # clear bss | ||
74 | la t0, bssbegin | ||
75 | la t1, bssend | ||
76 | |||
77 | clear_bss_loop: | ||
78 | sw zero, 0(t0) | ||
79 | bne t0, t1, clear_bss_loop | ||
80 | addiu t0, 4 | ||
81 | |||
82 | # setup stack | ||
83 | la k0, irqstackend | ||
84 | la sp, stackend | ||
85 | la t0, stackbegin | ||
86 | li t1, 0xdeadbeef | ||
87 | |||
88 | stack_munge_loop: | ||
89 | sw t1, 0(t0) | ||
90 | bne t0, sp, stack_munge_loop | ||
91 | addiu t0, 4 | ||
92 | |||
93 | # jump to C code with enabled interrupts | ||
94 | j main | ||
95 | ei | ||
96 | |||
97 | .set at | ||
98 | .set reorder | ||