diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/r61509.h | 105 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c | 139 |
2 files changed, 175 insertions, 69 deletions
diff --git a/firmware/export/r61509.h b/firmware/export/r61509.h new file mode 100644 index 0000000000..ca966ee781 --- /dev/null +++ b/firmware/export/r61509.h | |||
@@ -0,0 +1,105 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /* | ||
23 | * Register definitions for the Renesas R61509 TFT Panel | ||
24 | */ | ||
25 | #ifndef __R61509_H | ||
26 | #define __R61509_H | ||
27 | |||
28 | /* Register list */ | ||
29 | #define REG_DRIVER_OUTPUT 0x001 | ||
30 | #define REG_LCD_DR_WAVE_CTRL 0x002 | ||
31 | #define REG_ENTRY_MODE 0x003 | ||
32 | #define REG_DISP_CTRL1 0x007 | ||
33 | #define REG_DISP_CTRL2 0x008 | ||
34 | #define REG_DISP_CTRL3 0x009 | ||
35 | #define REG_LPCTRL 0x00B | ||
36 | #define REG_EXT_DISP_CTRL1 0x00C | ||
37 | #define REG_EXT_DISP_CTRL2 0x00F | ||
38 | #define REG_PAN_INTF_CTRL1 0x010 | ||
39 | #define REG_PAN_INTF_CTRL2 0x011 | ||
40 | #define REG_PAN_INTF_CTRL3 0x012 | ||
41 | #define REG_PAN_INTF_CTRL4 0x020 | ||
42 | #define REG_PAN_INTF_CTRL5 0x021 | ||
43 | #define REG_PAN_INTF_CTRL6 0x022 | ||
44 | #define REG_FRM_MRKR_CTRL 0x090 | ||
45 | |||
46 | #define REG_PWR_CTRL1 0x100 | ||
47 | #define REG_PWR_CTRL2 0x101 | ||
48 | #define REG_PWR_CTRL3 0x102 | ||
49 | #define REG_PWR_CTRL4 0x103 | ||
50 | #define REG_PWR_CTRL5 0x107 | ||
51 | #define REG_PWR_CTRL6 0x110 | ||
52 | #define REG_PWR_CTRL7 0x112 | ||
53 | |||
54 | #define REG_RAM_HADDR_SET 0x200 | ||
55 | #define REG_RAM_VADDR_SET 0x201 | ||
56 | #define REG_RW_GRAM 0x202 | ||
57 | #define REG_RAM_HADDR_START 0x210 | ||
58 | #define REG_RAM_HADDR_END 0x211 | ||
59 | #define REG_RAM_VADDR_START 0x212 | ||
60 | #define REG_RAM_VADDR_END 0x213 | ||
61 | #define REG_RW_NVM 0x280 | ||
62 | #define REG_VCOM_HVOLTAGE1 0x281 | ||
63 | #define REG_VCOM_HVOLTAGE2 0x282 | ||
64 | |||
65 | #define REG_GAMMA_CTRL1 0x300 | ||
66 | #define REG_GAMMA_CTRL2 0x301 | ||
67 | #define REG_GAMMA_CTRL3 0x302 | ||
68 | #define REG_GAMMA_CTRL4 0x303 | ||
69 | #define REG_GAMMA_CTRL5 0x304 | ||
70 | #define REG_GAMMA_CTRL6 0x305 | ||
71 | #define REG_GAMMA_CTRL7 0x306 | ||
72 | #define REG_GAMMA_CTRL8 0x307 | ||
73 | #define REG_GAMMA_CTRL9 0x308 | ||
74 | #define REG_GAMMA_CTRL10 0x309 | ||
75 | #define REG_GAMMA_CTRL11 0x30A | ||
76 | #define REG_GAMMA_CTRL12 0x30B | ||
77 | #define REG_GAMMA_CTRL13 0x30C | ||
78 | #define REG_GAMMA_CTRL14 0x30D | ||
79 | |||
80 | #define REG_BIMG_NR_LINE 0x400 | ||
81 | #define REG_BIMG_DISP_CTRL 0x401 | ||
82 | #define REG_BIMG_VSCROLL_CTRL 0x404 | ||
83 | |||
84 | #define REG_PARTIMG1_POS 0x500 | ||
85 | #define REG_PARTIMG1_RAM_START 0x501 | ||
86 | #define REG_PARTIMG1_RAM_END 0x502 | ||
87 | #define REG_PARTIMG2_POS 0x503 | ||
88 | #define REG_PARTIMG2_RAM_START 0x504 | ||
89 | #define REG_PARTIMG2_RAM_END 0x505 | ||
90 | |||
91 | #define REG_SOFT_RESET 0x600 | ||
92 | #define REG_ENDIAN_CTRL 0x606 | ||
93 | #define REG_NVM_ACCESS_CTRL 0x6F0 | ||
94 | |||
95 | /* Bits */ | ||
96 | #define DRIVER_OUTPUT_SS_BIT (1 << 8) | ||
97 | #define DRIVER_OUTPUT_SM_BIT (1 << 10) | ||
98 | |||
99 | #define SOFT_RESET_EN (1 << 0) | ||
100 | #define SOFT_RESET_DIS (0 << 0) | ||
101 | |||
102 | #define ENDIAN_CTRL_BIG | ||
103 | #define ENDIAN_CTRL_LITTLE | ||
104 | |||
105 | #endif /* __R61509_H */ \ No newline at end of file | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c index d46cee6884..05e4d3a9fc 100644 --- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c | |||
@@ -21,6 +21,7 @@ | |||
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "jz4740.h" | 23 | #include "jz4740.h" |
24 | #include "r61509.h" | ||
24 | #include "lcd-target.h" | 25 | #include "lcd-target.h" |
25 | 26 | ||
26 | #define PIN_CS_N (32*1+17) /* Chip select */ | 27 | #define PIN_CS_N (32*1+17) /* Chip select */ |
@@ -60,81 +61,81 @@ static void _display_on(void) | |||
60 | { | 61 | { |
61 | int i; | 62 | int i; |
62 | 63 | ||
63 | SLCD_SEND_COMMAND(0x600, 1); | 64 | SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET_EN); |
64 | SLEEP(700000); | 65 | SLEEP(700000); |
65 | SLCD_SEND_COMMAND(0x600, 0); | 66 | SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET_DIS); |
66 | SLEEP(700000); | 67 | SLEEP(700000); |
67 | SLCD_SEND_COMMAND(0x606, 0); | 68 | SLCD_SEND_COMMAND(REG_ENDIAN_CTRL, 0); |
68 | 69 | ||
69 | SLCD_SEND_COMMAND(1, 0x100); | 70 | SLCD_SEND_COMMAND(REG_DRIVER_OUTPUT, 0x100); |
70 | SLCD_SEND_COMMAND(2, 0x100); | 71 | SLCD_SEND_COMMAND(REG_LCD_DR_WAVE_CTRL, 0x100); |
71 | SLCD_SEND_COMMAND(3, 0x1028); | 72 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, 0x1028); |
72 | SLCD_SEND_COMMAND(8, 0x503); | 73 | SLCD_SEND_COMMAND(REG_DISP_CTRL2, 0x503); |
73 | SLCD_SEND_COMMAND(9, 1); | 74 | SLCD_SEND_COMMAND(REG_DISP_CTRL3, 1); |
74 | SLCD_SEND_COMMAND(0xB, 0x10); | 75 | SLCD_SEND_COMMAND(REG_LPCTRL, 0x10); |
75 | SLCD_SEND_COMMAND(0xC, 0); | 76 | SLCD_SEND_COMMAND(REG_EXT_DISP_CTRL1, 0); |
76 | SLCD_SEND_COMMAND(0xF, 0); | 77 | SLCD_SEND_COMMAND(REG_EXT_DISP_CTRL2, 0); |
77 | SLCD_SEND_COMMAND(7, 1); | 78 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, 1); |
78 | SLCD_SEND_COMMAND(0x10, 0x12); | 79 | SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL1, 0x12); |
79 | SLCD_SEND_COMMAND(0x11, 0x202); | 80 | SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL2, 0x202); |
80 | SLCD_SEND_COMMAND(0x12, 0x300); | 81 | SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL3, 0x300); |
81 | SLCD_SEND_COMMAND(0x20, 0x21e); | 82 | SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL4, 0x21e); |
82 | SLCD_SEND_COMMAND(0x21, 0x202); | 83 | SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL5, 0x202); |
83 | SLCD_SEND_COMMAND(0x22, 0x100); | 84 | SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL6, 0x100); |
84 | SLCD_SEND_COMMAND(0x90, 0x8000); | 85 | SLCD_SEND_COMMAND(REG_FRM_MRKR_CTRL, 0x8000); |
85 | SLCD_SEND_COMMAND(0x100, 0x16b0); | 86 | SLCD_SEND_COMMAND(REG_PWR_CTRL1, 0x16b0); |
86 | SLCD_SEND_COMMAND(0x101, 0x147); | 87 | SLCD_SEND_COMMAND(REG_PWR_CTRL2, 0x147); |
87 | SLCD_SEND_COMMAND(0x102, 0x1bd); | 88 | SLCD_SEND_COMMAND(REG_PWR_CTRL3, 0x1bd); |
88 | SLCD_SEND_COMMAND(0x103, 0x2f00); | 89 | SLCD_SEND_COMMAND(REG_PWR_CTRL4, 0x2f00); |
89 | SLCD_SEND_COMMAND(0x107, 0); | 90 | SLCD_SEND_COMMAND(REG_PWR_CTRL5, 0); |
90 | SLCD_SEND_COMMAND(0x110, 1); | 91 | SLCD_SEND_COMMAND(REG_PWR_CTRL6, 1); |
91 | SLCD_SEND_COMMAND(0x200, 0); /* set cursor at x_start */ | 92 | SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, 0); /* set cursor at x_start */ |
92 | SLCD_SEND_COMMAND(0x201, 0); /* set cursor at y_start */ | 93 | SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, 0); /* set cursor at y_start */ |
93 | SLCD_SEND_COMMAND(0x210, 0); /* y_start*/ | 94 | SLCD_SEND_COMMAND(REG_RAM_HADDR_START, 0); /* y_start*/ |
94 | SLCD_SEND_COMMAND(0x211, 239); /* y_end */ | 95 | SLCD_SEND_COMMAND(REG_RAM_HADDR_END, 239); /* y_end */ |
95 | SLCD_SEND_COMMAND(0x212, 0); /* x_start */ | 96 | SLCD_SEND_COMMAND(REG_RAM_VADDR_START, 0); /* x_start */ |
96 | SLCD_SEND_COMMAND(0x213, 399); /* x_end */ | 97 | SLCD_SEND_COMMAND(REG_RAM_VADDR_END, 399); /* x_end */ |
97 | SLCD_SEND_COMMAND(0x280, 0); | 98 | SLCD_SEND_COMMAND(REG_RW_NVM, 0); |
98 | SLCD_SEND_COMMAND(0x281, 6); | 99 | SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE1, 6); |
99 | SLCD_SEND_COMMAND(0x282, 0); | 100 | SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE2, 0); |
100 | SLCD_SEND_COMMAND(0x300, 0x101); | 101 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL1, 0x101); |
101 | SLCD_SEND_COMMAND(0x301, 0xb27); | 102 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL2, 0xb27); |
102 | SLCD_SEND_COMMAND(0x302, 0x132a); | 103 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL3, 0x132a); |
103 | SLCD_SEND_COMMAND(0x303, 0x2a13); | 104 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL4, 0x2a13); |
104 | SLCD_SEND_COMMAND(0x304, 0x270b); | 105 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL5, 0x270b); |
105 | SLCD_SEND_COMMAND(0x305, 0x101); | 106 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL6, 0x101); |
106 | SLCD_SEND_COMMAND(0x306, 0x1205); | 107 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL7, 0x1205); |
107 | SLCD_SEND_COMMAND(0x307, 0x512); | 108 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL8, 0x512); |
108 | SLCD_SEND_COMMAND(0x308, 5); | 109 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL9, 5); |
109 | SLCD_SEND_COMMAND(0x309, 3); | 110 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL10, 3); |
110 | SLCD_SEND_COMMAND(0x30a, 0xf04); | 111 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL11, 0xf04); |
111 | SLCD_SEND_COMMAND(0x30b, 0xf00); | 112 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL12, 0xf00); |
112 | SLCD_SEND_COMMAND(0x30c, 0xf); | 113 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL13, 0xf); |
113 | SLCD_SEND_COMMAND(0x30d, 0x40f); | 114 | SLCD_SEND_COMMAND(REG_GAMMA_CTRL14, 0x40f); |
114 | SLCD_SEND_COMMAND(0x30e, 0x300); | 115 | SLCD_SEND_COMMAND(0x30e, 0x300); |
115 | SLCD_SEND_COMMAND(0x30f, 0x500); | 116 | SLCD_SEND_COMMAND(0x30f, 0x500); |
116 | SLCD_SEND_COMMAND(0x400, 0x3100); | 117 | SLCD_SEND_COMMAND(REG_BIMG_NR_LINE, 0x3100); |
117 | SLCD_SEND_COMMAND(0x401, 1); | 118 | SLCD_SEND_COMMAND(REG_BIMG_DISP_CTRL, 1); |
118 | SLCD_SEND_COMMAND(0x404, 0); | 119 | SLCD_SEND_COMMAND(REG_BIMG_VSCROLL_CTRL, 0); |
119 | SLCD_SEND_COMMAND(0x500, 0); | 120 | SLCD_SEND_COMMAND(REG_PARTIMG1_POS, 0); |
120 | SLCD_SEND_COMMAND(0x501, 0); | 121 | SLCD_SEND_COMMAND(REG_PARTIMG1_RAM_START, 0); |
121 | SLCD_SEND_COMMAND(0x502, 0); | 122 | SLCD_SEND_COMMAND(REG_PARTIMG1_RAM_END, 0); |
122 | SLCD_SEND_COMMAND(0x503, 0); | 123 | SLCD_SEND_COMMAND(REG_PARTIMG2_POS, 0); |
123 | SLCD_SEND_COMMAND(0x504, 0); | 124 | SLCD_SEND_COMMAND(REG_PARTIMG2_RAM_START, 0); |
124 | SLCD_SEND_COMMAND(0x505, 0); | 125 | SLCD_SEND_COMMAND(REG_PARTIMG2_RAM_END, 0); |
125 | SLCD_SEND_COMMAND(0x606, 0); | 126 | SLCD_SEND_COMMAND(REG_ENDIAN_CTRL, 0); |
126 | SLCD_SEND_COMMAND(0x6f0, 0); | 127 | SLCD_SEND_COMMAND(REG_NVM_ACCESS_CTRL, 0); |
127 | SLCD_SEND_COMMAND(0x7f0, 0x5420); | 128 | SLCD_SEND_COMMAND(0x7f0, 0x5420); |
128 | SLCD_SEND_COMMAND(0x7f3, 0x288a); | 129 | SLCD_SEND_COMMAND(0x7f3, 0x288a); |
129 | SLCD_SEND_COMMAND(0x7f4, 0x22); | 130 | SLCD_SEND_COMMAND(0x7f4, 0x22); |
130 | SLCD_SEND_COMMAND(0x7f5, 1); | 131 | SLCD_SEND_COMMAND(0x7f5, 1); |
131 | SLCD_SEND_COMMAND(0x7f0, 0); | 132 | SLCD_SEND_COMMAND(0x7f0, 0); |
132 | 133 | ||
133 | SLCD_SEND_COMMAND(7, 0x173); | 134 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, 0x173); |
134 | SLEEP(3500000); | 135 | SLEEP(3500000); |
135 | SLCD_SEND_COMMAND(7, 0x171); | 136 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, 0x171); |
136 | SLEEP(3500000); | 137 | SLEEP(3500000); |
137 | SLCD_SEND_COMMAND(7, 0x173); | 138 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, 0x173); |
138 | SLEEP(3500000); | 139 | SLEEP(3500000); |
139 | } | 140 | } |
140 | 141 | ||
@@ -181,13 +182,13 @@ void lcd_init_controller(void) | |||
181 | 182 | ||
182 | void lcd_set_target(short x, short y, short width, short height) | 183 | void lcd_set_target(short x, short y, short width, short height) |
183 | { | 184 | { |
184 | SLCD_SEND_COMMAND(0x210, y); /* y_start */ | 185 | SLCD_SEND_COMMAND(REG_RAM_HADDR_START, y); /* y_start */ |
185 | SLCD_SEND_COMMAND(0x211, y+height); /* y_end */ | 186 | SLCD_SEND_COMMAND(REG_RAM_HADDR_END, y+height); /* y_end */ |
186 | SLCD_SEND_COMMAND(0x212, x); /* x_start */ | 187 | SLCD_SEND_COMMAND(REG_RAM_VADDR_START, x); /* x_start */ |
187 | SLCD_SEND_COMMAND(0x213, x+width); /* x_end */ | 188 | SLCD_SEND_COMMAND(REG_RAM_VADDR_END, x+width); /* x_end */ |
188 | SLCD_SEND_COMMAND(0x200, x); /* set cursor at x_start */ | 189 | SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, x); /* set cursor at x_start */ |
189 | SLCD_SEND_COMMAND(0x201, y); /* set cursor at y_start */ | 190 | SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, y); /* set cursor at y_start */ |
190 | SLCD_SET_COMMAND(0x202); /* write data? */ | 191 | SLCD_SET_COMMAND(REG_RW_GRAM); /* write data to GRAM */ |
191 | } | 192 | } |
192 | 193 | ||
193 | void lcd_on(void) | 194 | void lcd_on(void) |