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-rw-r--r--firmware/export/imx31l.h1
-rw-r--r--firmware/export/system.h4
2 files changed, 5 insertions, 0 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index ea92d059cc..3f3a0140c8 100644
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -37,6 +37,7 @@
37#define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE) 37#define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
38#define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR)) 38#define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
39 39
40#define CACHEALIGN_BITS 5
40#define CACHEALIGN_SIZE 32 41#define CACHEALIGN_SIZE 32
41#define NOCACHE_BASE CSD0_BASE_ADDR 42#define NOCACHE_BASE CSD0_BASE_ADDR
42 43
diff --git a/firmware/export/system.h b/firmware/export/system.h
index 3984ebeb11..bd31c03028 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -295,10 +295,14 @@ static inline void cpucache_flush(void)
295} 295}
296#endif 296#endif
297 297
298#ifndef CACHEALIGN_SIZE /* could be elsewhere for a particular reason */
298#ifdef CACHEALIGN_BITS 299#ifdef CACHEALIGN_BITS
299/* 2^CACHEALIGN_BITS = the byte size */ 300/* 2^CACHEALIGN_BITS = the byte size */
300#define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS) 301#define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS)
302#else
303#define CACHEALIGN_SIZE sizeof(int)
301#endif 304#endif
305#endif /* CACHEALIGN_SIZE */
302 306
303#ifdef PROC_NEEDS_CACHEALIGN 307#ifdef PROC_NEEDS_CACHEALIGN
304/* Cache alignment attributes and sizes are enabled */ 308/* Cache alignment attributes and sizes are enabled */