diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/config-ipodnano2g.h | 2 | ||||
-rw-r--r-- | firmware/export/s5l8700.h | 14 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/system-target.h | 7 |
3 files changed, 15 insertions, 8 deletions
diff --git a/firmware/export/config-ipodnano2g.h b/firmware/export/config-ipodnano2g.h index a10af32710..59ab28cc21 100644 --- a/firmware/export/config-ipodnano2g.h +++ b/firmware/export/config-ipodnano2g.h | |||
@@ -151,7 +151,7 @@ | |||
151 | #define FLASH_SIZE 0x400000 | 151 | #define FLASH_SIZE 0x400000 |
152 | 152 | ||
153 | /* Define this to the CPU frequency */ | 153 | /* Define this to the CPU frequency */ |
154 | #define CPU_FREQ 192000000 | 154 | #define CPU_FREQ 191692800 |
155 | 155 | ||
156 | /* Define this if you have ATA power-off control */ | 156 | /* Define this if you have ATA power-off control */ |
157 | //#define HAVE_ATA_POWER_OFF | 157 | //#define HAVE_ATA_POWER_OFF |
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index dc03553984..a8341137ee 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
@@ -25,7 +25,7 @@ | |||
25 | #define REG16_PTR_T volatile uint16_t * | 25 | #define REG16_PTR_T volatile uint16_t * |
26 | #define REG32_PTR_T volatile uint32_t * | 26 | #define REG32_PTR_T volatile uint32_t * |
27 | 27 | ||
28 | #define TIMER_FREQ 48000000L | 28 | #define TIMER_FREQ 47923200L |
29 | 29 | ||
30 | /* 04. CALMADM2E */ | 30 | /* 04. CALMADM2E */ |
31 | 31 | ||
@@ -226,6 +226,12 @@ | |||
226 | #define DMACADDR7 (*(REG32_PTR_T)(0x384000EC)) /* Current memory address register for channel 7 */ | 226 | #define DMACADDR7 (*(REG32_PTR_T)(0x384000EC)) /* Current memory address register for channel 7 */ |
227 | #define DMACTCNT7 (*(REG32_PTR_T)(0x384000F0)) /* Current transfer count register for channel 7 */ | 227 | #define DMACTCNT7 (*(REG32_PTR_T)(0x384000F0)) /* Current transfer count register for channel 7 */ |
228 | #define DMACOM7 (*(REG32_PTR_T)(0x384000F4)) /* Channel 7 command register */ | 228 | #define DMACOM7 (*(REG32_PTR_T)(0x384000F4)) /* Channel 7 command register */ |
229 | #define DMABASE8 (*(REG32_PTR_T)(0x38400100)) /* Base address register for channel 8 */ | ||
230 | #define DMACON8 (*(REG32_PTR_T)(0x38400104)) /* Configuration register for channel 8 */ | ||
231 | #define DMATCNT8 (*(REG32_PTR_T)(0x38400108)) /* Transfer count register for channel 8 */ | ||
232 | #define DMACADDR8 (*(REG32_PTR_T)(0x3840010C)) /* Current memory address register for channel 8 */ | ||
233 | #define DMACTCNT8 (*(REG32_PTR_T)(0x38400110)) /* Current transfer count register for channel 8 */ | ||
234 | #define DMACOM8 (*(REG32_PTR_T)(0x38400114)) /* Channel 8 command register */ | ||
229 | #define DMAALLST (*(REG32_PTR_T)(0x38400180)) /* All channel status register */ | 235 | #define DMAALLST (*(REG32_PTR_T)(0x38400180)) /* All channel status register */ |
230 | #else | 236 | #else |
231 | #define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */ | 237 | #define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */ |
@@ -304,9 +310,9 @@ | |||
304 | #define TDDATA1 (*(REG32_PTR_T)(0x3C70006C)) /* Data1 Register */ | 310 | #define TDDATA1 (*(REG32_PTR_T)(0x3C70006C)) /* Data1 Register */ |
305 | #define TDPRE (*(REG32_PTR_T)(0x3C700070)) /* Pre-scale register */ | 311 | #define TDPRE (*(REG32_PTR_T)(0x3C700070)) /* Pre-scale register */ |
306 | #define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */ | 312 | #define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */ |
307 | #define FIVE_USEC_TIMER ((*(REG32_PTR_T)(0x3C700080) << 32) \ | 313 | #define FIVE_USEC_TIMER (((*(REG32_PTR_T)(0x3C700080)) << 32) \ |
308 | | *(REG32_PTR_T)(0x3C700084)) /* 64bit 5usec timer */ | 314 | | (*(REG32_PTR_T)(0x3C700084))) /* 64bit 5usec timer */ |
309 | #define USEC_TIMER (*(REG32_PTR_T)(0x3C700084) * 5) /* lower 32 bits of the above as a usec timer */ | 315 | #define USEC_TIMER ((*(REG32_PTR_T)(0x3C700084)) * 5) /* lower 32 bits of the above as a usec timer */ |
310 | 316 | ||
311 | /* 12. NAND FLASH CONTROLER */ | 317 | /* 12. NAND FLASH CONTROLER */ |
312 | #if CONFIG_CPU==S5L8701 | 318 | #if CONFIG_CPU==S5L8701 |
diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h index 8f10301563..81e5c7f7fd 100644 --- a/firmware/target/arm/s5l8700/system-target.h +++ b/firmware/target/arm/s5l8700/system-target.h | |||
@@ -24,9 +24,10 @@ | |||
24 | #include "system-arm.h" | 24 | #include "system-arm.h" |
25 | #include "mmu-target.h" | 25 | #include "mmu-target.h" |
26 | 26 | ||
27 | #define CPUFREQ_DEFAULT 32000000 | 27 | #define CPUFREQ_SLEEP 32768 |
28 | #define CPUFREQ_NORMAL 48000000 | 28 | #define CPUFREQ_DEFAULT 47923200 |
29 | #define CPUFREQ_MAX 192000000 | 29 | #define CPUFREQ_NORMAL 47923200 |
30 | #define CPUFREQ_MAX 191692800 | ||
30 | 31 | ||
31 | #define inl(a) (*(volatile unsigned long *) (a)) | 32 | #define inl(a) (*(volatile unsigned long *) (a)) |
32 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) | 33 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) |