diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/drivers/uda1380.c | 145 | ||||
-rw-r--r-- | firmware/export/uda1380.h | 161 |
2 files changed, 306 insertions, 0 deletions
diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c new file mode 100644 index 0000000000..e8b8c14399 --- /dev/null +++ b/firmware/drivers/uda1380.c | |||
@@ -0,0 +1,145 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2005 by Andy Young | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "lcd.h" | ||
20 | #include "cpu.h" | ||
21 | #include "kernel.h" | ||
22 | #include "thread.h" | ||
23 | #include "power.h" | ||
24 | #include "debug.h" | ||
25 | #include "system.h" | ||
26 | #include "sprintf.h" | ||
27 | #include "button.h" | ||
28 | #include "string.h" | ||
29 | #include "file.h" | ||
30 | #include "buffer.h" | ||
31 | |||
32 | #include "i2c-h100.h" | ||
33 | #include "uda1380.h" | ||
34 | |||
35 | /* ------------------------------------------------- */ | ||
36 | /* Local functions and variables */ | ||
37 | /* ------------------------------------------------- */ | ||
38 | |||
39 | int uda1380_write_reg(unsigned char reg, unsigned short value); | ||
40 | unsigned short uda1380_regs[0x30]; | ||
41 | |||
42 | /* Definition of a good (?) configuration to start with */ | ||
43 | /* Not enabling ADC for now.. */ | ||
44 | |||
45 | #define NUM_DEFAULT_REGS 13 | ||
46 | unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] = | ||
47 | { | ||
48 | REG_0, EN_DAC | EN_INT | EN_DEC | SYSCLK_256FS | WSPLL_25_50, | ||
49 | REG_I2S, I2S_IFMT_IIS, | ||
50 | REG_PWR, PON_PLL | PON_HP | PON_DAC | EN_AVC | PON_AVC | PON_BIAS, | ||
51 | REG_AMIX, AMIX_RIGHT(0x10) | AMIX_LEFT(0x10), /* 00=max, 3f=mute */ | ||
52 | REG_MASTER_VOL, MASTER_VOL_LEFT(0x7f) | MASTER_VOL_RIGHT(0x7f), /* 00=max, ff=mute */ | ||
53 | REG_MIX_VOL, MIX_VOL_CHANNEL_1(0) | MIX_VOL_CHANNEL_2(0xff), /* 00=max, ff=mute */ | ||
54 | REG_EQ, 0, | ||
55 | REG_MUTE, MUTE_CH2, /* Mute channel 2 (digital decimation filter) */ | ||
56 | REG_MIX_CTL, 0, | ||
57 | REG_DEC_VOL, 0, | ||
58 | REG_PGA, MUTE_ADC, | ||
59 | REG_ADC, SKIP_DCFIL, | ||
60 | REG_AGC, 0 | ||
61 | }; | ||
62 | |||
63 | /* Returns 0 if register was written or -1 if write failed */ | ||
64 | int uda1380_write_reg(unsigned char reg, unsigned short value) | ||
65 | { | ||
66 | unsigned char data[4]; | ||
67 | |||
68 | data[0] = UDA1380_ADDR; | ||
69 | data[1] = reg; | ||
70 | data[2] = value >> 8; | ||
71 | data[3] = value & 0xff; | ||
72 | |||
73 | if (i2c_write(1, data, 4) != 4) | ||
74 | { | ||
75 | DEBUGF("uda1380 error reg=0x%x", reg); | ||
76 | return -1; | ||
77 | } | ||
78 | |||
79 | uda1380_regs[reg] = value; | ||
80 | |||
81 | return 0; | ||
82 | } | ||
83 | |||
84 | /** | ||
85 | * Sets the master volume | ||
86 | * | ||
87 | * \param vol Range [0..255] 0=max, 255=mute | ||
88 | * | ||
89 | */ | ||
90 | int uda1380_setvol(int vol) | ||
91 | { | ||
92 | return uda1380_write_reg(REG_MASTER_VOL, | ||
93 | MASTER_VOL_LEFT(vol) | MASTER_VOL_RIGHT(vol)); | ||
94 | } | ||
95 | |||
96 | /** | ||
97 | * Mute (mute=1) or enable sound (mute=0) | ||
98 | * | ||
99 | */ | ||
100 | int uda1380_mute(int mute) | ||
101 | { | ||
102 | unsigned int value = uda1380_regs[REG_MUTE]; | ||
103 | |||
104 | if (mute) | ||
105 | value = value | MUTE_MASTER; | ||
106 | else | ||
107 | value = value & ~MUTE_MASTER; | ||
108 | |||
109 | return uda1380_write_reg(REG_MUTE, value); | ||
110 | } | ||
111 | |||
112 | /* Returns 0 if successful or -1 if some register failed */ | ||
113 | int uda1380_set_regs(void) | ||
114 | { | ||
115 | int i; | ||
116 | memset(uda1380_regs, 0, sizeof(uda1380_regs)); | ||
117 | |||
118 | /* Initialize all registers */ | ||
119 | for (i=0; i<NUM_DEFAULT_REGS; i++) | ||
120 | { | ||
121 | unsigned char reg = uda1380_defaults[i*2+0]; | ||
122 | unsigned short value = uda1380_defaults[i*2+1]; | ||
123 | |||
124 | if (uda1380_write_reg(reg, value) == -1) | ||
125 | return -1; | ||
126 | } | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | /* Initialize UDA1380 codec with default register values (uda1380_defaults) */ | ||
132 | int uda1380_init(void) | ||
133 | { | ||
134 | if (uda1380_set_regs() == -1) | ||
135 | return -1; | ||
136 | |||
137 | return 0; | ||
138 | } | ||
139 | |||
140 | /* Nice shutdown of UDA1380 codec */ | ||
141 | void uda1380_close(void) | ||
142 | { | ||
143 | uda1380_write_reg(REG_PWR, 0); /* Disable power */ | ||
144 | uda1380_write_reg(REG_0, 0); /* Disable codec */ | ||
145 | } | ||
diff --git a/firmware/export/uda1380.h b/firmware/export/uda1380.h new file mode 100644 index 0000000000..2d560e537e --- /dev/null +++ b/firmware/export/uda1380.h | |||
@@ -0,0 +1,161 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | /* | ||
21 | * Driver for UDA1380 Audio-Codec | ||
22 | * 2005-02-17 hubble@mochine.com | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | #ifndef _UDA1380_H | ||
27 | #define _UDA1380_H | ||
28 | |||
29 | extern int uda1380_init(void); | ||
30 | extern int uda1380_setvol(int vol); | ||
31 | extern int uda1380_mute(int mute); | ||
32 | extern void uda1380_close(void); | ||
33 | |||
34 | #define UDA1380_ADDR 0x30 | ||
35 | |||
36 | /* REG_0: Misc settings */ | ||
37 | #define REG_0 0x00 | ||
38 | |||
39 | #define EN_ADC (1 << 11) /* Enable ADC */ | ||
40 | #define EN_DEC (1 << 10) /* Enable Decimator */ | ||
41 | #define EN_DAC (1 << 9) /* Enable DAC */ | ||
42 | #define EN_INT (1 << 8) /* Enable Interpolator */ | ||
43 | #define ADC_CLK (1 << 5) /* ADC_CLK: WSPLL (1) SYSCLK (0) */ | ||
44 | #define DAC_CLK (1 << 4) /* DAC_CLK: WSPLL (1) SYSCLK (0) */ | ||
45 | |||
46 | /* SYSCLK freqency select */ | ||
47 | #define SYSCLK_256FS (0 << 2) | ||
48 | #define SYSCLK_384FS (1 << 2) | ||
49 | #define SYSCLK_512FS (2 << 2) | ||
50 | #define SYSCLK_768FS (3 << 2) | ||
51 | |||
52 | /* WSPLL Input frequency range (kHz) */ | ||
53 | #define WSPLL_625_125 (0 << 0) /* 6.25 - 12.5 */ | ||
54 | #define WSPLL_125_25 (1 << 0) /* 12.5 - 25 */ | ||
55 | #define WSPLL_25_50 (2 << 0) /* 25 - 50 */ | ||
56 | #define WSPLL_50_100 (3 << 0) /* 50 - 100 */ | ||
57 | |||
58 | |||
59 | /* REG_I2S: I2S settings */ | ||
60 | #define REG_I2S 0x01 | ||
61 | #define I2S_IFMT_IIS (0 << 8) | ||
62 | #define I2S_IFMT_LSB16 (1 << 8) | ||
63 | #define I2S_IFMT_LSB18 (2 << 8) | ||
64 | #define I2S_IFMT_LSB20 (3 << 8) | ||
65 | #define I2S_IFMT_MSB (5 << 8) | ||
66 | #define I2S_OFMT_IIS (0 << 0) | ||
67 | #define I2S_OFMT_LSB16 (1 << 0) | ||
68 | #define I2S_OFMT_LSB18 (2 << 0) | ||
69 | #define I2S_OFMT_LSB20 (3 << 0) | ||
70 | #define I2S_OFMT_LSB24 (4 << 0) | ||
71 | #define I2S_OFMT_MSB (5 << 0) | ||
72 | |||
73 | |||
74 | /* REG_PWR: Power control */ | ||
75 | #define REG_PWR 0x02 | ||
76 | #define PON_PLL (1 << 15) /* Power-on WSPLL */ | ||
77 | #define PON_HP (1 << 13) /* Power-on Headphone driver */ | ||
78 | #define PON_DAC (1 << 10) /* Power-on DAC */ | ||
79 | #define PON_BIAS (1 << 8) /* Power-on BIAS for ADC, AVC, FSDAC */ | ||
80 | #define EN_AVC (1 << 7) /* Enable analog mixer */ | ||
81 | #define PON_AVC (1 << 6) /* Power-on analog mixer */ | ||
82 | #define PON_LNA (1 << 4) /* Power-on LNA & SDC */ | ||
83 | #define PON_PGAL (1 << 3) /* Power-on PGA left */ | ||
84 | #define PON_ADCL (1 << 2) /* Power-on ADC left */ | ||
85 | #define PON_PGAR (1 << 1) /* Power-on PGA right */ | ||
86 | #define PON_ADCR (1 << 0) /* Power-on ADC right */ | ||
87 | |||
88 | |||
89 | /* REG_AMIX: Analog mixer */ | ||
90 | #define REG_AMIX 0x03 | ||
91 | #define AMIX_LEFT(x) (((x) & 0x3f) << 8) | ||
92 | #define AMIX_RIGHT(x) (((x) & 0x3f) << 0) | ||
93 | |||
94 | /* REG_HP: Headphone amp */ | ||
95 | #define REG_HP 0x04 | ||
96 | |||
97 | /* REG_MV: Master Volume control */ | ||
98 | #define REG_MASTER_VOL 0x10 | ||
99 | |||
100 | #define MASTER_VOL_RIGHT(x) (((x) & 0xff) << 8) | ||
101 | #define MASTER_VOL_LEFT(x) (((x) & 0xff) << 0) | ||
102 | |||
103 | /* REG_MIX: Mixer volume control */ | ||
104 | /* Channel 1 is from digital data from I2S */ | ||
105 | /* Channel 2 is from decimation filter */ | ||
106 | |||
107 | #define REG_MIX_VOL 0x11 | ||
108 | #define MIX_VOL_CHANNEL_1(x) (((x) & 0xff) << 0) | ||
109 | #define MIX_VOL_CHANNEL_2(x) (((x) & 0xff) << 8) | ||
110 | |||
111 | /* REG_EQ: Bass boost and tremble */ | ||
112 | #define REG_EQ 0x12 | ||
113 | |||
114 | /* REG_MUTE: Master Mute */ | ||
115 | #define REG_MUTE 0x13 | ||
116 | #define MUTE_MASTER (1 << 14) /* Master Mute (soft) */ | ||
117 | #define MUTE_CH2 (1 << 11) /* Channel 2 mute */ | ||
118 | #define MUTE_CH1 (1 << 3) /* Channel 1 mute */ | ||
119 | |||
120 | /* REG_MIX_CTL: Mixer, silence detector and oversampling settings */ | ||
121 | #define REG_MIX_CTL 0x14 | ||
122 | #define MIX_CTL_MIX_POS (1 << 13) | ||
123 | #define MIX_CTL_MIX (1 << 12) | ||
124 | |||
125 | /* REG_DEC_VOL: Decimator Volume control */ | ||
126 | #define REG_DEC_VOL 0x20 | ||
127 | |||
128 | /* REG_PGA: PGA settings and mute */ | ||
129 | #define REG_PGA 0x21 | ||
130 | #define MUTE_ADC (1 << 15) /* Mute ADC */ | ||
131 | |||
132 | /* REG_ADC: */ | ||
133 | #define REG_ADC 0x22 | ||
134 | |||
135 | /* REG_AGC: Attack / Gain */ | ||
136 | #define REG_AGC 0x23 | ||
137 | #define SKIP_DCFIL ( 1 << 1) | ||
138 | |||
139 | |||
140 | /* Audio tick interrupt */ | ||
141 | #define AUDIO_TICK_NUMBER 8 | ||
142 | #define AUDIO_TICK_BIT (1 << 8) | ||
143 | |||
144 | |||
145 | /* AUDIOGLOB bits */ | ||
146 | |||
147 | #define TICK_COUNT(x) ((x) << 3) | ||
148 | |||
149 | #define TICK_SOURCE_IIS1_TX 1 | ||
150 | #define TICK_SOURCE_IIS2_TX 2 | ||
151 | #define TICK_SOURCE_EBU_TX 3 | ||
152 | #define TICK_SOURCE_IIS1_RX 4 | ||
153 | #define TICK_SOURCE_IIS3_RX 5 | ||
154 | #define TICK_SOURCE_IIS4_RX 6 | ||
155 | #define TICK_SOURCE_EBU1_RX 7 | ||
156 | #define TICK_SOURCE_EBU2_RX (1 << 11) | ||
157 | |||
158 | |||
159 | |||
160 | |||
161 | #endif /* _UDA_1380_H */ | ||