diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/s5l8700/pcm-s5l8700.c | 34 |
1 files changed, 15 insertions, 19 deletions
diff --git a/firmware/target/arm/s5l8700/pcm-s5l8700.c b/firmware/target/arm/s5l8700/pcm-s5l8700.c index 75afbd3dc8..eb63bbacbd 100644 --- a/firmware/target/arm/s5l8700/pcm-s5l8700.c +++ b/firmware/target/arm/s5l8700/pcm-s5l8700.c | |||
@@ -51,17 +51,18 @@ static const struct div_entry { | |||
51 | int pdiv, mdiv, sdiv, cdiv; | 51 | int pdiv, mdiv, sdiv, cdiv; |
52 | } div_table[HW_NUM_FREQ] = { | 52 | } div_table[HW_NUM_FREQ] = { |
53 | #ifdef IPOD_NANO2G | 53 | #ifdef IPOD_NANO2G |
54 | [HW_FREQ_11] = { 2, 41, 5, 4}, | 54 | [HW_FREQ_11] = { 0, 41, 3, 8}, |
55 | [HW_FREQ_22] = { 2, 41, 4, 4}, | 55 | [HW_FREQ_22] = { 0, 41, 3, 4}, |
56 | [HW_FREQ_44] = { 2, 41, 3, 4}, | 56 | [HW_FREQ_44] = { 0, 41, 3, 2}, |
57 | [HW_FREQ_88] = { 2, 41, 2, 4}, | 57 | [HW_FREQ_88] = { 0, 41, 3, 1}, |
58 | [HW_FREQ_8 ] = { 2, 12, 3, 9}, | 58 | [HW_FREQ_8 ] = { 0, 2, 1, 9}, |
59 | [HW_FREQ_16] = { 2, 12, 2, 9}, | 59 | [HW_FREQ_16] = { 0, 2, 0, 9}, |
60 | [HW_FREQ_32] = { 2, 12, 1, 9}, | 60 | [HW_FREQ_32] = { 2, 2, 0, 9}, |
61 | [HW_FREQ_12] = { 2, 12, 4, 3}, | 61 | [HW_FREQ_64] = { 6, 2, 0, 9}, |
62 | [HW_FREQ_24] = { 2, 12, 3, 3}, | 62 | [HW_FREQ_12] = { 0, 2, 2, 3}, |
63 | [HW_FREQ_48] = { 2, 12, 2, 3}, | 63 | [HW_FREQ_24] = { 0, 2, 1, 3}, |
64 | [HW_FREQ_96] = { 2, 12, 1, 3}, | 64 | [HW_FREQ_48] = { 0, 2, 0, 3}, |
65 | [HW_FREQ_96] = { 2, 2, 0, 3}, | ||
65 | #else | 66 | #else |
66 | /* table of recommended PLL/MCLK dividers for mode 256Fs from the datasheet */ | 67 | /* table of recommended PLL/MCLK dividers for mode 256Fs from the datasheet */ |
67 | [HW_FREQ_11] = { 26, 189, 3, 8}, | 68 | [HW_FREQ_11] = { 26, 189, 3, 8}, |
@@ -173,19 +174,14 @@ static void pcm_dma_set_freq(enum hw_freq_indexes idx) | |||
173 | { | 174 | { |
174 | struct div_entry div = div_table[idx]; | 175 | struct div_entry div = div_table[idx]; |
175 | 176 | ||
176 | PLLCON &= ~4; | ||
177 | PLLCON &= ~0x10; | ||
178 | PLLCON &= 0x3f; | ||
179 | PLLCON |= 4; | ||
180 | |||
181 | /* configure PLL1 and MCLK for the desired sample rate */ | 177 | /* configure PLL1 and MCLK for the desired sample rate */ |
182 | PLL1PMS = (div.pdiv << 16) | | 178 | PLL1PMS = (div.pdiv << 16) | |
183 | (div.mdiv << 8) | | 179 | (div.mdiv << 8) | |
184 | (div.sdiv << 0); | 180 | (div.sdiv << 0); |
185 | PLL1LCNT = 7500; /* no idea what to put here */ | 181 | PLL1LCNT = 280; /* 150 microseconds */ |
186 | 182 | ||
187 | /* enable PLL1 and wait for lock */ | 183 | /* enable PLL1 and wait for lock */ |
188 | PLLCON |= (1 << 1); | 184 | PLLCON |= 1 << 1; |
189 | while ((PLLLOCK & (1 << 1)) == 0); | 185 | while ((PLLLOCK & (1 << 1)) == 0); |
190 | 186 | ||
191 | /* configure MCLK */ | 187 | /* configure MCLK */ |
@@ -234,7 +230,7 @@ void pcm_play_dma_init(void) | |||
234 | (0 << 13) | /* 0 = basic I2S format */ | 230 | (0 << 13) | /* 0 = basic I2S format */ |
235 | (0 << 12) | /* 0 = MSB first */ | 231 | (0 << 12) | /* 0 = MSB first */ |
236 | (0 << 11) | /* 0 = left channel for low polarity */ | 232 | (0 << 11) | /* 0 = left channel for low polarity */ |
237 | (5 << 8) | /* MCLK divider */ | 233 | (3 << 8) | /* MCLK divider */ |
238 | (0 << 5) | /* 0 = 16-bit */ | 234 | (0 << 5) | /* 0 = 16-bit */ |
239 | (2 << 3) | /* bit clock per frame */ | 235 | (2 << 3) | /* bit clock per frame */ |
240 | (1 << 0); /* channel index */ | 236 | (1 << 0); /* channel index */ |