diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/config.h | 17 | ||||
-rw-r--r-- | firmware/export/config/ipodnano2g.h | 1 | ||||
-rw-r--r-- | firmware/export/system.h | 18 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/system-target.h | 5 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 5 |
5 files changed, 28 insertions, 18 deletions
diff --git a/firmware/export/config.h b/firmware/export/config.h index e678590b44..9d8dc41111 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h | |||
@@ -914,23 +914,6 @@ Lyre prototype 1 */ | |||
914 | 914 | ||
915 | #endif /* HAVE_USBSTACK */ | 915 | #endif /* HAVE_USBSTACK */ |
916 | 916 | ||
917 | /* Storage alignment: the mask specifies a mask of bits which should be | ||
918 | * clear in addresses used for storage_{read,write}_sectors(). This is | ||
919 | * only relevant for buffers that will contain one or more whole sectors. | ||
920 | */ | ||
921 | |||
922 | /* PP502x DMA requires an alignment of at least 16 bytes */ | ||
923 | #ifdef HAVE_ATA_DMA | ||
924 | #ifdef CPU_PP502x | ||
925 | #define STORAGE_ALIGN_MASK 15 | ||
926 | #endif | ||
927 | #endif /* HAVE_ATA_DMA */ | ||
928 | |||
929 | /* by default no alignment is required */ | ||
930 | #ifndef STORAGE_ALIGN_MASK | ||
931 | #define STORAGE_ALIGN_MASK 0 | ||
932 | #endif | ||
933 | |||
934 | /* This attribute can be used to enable to detection of plugin file handles leaks. | 917 | /* This attribute can be used to enable to detection of plugin file handles leaks. |
935 | * When enabled, the plugin core will monitor open/close/creat and when the plugin exits | 918 | * When enabled, the plugin core will monitor open/close/creat and when the plugin exits |
936 | * will display an error message if the plugin leaked some file handles */ | 919 | * will display an error message if the plugin leaked some file handles */ |
diff --git a/firmware/export/config/ipodnano2g.h b/firmware/export/config/ipodnano2g.h index 0b690416a7..989d56338d 100644 --- a/firmware/export/config/ipodnano2g.h +++ b/firmware/export/config/ipodnano2g.h | |||
@@ -219,6 +219,5 @@ | |||
219 | //#define IPOD_ACCESSORY_PROTOCOL | 219 | //#define IPOD_ACCESSORY_PROTOCOL |
220 | //#define HAVE_SERIAL | 220 | //#define HAVE_SERIAL |
221 | 221 | ||
222 | #define STORAGE_ALIGN_MASK 15 | ||
223 | #define USB_WRITE_BUFFER_SIZE (1024*64) | 222 | #define USB_WRITE_BUFFER_SIZE (1024*64) |
224 | 223 | ||
diff --git a/firmware/export/system.h b/firmware/export/system.h index 505b167af9..fee188802b 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h | |||
@@ -312,6 +312,16 @@ static inline void cpucache_flush(void) | |||
312 | /* Aligns a buffer pointer and size to proper boundaries */ | 312 | /* Aligns a buffer pointer and size to proper boundaries */ |
313 | #define CACHEALIGN_BUFFER(start, size) \ | 313 | #define CACHEALIGN_BUFFER(start, size) \ |
314 | ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) | 314 | ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) |
315 | /* Pad a size so the buffer can be aligned later */ | ||
316 | #define CACHE_PAD(x) ((x) + CACHEALIGN_SIZE - 1) | ||
317 | /* Number of bytes in the last cacheline assuming buffer of size x is aligned */ | ||
318 | #define CACHE_OVERLAP(x) (x & (CACHEALIGN_SIZE - 1)) | ||
319 | |||
320 | #ifdef NEEDS_STORAGE_ALIGN | ||
321 | #define STORAGE_ALIGN_DOWN(x) CACHEALIGN_DOWN(x) | ||
322 | #define STORAGE_PAD(x) CACHE_PAD(x) | ||
323 | #define STORAGE_OVERLAP(x) CACHE_OVERLAP(x) | ||
324 | #endif | ||
315 | 325 | ||
316 | #else /* ndef PROC_NEEDS_CACHEALIGN */ | 326 | #else /* ndef PROC_NEEDS_CACHEALIGN */ |
317 | 327 | ||
@@ -323,9 +333,17 @@ static inline void cpucache_flush(void) | |||
323 | #define CACHEALIGN_DOWN(x) (x) | 333 | #define CACHEALIGN_DOWN(x) (x) |
324 | /* Make no adjustments */ | 334 | /* Make no adjustments */ |
325 | #define CACHEALIGN_BUFFER(start, size) | 335 | #define CACHEALIGN_BUFFER(start, size) |
336 | #define CACHE_PAD(x) (x) | ||
337 | #define CACHE_OVERLAP(x) 0 | ||
326 | 338 | ||
327 | #endif /* PROC_NEEDS_CACHEALIGN */ | 339 | #endif /* PROC_NEEDS_CACHEALIGN */ |
328 | 340 | ||
341 | #if !defined(PROC_NEEDS_CACHEALIGN) || !defined(NEEDS_STORAGE_ALIGN) | ||
342 | #define STORAGE_ALIGN_DOWN(x) (x) | ||
343 | #define STORAGE_PAD(x) (x) | ||
344 | #define STORAGE_OVERLAP(x) 0 | ||
345 | #endif | ||
346 | |||
329 | /* Double-cast to avoid 'dereferencing type-punned pointer will | 347 | /* Double-cast to avoid 'dereferencing type-punned pointer will |
330 | * break strict aliasing rules' B.S. */ | 348 | * break strict aliasing rules' B.S. */ |
331 | #define PUN_PTR(type, p) ((type)(intptr_t)(p)) | 349 | #define PUN_PTR(type, p) ((type)(intptr_t)(p)) |
diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h index 81e5c7f7fd..c531344b64 100644 --- a/firmware/target/arm/s5l8700/system-target.h +++ b/firmware/target/arm/s5l8700/system-target.h | |||
@@ -29,6 +29,11 @@ | |||
29 | #define CPUFREQ_NORMAL 47923200 | 29 | #define CPUFREQ_NORMAL 47923200 |
30 | #define CPUFREQ_MAX 191692800 | 30 | #define CPUFREQ_MAX 191692800 |
31 | 31 | ||
32 | /* DMA engine needs aligned addresses */ | ||
33 | #define PROC_NEEDS_CACHEALIGN | ||
34 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ | ||
35 | #define NEEDS_STORAGE_ALIGN | ||
36 | |||
32 | #define inl(a) (*(volatile unsigned long *) (a)) | 37 | #define inl(a) (*(volatile unsigned long *) (a)) |
33 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) | 38 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) |
34 | #define inb(a) (*(volatile unsigned char *) (a)) | 39 | #define inb(a) (*(volatile unsigned char *) (a)) |
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 764cd18d15..1422e6467a 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -22,6 +22,7 @@ | |||
22 | #ifndef SYSTEM_TARGET_H | 22 | #ifndef SYSTEM_TARGET_H |
23 | #define SYSTEM_TARGET_H | 23 | #define SYSTEM_TARGET_H |
24 | 24 | ||
25 | #include "config.h" | ||
25 | #include "system-arm.h" | 26 | #include "system-arm.h" |
26 | 27 | ||
27 | #ifdef CPU_PP | 28 | #ifdef CPU_PP |
@@ -162,6 +163,10 @@ static inline void wake_core(int core) | |||
162 | #define PROC_NEEDS_CACHEALIGN | 163 | #define PROC_NEEDS_CACHEALIGN |
163 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ | 164 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ |
164 | 165 | ||
166 | #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) | ||
167 | #define NEEDS_STORAGE_ALIGN | ||
168 | #endif | ||
169 | |||
165 | /** cache functions **/ | 170 | /** cache functions **/ |
166 | #ifndef BOOTLOADER | 171 | #ifndef BOOTLOADER |
167 | #define HAVE_CPUCACHE_INVALIDATE | 172 | #define HAVE_CPUCACHE_INVALIDATE |