diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525.c | 90 |
1 files changed, 67 insertions, 23 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525.c b/firmware/target/arm/as3525/usb-drv-as3525.c index f50713efbb..580c866c22 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525.c +++ b/firmware/target/arm/as3525/usb-drv-as3525.c | |||
@@ -129,6 +129,21 @@ typedef struct { | |||
129 | /* USER_CONF5 seems to the same as USBt least on read */ | 129 | /* USER_CONF5 seems to the same as USBt least on read */ |
130 | #define USB_USER_CONF5 USB_REG(0x2024) | 130 | #define USB_USER_CONF5 USB_REG(0x2024) |
131 | 131 | ||
132 | #define USB_CSR_NUM_MASK 0x0000000f | ||
133 | #define USB_CSR_DIR_MASK 0x00000010 | ||
134 | #define USB_CSR_DIR_IN 0x00000010 | ||
135 | #define USB_CSR_DIR_OUT 0x00000000 | ||
136 | #define USB_CSR_TYPE_MASK 0x00000060 | ||
137 | #define USB_CSR_TYPE_CTL 0x00000000 | ||
138 | #define USB_CSR_TYPE_ISO 0x00000020 | ||
139 | #define USB_CSR_TYPE_BULK 0x00000040 | ||
140 | #define USB_CSR_TYPE_INT 0x00000060 | ||
141 | #define USB_CSR_CFG_MASK 0x00000780 | ||
142 | #define USB_CSR_INTF_MASK 0x00007800 | ||
143 | #define USB_CSR_ALT_MASK 0x00078000 | ||
144 | #define USB_CSR_MAXPKT_MASK 0x3ff80000 | ||
145 | #define USB_CSR_ISOMULT_MASK 0xc0000000 | ||
146 | |||
132 | /* write bits 31..16 */ | 147 | /* write bits 31..16 */ |
133 | #define USB_GPIO_IDDIG_SEL (1<<30) | 148 | #define USB_GPIO_IDDIG_SEL (1<<30) |
134 | #define USB_GPIO_FS_DATA_EXT (1<<29) | 149 | #define USB_GPIO_FS_DATA_EXT (1<<29) |
@@ -153,16 +168,24 @@ typedef struct { | |||
153 | 168 | ||
154 | /* Device Control Register and bit fields */ | 169 | /* Device Control Register and bit fields */ |
155 | #define USB_DEV_CTRL_REMOTE_WAKEUP 0x00000001 // set remote wake-up signal | 170 | #define USB_DEV_CTRL_REMOTE_WAKEUP 0x00000001 // set remote wake-up signal |
171 | #define USB_DEV_CTRL_RESERVED0 0x00000002 // reserved, ro, read as 0 | ||
156 | #define USB_DEV_CTRL_RDE 0x00000004 // receive dma enable | 172 | #define USB_DEV_CTRL_RDE 0x00000004 // receive dma enable |
157 | #define USB_DEV_CTRL_DESC_UPDATE 0x00000010 // descriptor update | 173 | #define USB_DEV_CTRL_TDE 0x00000008 // transmit dma enable |
174 | #define USB_DEV_CTRL_DESC_UPDATE 0x00000010 // update desc after dma | ||
175 | #define USB_DEV_CTRL_BE 0x00000020 // big endian when set (ro) | ||
176 | #define USB_DEV_CTRL_BUFFER_FULL 0x00000040 | ||
158 | #define USB_DEV_CTRL_THRES_ENABLE 0x00000080 // threshold enable | 177 | #define USB_DEV_CTRL_THRES_ENABLE 0x00000080 // threshold enable |
159 | #define USB_DEV_CTRL_BURST_CONTROL 0x00000100 // burst control | 178 | #define USB_DEV_CTRL_BURST_ENABLE 0x00000100 // ahb burst enable |
179 | #define USB_DEV_CTRL_MODE 0x00000200 // 0=slave, 1=dma | ||
160 | #define USB_DEV_CTRL_SOFT_DISCONN 0x00000400 // soft disconnect | 180 | #define USB_DEV_CTRL_SOFT_DISCONN 0x00000400 // soft disconnect |
161 | #define USB_DEV_CTRL_APCSR_DONE 0x00002000 // app Prog CSR Done | 181 | #define USB_DEV_CTRL_SCALEDOWN 0x00000800 // for simulation speedup |
182 | #define USB_DEV_CTRL_DEVNAK 0x00001000 // set nak on all OUT EPs | ||
183 | #define USB_DEV_CTRL_APCSR_DONE 0x00002000 // set to signal CSR update | ||
162 | #define USB_DEV_CTRL_MASK_BURST_LEN 0x000f0000 // mask for burst length | 184 | #define USB_DEV_CTRL_MASK_BURST_LEN 0x000f0000 // mask for burst length |
163 | #define USB_DEV_CTRL_MASK_THRESHOLD_LEN 0xff000000 // mask for threshold length | 185 | #define USB_DEV_CTRL_MASK_THRESHOLD_LEN 0xff000000 // mask for threshold length |
164 | 186 | ||
165 | /* settings of burst length for maskBurstLen_c field */ | 187 | /* settings of burst length for maskBurstLen_c field */ |
188 | /* amd 5536 datasheet: (BLEN+1) dwords */ | ||
166 | #define USB_DEV_CTRL_BLEN_1DWORD 0x00000000 | 189 | #define USB_DEV_CTRL_BLEN_1DWORD 0x00000000 |
167 | #define USB_DEV_CTRL_BLEN_2DWORDS 0x00010000 | 190 | #define USB_DEV_CTRL_BLEN_2DWORDS 0x00010000 |
168 | #define USB_DEV_CTRL_BLEN_4DWORDS 0x00020000 | 191 | #define USB_DEV_CTRL_BLEN_4DWORDS 0x00020000 |
@@ -175,6 +198,7 @@ typedef struct { | |||
175 | #define USB_DEV_CTRL_BLEN_512DWORDS 0x00090000 | 198 | #define USB_DEV_CTRL_BLEN_512DWORDS 0x00090000 |
176 | 199 | ||
177 | /* settings of threshold length for maskThresholdLen_c field */ | 200 | /* settings of threshold length for maskThresholdLen_c field */ |
201 | /* amd 5536 datasheet: (TLEN+1) dwords */ | ||
178 | #define USB_DEV_CTRL_TLEN_1DWORD 0x00000000 | 202 | #define USB_DEV_CTRL_TLEN_1DWORD 0x00000000 |
179 | #define USB_DEV_CTRL_TLEN_HALFMAXSIZE 0x01000000 | 203 | #define USB_DEV_CTRL_TLEN_HALFMAXSIZE 0x01000000 |
180 | #define USB_DEV_CTRL_TLEN_4THMAXSIZE 0x02000000 | 204 | #define USB_DEV_CTRL_TLEN_4THMAXSIZE 0x02000000 |
@@ -193,6 +217,15 @@ typedef struct { | |||
193 | #define USB_DEV_CFG_BI_DIR 0x00000040 | 217 | #define USB_DEV_CFG_BI_DIR 0x00000040 |
194 | #define USB_DEV_CFG_STAT_ACK 0x00000000 | 218 | #define USB_DEV_CFG_STAT_ACK 0x00000000 |
195 | #define USB_DEV_CFG_STAT_STALL 0x00000080 | 219 | #define USB_DEV_CFG_STAT_STALL 0x00000080 |
220 | #define USB_DEV_CFG_PHY_ERR_DETECT 0x00000200 /* monitor phy for errors */ | ||
221 | #define USB_DEV_CFG_HALT_STAT 0x00010000 /* ENDPOINT_HALT supported */ | ||
222 | /* 0: ACK, 1: STALL */ | ||
223 | #define USB_DEV_CFG_CSR_PRG 0x00020000 | ||
224 | #define USB_DEV_CFG_SET_DESC 0x00040000 /* SET_DESCRIPTOR supported */ | ||
225 | /* 0: STALL, 1: pass on setup packet */ | ||
226 | #define USB_DEV_CFG_DMA_RESET 0x20000000 | ||
227 | #define USB_DEV_CFG_HNPSFEN 0x40000000 | ||
228 | #define USB_DEV_CFG_SOFT_RESET 0x80000000 | ||
196 | 229 | ||
197 | /* Device Status Register and bit fields */ | 230 | /* Device Status Register and bit fields */ |
198 | #define USB_DEV_STS_MASK_CFG 0x0000000f | 231 | #define USB_DEV_STS_MASK_CFG 0x0000000f |
@@ -204,6 +237,8 @@ typedef struct { | |||
204 | #define USB_DEV_STS_SPD_FS 0x00002000 | 237 | #define USB_DEV_STS_SPD_FS 0x00002000 |
205 | #define USB_DEV_STS_SPD_LS 0x00004000 | 238 | #define USB_DEV_STS_SPD_LS 0x00004000 |
206 | #define USB_DEV_STS_RXF_EMPTY 0x00008000 | 239 | #define USB_DEV_STS_RXF_EMPTY 0x00008000 |
240 | #define USB_DEV_STS_PHY_ERROR 0x00010000 | ||
241 | #define USB_DEV_STS_SESSVLD 0x00020000 /* session valid (vbus>1.2V) */ | ||
207 | #define USB_DEV_STS_MASK_FRM_NUM 0xfffc0000 /* SOF frame number */ | 242 | #define USB_DEV_STS_MASK_FRM_NUM 0xfffc0000 /* SOF frame number */ |
208 | 243 | ||
209 | 244 | ||
@@ -215,8 +250,7 @@ typedef struct { | |||
215 | #define USB_DEV_INTR_USB_SUSPEND 0x00000010 /* usb bus suspend req */ | 250 | #define USB_DEV_INTR_USB_SUSPEND 0x00000010 /* usb bus suspend req */ |
216 | #define USB_DEV_INTR_SOF 0x00000020 /* SOF seen on bus */ | 251 | #define USB_DEV_INTR_SOF 0x00000020 /* SOF seen on bus */ |
217 | #define USB_DEV_INTR_ENUM_DONE 0x00000040 /* usb speed enum done */ | 252 | #define USB_DEV_INTR_ENUM_DONE 0x00000040 /* usb speed enum done */ |
218 | #define USB_DEV_INTR_OTG 0x00000080 /* otg status change? */ | 253 | #define USB_DEV_INTR_SVC 0x00000080 /* USB_DEV_STS changed */ |
219 | #define USB_DEV_INTR_BUSERR 0x00000080 /* AHB DMA error */ | ||
220 | 254 | ||
221 | /* EP Control Register Fields */ | 255 | /* EP Control Register Fields */ |
222 | #define USB_EP_CTRL_STALL 0x00000001 | 256 | #define USB_EP_CTRL_STALL 0x00000001 |
@@ -445,10 +479,10 @@ static void reset_endpoints(int init) | |||
445 | 479 | ||
446 | dma_desc_init(i, 0); | 480 | dma_desc_init(i, 0); |
447 | USB_IEP_CTRL (i) = USB_EP_CTRL_FLUSH|USB_EP_CTRL_SNAK; | 481 | USB_IEP_CTRL (i) = USB_EP_CTRL_FLUSH|USB_EP_CTRL_SNAK; |
448 | USB_IEP_MPS (i) = mps; | 482 | USB_IEP_MPS (i) = mps; /* in bytes */ |
449 | /* We don't care about the 'IN token received' event */ | 483 | /* We don't care about the 'IN token received' event */ |
450 | USB_IEP_STS_MASK(i) = USB_EP_STAT_IN; /* OF: 0x840 */ | 484 | USB_IEP_STS_MASK(i) = USB_EP_STAT_IN; /* OF: 0x840 */ |
451 | USB_IEP_TXFSIZE (i) = mps/2; | 485 | USB_IEP_TXFSIZE (i) = mps/2; /* in dwords => mps*2 bytes */ |
452 | USB_IEP_STS (i) = 0xffffffff; /* clear status */ | 486 | USB_IEP_STS (i) = 0xffffffff; /* clear status */ |
453 | USB_IEP_DESC_PTR(i) = 0; | 487 | USB_IEP_DESC_PTR(i) = 0; |
454 | 488 | ||
@@ -500,19 +534,20 @@ void usb_drv_init(void) | |||
500 | usb_phy_suspend(); | 534 | usb_phy_suspend(); |
501 | USB_DEV_CTRL |= USB_DEV_CTRL_SOFT_DISCONN; | 535 | USB_DEV_CTRL |= USB_DEV_CTRL_SOFT_DISCONN; |
502 | 536 | ||
503 | /* We don't care about OTG or SOF events */ | 537 | /* We don't care about SVC or SOF events */ |
504 | /* Right now we don't handle suspend or reset, so mask those too */ | 538 | /* Right now we don't handle suspend, so mask those too */ |
505 | USB_DEV_INTR_MASK = USB_DEV_INTR_OTG | | 539 | USB_DEV_INTR_MASK = USB_DEV_INTR_SVC | |
506 | USB_DEV_INTR_SOF | | 540 | USB_DEV_INTR_SOF | |
507 | USB_DEV_INTR_USB_SUSPEND | | 541 | USB_DEV_INTR_USB_SUSPEND | |
508 | USB_DEV_INTR_EARLY_SUSPEND; | 542 | USB_DEV_INTR_EARLY_SUSPEND; |
509 | 543 | ||
510 | USB_DEV_CFG = USB_DEV_CFG_STAT_ACK | | 544 | USB_DEV_CFG = USB_DEV_CFG_STAT_ACK | |
511 | USB_DEV_CFG_UNI_DIR | | 545 | USB_DEV_CFG_UNI_DIR | |
512 | USB_DEV_CFG_PI_16BIT | | 546 | USB_DEV_CFG_PI_16BIT | |
513 | USB_DEV_CFG_HS | | 547 | USB_DEV_CFG_HS | |
514 | USB_DEV_CFG_SELF_POWERED | | 548 | USB_DEV_CFG_SELF_POWERED | |
515 | 0x20200; | 549 | USB_DEV_CFG_CSR_PRG | |
550 | USB_DEV_CFG_PHY_ERR_DETECT; | ||
516 | 551 | ||
517 | USB_DEV_CTRL = USB_DEV_CTRL_BLEN_1DWORD | | 552 | USB_DEV_CTRL = USB_DEV_CTRL_BLEN_1DWORD | |
518 | USB_DEV_CTRL_DESC_UPDATE | | 553 | USB_DEV_CTRL_DESC_UPDATE | |
@@ -694,7 +729,6 @@ char *make_hex(char *data, int len) | |||
694 | void ep_send(int ep, void *ptr, int len) | 729 | void ep_send(int ep, void *ptr, int len) |
695 | { | 730 | { |
696 | struct usb_dev_dma_desc *uc_desc = endpoints[ep][0].uc_desc; | 731 | struct usb_dev_dma_desc *uc_desc = endpoints[ep][0].uc_desc; |
697 | int i; | ||
698 | 732 | ||
699 | endpoints[ep][0].state |= EP_STATE_BUSY; | 733 | endpoints[ep][0].state |= EP_STATE_BUSY; |
700 | endpoints[ep][0].len = len; | 734 | endpoints[ep][0].len = len; |
@@ -756,7 +790,6 @@ static void handle_in_ep(int ep) | |||
756 | } | 790 | } |
757 | 791 | ||
758 | if (ep_sts & USB_EP_STAT_TDC) { | 792 | if (ep_sts & USB_EP_STAT_TDC) { |
759 | USB_IEP_CTRL(ep) |= USB_EP_CTRL_FLUSH; | ||
760 | endpoints[ep][0].state &= ~EP_STATE_BUSY; | 793 | endpoints[ep][0].state &= ~EP_STATE_BUSY; |
761 | endpoints[ep][0].rc = 0; | 794 | endpoints[ep][0].rc = 0; |
762 | logf("EP%d %x %stx done len %x stat %08x\n", | 795 | logf("EP%d %x %stx done len %x stat %08x\n", |
@@ -925,6 +958,10 @@ void INT_USB(void) | |||
925 | logf("sof\n"); | 958 | logf("sof\n"); |
926 | intr &= ~USB_DEV_INTR_SOF; | 959 | intr &= ~USB_DEV_INTR_SOF; |
927 | } | 960 | } |
961 | if (intr & USB_DEV_INTR_SVC) {/* device status changed */ | ||
962 | logf("svc: %08x otg: %08x\n", (int)USB_DEV_STS, (int)USB_OTG_CSR); | ||
963 | intr &= ~USB_DEV_INTR_SVC; | ||
964 | } | ||
928 | if (intr & USB_DEV_INTR_ENUM_DONE) {/* speed enumeration complete */ | 965 | if (intr & USB_DEV_INTR_ENUM_DONE) {/* speed enumeration complete */ |
929 | int spd = USB_DEV_STS & USB_DEV_STS_MASK_SPD; /* Enumerated Speed */ | 966 | int spd = USB_DEV_STS & USB_DEV_STS_MASK_SPD; /* Enumerated Speed */ |
930 | 967 | ||
@@ -933,16 +970,23 @@ void INT_USB(void) | |||
933 | if (spd == USB_DEV_STS_SPD_FS) logf("fs\n"); | 970 | if (spd == USB_DEV_STS_SPD_FS) logf("fs\n"); |
934 | if (spd == USB_DEV_STS_SPD_LS) logf("ls\n"); | 971 | if (spd == USB_DEV_STS_SPD_LS) logf("ls\n"); |
935 | 972 | ||
936 | USB_PHY_EP0_INFO = 0x00200000; | 973 | USB_PHY_EP0_INFO = 0x00200000 | |
974 | USB_CSR_DIR_OUT | | ||
975 | USB_CSR_TYPE_CTL; | ||
976 | USB_PHY_EP1_INFO = 0x00200000 | | ||
977 | USB_CSR_DIR_IN | | ||
978 | USB_CSR_TYPE_CTL; | ||
979 | USB_PHY_EP2_INFO = 0x00200001 | | ||
980 | USB_CSR_DIR_IN | | ||
981 | USB_CSR_TYPE_BULK; | ||
982 | USB_PHY_EP3_INFO = 0x00200001 | | ||
983 | USB_CSR_DIR_IN | | ||
984 | USB_CSR_TYPE_BULK; | ||
937 | USB_DEV_CTRL |= USB_DEV_CTRL_APCSR_DONE; | 985 | USB_DEV_CTRL |= USB_DEV_CTRL_APCSR_DONE; |
938 | USB_IEP_CTRL(0) |= USB_EP_CTRL_ACT; | 986 | USB_IEP_CTRL(0) |= USB_EP_CTRL_ACT; |
939 | USB_OEP_CTRL(0) |= USB_EP_CTRL_ACT; | 987 | USB_OEP_CTRL(0) |= USB_EP_CTRL_ACT; |
940 | intr &= ~USB_DEV_INTR_ENUM_DONE; | 988 | intr &= ~USB_DEV_INTR_ENUM_DONE; |
941 | } | 989 | } |
942 | if (intr & USB_DEV_INTR_BUSERR) { | ||
943 | panicf("usb dma bus error"); | ||
944 | intr &= ~USB_DEV_INTR_BUSERR; | ||
945 | } | ||
946 | if (intr) | 990 | if (intr) |
947 | panicf("usb devirq 0x%x", intr); | 991 | panicf("usb devirq 0x%x", intr); |
948 | } | 992 | } |