diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/dm320.h | 142 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/kernel-mr500.c | 15 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/system-mr500.c | 28 | ||||
-rwxr-xr-x | firmware/target/arm/olympus/mrobe-500/system-target.h | 32 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/timer-mr500.c | 58 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 5 |
7 files changed, 180 insertions, 102 deletions
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index f072e8975f..70992b715d 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h | |||
@@ -5,7 +5,7 @@ | |||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: $ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2007 by Karl Kurbjun | 10 | * Copyright (C) 2007 by Karl Kurbjun |
11 | * | 11 | * |
@@ -30,33 +30,33 @@ | |||
30 | #define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr))) | 30 | #define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr))) |
31 | 31 | ||
32 | /* Timer 0-3 */ | 32 | /* Timer 0-3 */ |
33 | #define IO_TIMER0_TMMD 0x0000 | 33 | #define IO_TIMER0_TMMD DM320_REG(0x0000) |
34 | #define IO_TIMER0_TMRSV0 0x0002 | 34 | #define IO_TIMER0_TMRSV0 DM320_REG(0x0002) |
35 | #define IO_TIMER0_TMPRSCL 0x0004 | 35 | #define IO_TIMER0_TMPRSCL DM320_REG(0x0004) |
36 | #define IO_TIMER0_TMDIV 0x0006 | 36 | #define IO_TIMER0_TMDIV DM320_REG(0x0006) |
37 | #define IO_TIMER0_TMTRG 0x0008 | 37 | #define IO_TIMER0_TMTRG DM320_REG(0x0008) |
38 | #define IO_TIMER0_TMCNT 0x000A | 38 | #define IO_TIMER0_TMCNT DM320_REG(0x000A) |
39 | 39 | ||
40 | #define IO_TIMER1_TMMD 0x0080 | 40 | #define IO_TIMER1_TMMD DM320_REG(0x0080) |
41 | #define IO_TIMER1_TMRSV0 0x0082 | 41 | #define IO_TIMER1_TMRSV0 DM320_REG(0x0082) |
42 | #define IO_TIMER1_TMPRSCL 0x0084 | 42 | #define IO_TIMER1_TMPRSCL DM320_REG(0x0084) |
43 | #define IO_TIMER1_TMDIV 0x0086 | 43 | #define IO_TIMER1_TMDIV DM320_REG(0x0086) |
44 | #define IO_TIMER1_TMTRG 0x0088 | 44 | #define IO_TIMER1_TMTRG DM320_REG(0x0088) |
45 | #define IO_TIMER1_TMCNT 0x008A | 45 | #define IO_TIMER1_TMCNT DM320_REG(0x008A) |
46 | 46 | ||
47 | #define IO_TIMER2_TMMD 0x0100 | 47 | #define IO_TIMER2_TMMD DM320_REG(0x0100) |
48 | #define IO_TIMER2_TMVDCLR 0x0102 | 48 | #define IO_TIMER2_TMVDCLR DM320_REG(0x0102) |
49 | #define IO_TIMER2_TMPRSCL 0x0104 | 49 | #define IO_TIMER2_TMPRSCL DM320_REG(0x0104) |
50 | #define IO_TIMER2_TMDIV 0x0106 | 50 | #define IO_TIMER2_TMDIV DM320_REG(0x0106) |
51 | #define IO_TIMER2_TMTRG 0x0108 | 51 | #define IO_TIMER2_TMTRG DM320_REG(0x0108) |
52 | #define IO_TIMER2_TMCNT 0x010A | 52 | #define IO_TIMER2_TMCNT DM320_REG(0x010A) |
53 | 53 | ||
54 | #define IO_TIMER3_TMMD 0x0180 | 54 | #define IO_TIMER3_TMMD DM320_REG(0x0180) |
55 | #define IO_TIMER3_TMVDCLR 0x0182 | 55 | #define IO_TIMER3_TMVDCLR DM320_REG(0x0182) |
56 | #define IO_TIMER3_TMPRSCL 0x0184 | 56 | #define IO_TIMER3_TMPRSCL DM320_REG(0x0184) |
57 | #define IO_TIMER3_TMDIV 0x0186 | 57 | #define IO_TIMER3_TMDIV DM320_REG(0x0186) |
58 | #define IO_TIMER3_TMTRG 0x0188 | 58 | #define IO_TIMER3_TMTRG DM320_REG(0x0188) |
59 | #define IO_TIMER3_TMCNT 0x018A | 59 | #define IO_TIMER3_TMCNT DM320_REG(0x018A) |
60 | 60 | ||
61 | /* Serial 0/1 */ | 61 | /* Serial 0/1 */ |
62 | #define IO_SERIAL0_TX_DATA DM320_REG(0x0200) | 62 | #define IO_SERIAL0_TX_DATA DM320_REG(0x0200) |
@@ -144,30 +144,30 @@ | |||
144 | #define IO_SDIO_INT_STATUS 0x04D0 | 144 | #define IO_SDIO_INT_STATUS 0x04D0 |
145 | 145 | ||
146 | /* Interrupt Controller */ | 146 | /* Interrupt Controller */ |
147 | #define IO_INTC_FIQ0 0x0500 | 147 | #define IO_INTC_FIQ0 DM320_REG(0x0500) |
148 | #define IO_INTC_FIQ1 0x0502 | 148 | #define IO_INTC_FIQ1 DM320_REG(0x0502) |
149 | #define IO_INTC_FIQ2 0x0504 | 149 | #define IO_INTC_FIQ2 DM320_REG(0x0504) |
150 | #define IO_INTC_IRQ0 0x0508 | 150 | #define IO_INTC_IRQ0 DM320_REG(0x0508) |
151 | #define IO_INTC_IRQ1 0x050A | 151 | #define IO_INTC_IRQ1 DM320_REG(0x050A) |
152 | #define IO_INTC_IRQ2 0x050C | 152 | #define IO_INTC_IRQ2 DM320_REG(0x050C) |
153 | #define IO_INTC_FIQENTRY0 0x0510 | 153 | #define IO_INTC_FIQENTRY0 DM320_REG(0x0510) |
154 | #define IO_INTC_FIQENTRY1 0x0512 | 154 | #define IO_INTC_FIQENTRY1 DM320_REG(0x0512) |
155 | #define IO_INTC_FIQ_LOCK_ADDR0 0x0514 | 155 | #define IO_INTC_FIQ_LOCK_ADDR0 DM320_REG(0x0514) |
156 | #define IO_INTC_FIQ_LOCK_ADDR1 0x0516 | 156 | #define IO_INTC_FIQ_LOCK_ADDR1 DM320_REG(0x0516) |
157 | #define IO_INTC_IRQENTRY0 0x0518 | 157 | #define IO_INTC_IRQENTRY0 DM320_REG(0x0518) |
158 | #define IO_INTC_IRQENTRY1 0x051A | 158 | #define IO_INTC_IRQENTRY1 DM320_REG(0x051A) |
159 | #define IO_INTC_IRQ_LOCK_ADDR0 0x051C | 159 | #define IO_INTC_IRQ_LOCK_ADDR0 DM320_REG(0x051C) |
160 | #define IO_INTC_IRQ_LOCK_ADDR1 0x051E | 160 | #define IO_INTC_IRQ_LOCK_ADDR1 DM320_REG(0x051E) |
161 | #define IO_INTC_FISEL0 0x0520 | 161 | #define IO_INTC_FISEL0 DM320_REG(0x0520) |
162 | #define IO_INTC_FISEL1 0x0522 | 162 | #define IO_INTC_FISEL1 DM320_REG(0x0522) |
163 | #define IO_INTC_FISEL2 0x0524 | 163 | #define IO_INTC_FISEL2 DM320_REG(0x0524) |
164 | #define IO_INTC_EINT0 0x0528 | 164 | #define IO_INTC_EINT0 DM320_REG(0x0528) |
165 | #define IO_INTC_EINT1 0x052A | 165 | #define IO_INTC_EINT1 DM320_REG(0x052A) |
166 | #define IO_INTC_EINT2 0x052C | 166 | #define IO_INTC_EINT2 DM320_REG(0x052C) |
167 | #define IO_INTC_RAW 0x0530 | 167 | #define IO_INTC_RAW DM320_REG(0x0530) |
168 | #define IO_INTC_ENTRY_TBA0 0x0538 | 168 | #define IO_INTC_ENTRY_TBA0 DM320_REG(0x0538) |
169 | #define IO_INTC_ENTRY_TBA1 0x053A | 169 | #define IO_INTC_ENTRY_TBA1 DM320_REG(0x053A) |
170 | #define IO_INTC_PRIORITY0 0x0540 | 170 | #define IO_INTC_PRIORITY0 DM320_REG(0x0540) |
171 | #define IO_INTC_PRIORITY1 0x0542 | 171 | #define IO_INTC_PRIORITY1 0x0542 |
172 | #define IO_INTC_PRIORITY2 0x0544 | 172 | #define IO_INTC_PRIORITY2 0x0544 |
173 | #define IO_INTC_PRIORITY3 0x0546 | 173 | #define IO_INTC_PRIORITY3 0x0546 |
@@ -702,4 +702,42 @@ | |||
702 | 702 | ||
703 | #define NR_IRQS 46 | 703 | #define NR_IRQS 46 |
704 | 704 | ||
705 | /* Taken from linux/include/asm-arm/arch-integrator/timex.h | ||
706 | * | ||
707 | * Copyright (C) 1999 ARM Limited | ||
708 | */ | ||
709 | |||
710 | #define CONFIG_TIMER1_TMPRSCL 0x000A | ||
711 | #define CLOCK_TICK_RATE (CPUFREQ_MAX / CONFIG_TIMER1_TMPRSCL) | ||
712 | #define CONFIG_TIMER1_TMDIV (unsigned short)(CLOCK_TICK_RATE / HZ) | ||
713 | |||
714 | #define CONFIG_TIMER0_TMMD_STOP 0x0000 | ||
715 | #define CONFIG_TIMER0_TMMD_ONE_SHOT 0x0001 | ||
716 | #define CONFIG_TIMER0_TMMD_FREE_RUN 0x0002 | ||
717 | |||
718 | #define CONFIG_TIMER1_TMMD_STOP 0x0000 | ||
719 | #define CONFIG_TIMER1_TMMD_ONE_SHOT 0x0001 | ||
720 | #define CONFIG_TIMER1_TMMD_FREE_RUN 0x0002 | ||
721 | |||
722 | #define CONFIG_TIMER2_TMMD_STOP 0x0000 | ||
723 | #define CONFIG_TIMER2_TMMD_ONE_SHOT 0x0001 | ||
724 | #define CONFIG_TIMER2_TMMD_FREE_RUN 0x0002 | ||
725 | #define CONFIG_TIMER2_TMMD_CCD_SHUTTER 0x0100 | ||
726 | #define CONFIG_TIMER2_TMMD_CCD_STROBE 0x0200 | ||
727 | #define CONFIG_TIMER2_TMMD_POLARITY 0x0400 | ||
728 | #define CONFIG_TIMER2_TMMD_TRG_SELECT 0x0800 | ||
729 | #define CONFIG_TIMER2_TMMD_TRG_READY 0x1000 | ||
730 | #define CONFIG_TIMER2_TMMD_SIGNAL 0x2000 | ||
731 | |||
732 | #define CONFIG_TIMER3_TMMD_STOP 0x0000 | ||
733 | #define CONFIG_TIMER3_TMMD_ONE_SHOT 0x0001 | ||
734 | #define CONFIG_TIMER3_TMMD_FREE_RUN 0x0002 | ||
735 | #define CONFIG_TIMER3_TMMD_CCD_SHUTTER 0x0100 | ||
736 | #define CONFIG_TIMER3_TMMD_CCD_STROBE 0x0200 | ||
737 | #define CONFIG_TIMER3_TMMD_POLARITY 0x0400 | ||
738 | #define CONFIG_TIMER3_TMMD_TRG_SELECT 0x0800 | ||
739 | #define CONFIG_TIMER3_TMMD_TRG_READY 0x1000 | ||
740 | #define CONFIG_TIMER3_TMMD_SIGNAL 0x2000 | ||
741 | |||
742 | |||
705 | #endif | 743 | #endif |
diff --git a/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c b/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c index 450f0e6b03..3ac0730691 100644 --- a/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c | |||
@@ -27,7 +27,19 @@ extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void); | |||
27 | 27 | ||
28 | void tick_start(unsigned int interval_in_ms) | 28 | void tick_start(unsigned int interval_in_ms) |
29 | { | 29 | { |
30 | (void)interval_in_ms; | 30 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP; |
31 | |||
32 | /* Setup the Prescalar */ | ||
33 | IO_TIMER1_TMPRSCL = CONFIG_TIMER1_TMPRSCL; | ||
34 | |||
35 | /* Setup the Divisor */ | ||
36 | IO_TIMER1_TMDIV = CONFIG_TIMER1_TMDIV; | ||
37 | |||
38 | /* Turn Timer1 to Free Run mode */ | ||
39 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_FREE_RUN; | ||
40 | |||
41 | /* Enable the interrupt */ | ||
42 | IO_INTC_EINT0 |= 1<<IRQ_TIMER1; | ||
31 | } | 43 | } |
32 | 44 | ||
33 | void TIMER4(void) | 45 | void TIMER4(void) |
@@ -45,4 +57,5 @@ void TIMER4(void) | |||
45 | 57 | ||
46 | current_tick++; | 58 | current_tick++; |
47 | 59 | ||
60 | IO_INTC_IRQ0 |= 1<<IRQ_TIMER1; | ||
48 | } | 61 | } |
diff --git a/firmware/target/arm/olympus/mrobe-500/system-mr500.c b/firmware/target/arm/olympus/mrobe-500/system-mr500.c index 1163104ad2..5b52dc3208 100644 --- a/firmware/target/arm/olympus/mrobe-500/system-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/system-mr500.c | |||
@@ -95,7 +95,7 @@ static const char * const irqname[] = | |||
95 | 95 | ||
96 | static void UIRQ(void) | 96 | static void UIRQ(void) |
97 | { | 97 | { |
98 | unsigned int offset = inw(IO_INTC_IRQENTRY0); | 98 | unsigned int offset = IO_INTC_IRQENTRY0; |
99 | panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); | 99 | panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); |
100 | } | 100 | } |
101 | 101 | ||
@@ -105,7 +105,7 @@ void irq_handler(void) | |||
105 | /* | 105 | /* |
106 | * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c | 106 | * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c |
107 | */ | 107 | */ |
108 | 108 | printf("INTERUPT!"); | |
109 | asm volatile ( | 109 | asm volatile ( |
110 | "sub lr, lr, #4 \r\n" | 110 | "sub lr, lr, #4 \r\n" |
111 | "stmfd sp!, {r0-r3, ip, lr} \r\n" | 111 | "stmfd sp!, {r0-r3, ip, lr} \r\n" |
@@ -149,23 +149,23 @@ void system_init(void) | |||
149 | /* taken from linux/arch/arm/mach-itdm320-20/irq.c */ | 149 | /* taken from linux/arch/arm/mach-itdm320-20/irq.c */ |
150 | 150 | ||
151 | /* Clearing all FIQs and IRQs. */ | 151 | /* Clearing all FIQs and IRQs. */ |
152 | outw(0xFFFF, IO_INTC_IRQ0); | 152 | IO_INTC_IRQ0 = 0xFFFF; |
153 | outw(0xFFFF, IO_INTC_IRQ1); | 153 | IO_INTC_IRQ1 = 0xFFFF; |
154 | outw(0xFFFF, IO_INTC_IRQ2); | 154 | IO_INTC_IRQ2 = 0xFFFF; |
155 | 155 | ||
156 | outw(0xFFFF, IO_INTC_FIQ0); | 156 | IO_INTC_FIQ0 = 0xFFFF; |
157 | outw(0xFFFF, IO_INTC_FIQ1); | 157 | IO_INTC_FIQ1 = 0xFFFF; |
158 | outw(0xFFFF, IO_INTC_FIQ2); | 158 | IO_INTC_FIQ2 = 0xFFFF; |
159 | 159 | ||
160 | /* Masking all Interrupts. */ | 160 | /* Masking all Interrupts. */ |
161 | outw(0, IO_INTC_EINT0); | 161 | IO_INTC_EINT0 = 0; |
162 | outw(0, IO_INTC_EINT1); | 162 | IO_INTC_EINT1 = 0; |
163 | outw(0, IO_INTC_EINT2); | 163 | IO_INTC_EINT2 = 0; |
164 | 164 | ||
165 | /* Setting INTC to all IRQs. */ | 165 | /* Setting INTC to all IRQs. */ |
166 | outw(0, IO_INTC_FISEL0); | 166 | IO_INTC_FISEL0 = 0; |
167 | outw(0, IO_INTC_FISEL1); | 167 | IO_INTC_FISEL1 = 0; |
168 | outw(0, IO_INTC_FISEL2); | 168 | IO_INTC_FISEL2 = 0; |
169 | } | 169 | } |
170 | 170 | ||
171 | int system_memory_guard(int newmode) | 171 | int system_memory_guard(int newmode) |
diff --git a/firmware/target/arm/olympus/mrobe-500/system-target.h b/firmware/target/arm/olympus/mrobe-500/system-target.h new file mode 100755 index 0000000000..7adfda6f7d --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/system-target.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Karl Kurbjun | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #ifndef SYSTEM_TARGET_H | ||
20 | #define SYSTEM_TARGET_H | ||
21 | |||
22 | #include "system-arm.h" | ||
23 | |||
24 | #define CPUFREQ_SLEEP 32768 | ||
25 | #define CPUFREQ_DEFAULT 24000000 | ||
26 | #define CPUFREQ_NORMAL 30000000 | ||
27 | #define CPUFREQ_MAX 80000000 | ||
28 | |||
29 | #define inw(p) (*((volatile unsigned short*)((p) + PHY_IO_BASE))) | ||
30 | #define outw(v,p) (*((volatile unsigned short*)((p) + PHY_IO_BASE)) = (v)) | ||
31 | |||
32 | #endif /* SYSTEM_TARGET_H */ | ||
diff --git a/firmware/target/arm/olympus/mrobe-500/timer-mr500.c b/firmware/target/arm/olympus/mrobe-500/timer-mr500.c index 846d83b3de..21449ed19f 100644 --- a/firmware/target/arm/olympus/mrobe-500/timer-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/timer-mr500.c | |||
@@ -29,59 +29,55 @@ void TIMER0(void) | |||
29 | { | 29 | { |
30 | if (pfn_timer != NULL) | 30 | if (pfn_timer != NULL) |
31 | pfn_timer(); | 31 | pfn_timer(); |
32 | IO_INTC_IRQ0 |= 1<<IRQ_TIMER0; | ||
32 | } | 33 | } |
33 | 34 | ||
34 | static void stop_timer(void) | 35 | static void stop_timer(void) |
35 | { | 36 | { |
37 | IO_INTC_EINT0 &= ~(1<<IRQ_TIMER0); | ||
38 | |||
39 | IO_INTC_IRQ0 |= 1<<IRQ_TIMER0; | ||
40 | |||
41 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP; | ||
36 | } | 42 | } |
37 | 43 | ||
38 | bool __timer_set(long cycles, bool start) | 44 | bool __timer_set(long cycles, bool start) |
39 | { | 45 | { |
46 | int oldlevel; | ||
47 | unsigned int divider; | ||
40 | /* taken from linux/arch/arm/mach-itdm320-20/time.c and timer-meg-fx.c */ | 48 | /* taken from linux/arch/arm/mach-itdm320-20/time.c and timer-meg-fx.c */ |
41 | 49 | ||
42 | /* Turn off all timers */ | 50 | /* Turn off all timers */ |
43 | /* outw(CONFIG_TIMER0_TMMD_STOP, IO_TIMER0_TMMD); | 51 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP; |
44 | outw(CONFIG_TIMER1_TMMD_STOP, IO_TIMER1_TMMD); | 52 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP; |
45 | outw(CONFIG_TIMER2_TMMD_STOP, IO_TIMER2_TMMD); | 53 | IO_TIMER2_TMMD = CONFIG_TIMER2_TMMD_STOP; |
46 | outw(CONFIG_TIMER3_TMMD_STOP, IO_TIMER3_TMMD); | 54 | IO_TIMER3_TMMD = CONFIG_TIMER3_TMMD_STOP; |
47 | */ | ||
48 | /* Turn Timer0 to Free Run mode */ | ||
49 | // outw(CONFIG_TIMER0_TMMD_FREE_RUN, IO_TIMER0_TMMD); | ||
50 | |||
51 | bool retval = false; | ||
52 | 55 | ||
53 | /* Find the minimum factor that puts the counter in range 1-65535 */ | 56 | /* Find the minimum factor that puts the counter in range 1-65535 */ |
54 | unsigned int prescaler = (cycles + 65534) / 65535; | 57 | unsigned int prescaler = (cycles + 65534) / 65535; |
55 | 58 | ||
56 | /* Test this by writing 1's to registers to see how many bits we have */ | 59 | /* Test this by writing 1's to registers to see how many bits we have */ |
57 | /* Maximum divider setting is x / 1024 / 65536 = x / 67108864 */ | 60 | /* Maximum divider setting is x / 1024 / 65536 = x / 67108864 */ |
61 | if (start && pfn_unregister != NULL) | ||
58 | { | 62 | { |
59 | int oldlevel; | 63 | pfn_unregister(); |
60 | unsigned int divider; | 64 | pfn_unregister = NULL; |
61 | 65 | } | |
62 | if (start && pfn_unregister != NULL) | ||
63 | { | ||
64 | pfn_unregister(); | ||
65 | pfn_unregister = NULL; | ||
66 | } | ||
67 | |||
68 | oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); | ||
69 | 66 | ||
70 | /* Max prescale is 1023+1 */ | 67 | oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); |
71 | for (divider = 0; prescaler > 1024; prescaler >>= 1, divider++); | ||
72 | 68 | ||
73 | /* Setup the Prescalar */ | 69 | /* Max prescale is 1023+1 */ |
74 | outw(prescaler, IO_TIMER0_TMPRSCL); | 70 | for (divider = 0; prescaler > 1024; prescaler >>= 1, divider++); |
75 | 71 | ||
76 | /* Setup the Divisor */ | 72 | /* Setup the Prescalar */ |
77 | outw(divider, IO_TIMER0_TMDIV); | 73 | IO_TIMER0_TMPRSCL = prescaler; |
78 | 74 | ||
79 | set_irq_level(oldlevel); | 75 | /* Setup the Divisor */ |
76 | IO_TIMER0_TMDIV = divider; | ||
80 | 77 | ||
81 | retval = true; | 78 | set_irq_level(oldlevel); |
82 | } | ||
83 | 79 | ||
84 | return retval; | 80 | return true; |
85 | } | 81 | } |
86 | 82 | ||
87 | bool __timer_register(void) | 83 | bool __timer_register(void) |
@@ -93,7 +89,9 @@ bool __timer_register(void) | |||
93 | stop_timer(); | 89 | stop_timer(); |
94 | 90 | ||
95 | /* Turn Timer0 to Free Run mode */ | 91 | /* Turn Timer0 to Free Run mode */ |
96 | outw(0x0002, IO_TIMER0_TMMD); | 92 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_FREE_RUN; |
93 | |||
94 | IO_INTC_EINT0 |= 1<<IRQ_TIMER0; | ||
97 | 95 | ||
98 | set_interrupt_status(oldstatus, IRQ_FIQ_STATUS); | 96 | set_interrupt_status(oldstatus, IRQ_FIQ_STATUS); |
99 | 97 | ||
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c index 39e4efab49..340a0494c7 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c | |||
@@ -40,7 +40,7 @@ void tick_start(unsigned int interval_in_ms) | |||
40 | INTMSK &= ~TIMER4_MASK; | 40 | INTMSK &= ~TIMER4_MASK; |
41 | } | 41 | } |
42 | 42 | ||
43 | void TIMER4(void) | 43 | void TIMER1(void) |
44 | { | 44 | { |
45 | int i; | 45 | int i; |
46 | 46 | ||
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index fa63c8fb2c..7533f5da76 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -91,10 +91,7 @@ static inline void flush_icache(void) | |||
91 | } | 91 | } |
92 | 92 | ||
93 | #endif /* CONFIG_CPU */ | 93 | #endif /* CONFIG_CPU */ |
94 | #else /* CPU_CONFIG == DM320 */ | 94 | #else |
95 | |||
96 | #define inw(p) (*((volatile unsigned short*)((p) + PHY_IO_BASE))) | ||
97 | #define outw(v,p) (*((volatile unsigned short*)((p) + PHY_IO_BASE)) = (v)) | ||
98 | 95 | ||
99 | #endif | 96 | #endif |
100 | 97 | ||