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-rw-r--r--firmware/target/arm/usb-s3c6400x.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/firmware/target/arm/usb-s3c6400x.c b/firmware/target/arm/usb-s3c6400x.c
index 24e0fdc08a..fbf9a4d483 100644
--- a/firmware/target/arm/usb-s3c6400x.c
+++ b/firmware/target/arm/usb-s3c6400x.c
@@ -132,18 +132,18 @@ void usb_drv_release_endpoint(int ep)
132 132
133static void usb_reset(void) 133static void usb_reset(void)
134{ 134{
135 volatile int i;
136
137 DCTL = 0x802; /* Soft Disconnect */ 135 DCTL = 0x802; /* Soft Disconnect */
138 136
139 OPHYPWR = 0; /* PHY: Power up */ 137 OPHYPWR = 0; /* PHY: Power up */
138 udelay(10);
140 OPHYUNK1 = 1; 139 OPHYUNK1 = 1;
141 OPHYUNK2 = 0xE3F; 140 OPHYUNK2 = 0xE3F;
142 OPHYCLK = SYNOPSYSOTG_CLOCK;
143 ORSTCON = 1; /* PHY: Assert Software Reset */ 141 ORSTCON = 1; /* PHY: Assert Software Reset */
144 for (i = 0; i < 50; i++); 142 udelay(10);
145 ORSTCON = 0; /* PHY: Deassert Software Reset */ 143 ORSTCON = 0; /* PHY: Deassert Software Reset */
146 OPHYUNK3 = 0x600; 144 OPHYUNK3 = 0x600;
145 OPHYCLK = SYNOPSYSOTG_CLOCK;
146 udelay(400);
147 147
148 GRSTCTL = 1; /* OTG: Assert Software Reset */ 148 GRSTCTL = 1; /* OTG: Assert Software Reset */
149 while (GRSTCTL & 1); /* Wait for OTG to ack reset */ 149 while (GRSTCTL & 1); /* Wait for OTG to ack reset */
@@ -395,9 +395,11 @@ void usb_drv_exit(void)
395{ 395{
396 DCTL = 0x802; /* Soft Disconnect */ 396 DCTL = 0x802; /* Soft Disconnect */
397 397
398 ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */
399 PCGCCTL = 1; /* Shut down PHY clock */
400 OPHYPWR = 0xF; /* PHY: Power down */ 398 OPHYPWR = 0xF; /* PHY: Power down */
399 udelay(10);
400 ORSTCON = 7; /* Put the PHY into reset (needed to get current down) */
401 udelay(10);
402 PCGCCTL = 1; /* Shut down PHY clock */
401 403
402#if CONFIG_CPU==S5L8701 404#if CONFIG_CPU==S5L8701
403 PWRCON |= 0x4000; 405 PWRCON |= 0x4000;