diff options
Diffstat (limited to 'firmware/timer.c')
-rw-r--r-- | firmware/timer.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/firmware/timer.c b/firmware/timer.c index 80d3fec561..849e4ba598 100644 --- a/firmware/timer.c +++ b/firmware/timer.c | |||
@@ -49,7 +49,7 @@ void TIMER1(void) | |||
49 | pfn_timer(); | 49 | pfn_timer(); |
50 | TER1 = 0xff; /* clear all events */ | 50 | TER1 = 0xff; /* clear all events */ |
51 | } | 51 | } |
52 | #elif CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002 | 52 | #elif defined(CPU_PP) |
53 | void TIMER2(void) | 53 | void TIMER2(void) |
54 | { | 54 | { |
55 | TIMER2_VAL; /* ACK interrupt */ | 55 | TIMER2_VAL; /* ACK interrupt */ |
@@ -150,7 +150,7 @@ static bool timer_set(long cycles, bool start) | |||
150 | if (start || (TCN1 >= TRR1)) | 150 | if (start || (TCN1 >= TRR1)) |
151 | TCN1 = 0; /* reset the timer */ | 151 | TCN1 = 0; /* reset the timer */ |
152 | TER1 = 0xff; /* clear all events */ | 152 | TER1 = 0xff; /* clear all events */ |
153 | #elif CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002 | 153 | #elif defined(CPU_PP) |
154 | if (cycles > 0x20000000 || cycles < 2) | 154 | if (cycles > 0x20000000 || cycles < 2) |
155 | return false; | 155 | return false; |
156 | 156 | ||
@@ -200,9 +200,8 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), | |||
200 | if (reg_prio <= timer_prio || cycles == 0) | 200 | if (reg_prio <= timer_prio || cycles == 0) |
201 | return false; | 201 | return false; |
202 | 202 | ||
203 | #if (CONFIG_CPU==PP5002) || (CONFIG_CPU==PP5020) || (CONFIG_CPU==PNX0101) \ | 203 | #if defined(CPU_PP) || (CONFIG_CPU==PNX0101) || (CONFIG_CPU==S3C2440) |
204 | || (CONFIG_CPU==S3C2440) | 204 | /* TODO: Implement for PortalPlayer and iFP (if possible) */ |
205 | /* TODO: Implement for iPod and iFP (if possible) */ | ||
206 | (void)int_prio; | 205 | (void)int_prio; |
207 | #endif | 206 | #endif |
208 | 207 | ||
@@ -227,7 +226,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), | |||
227 | ICR2 = 0x90; /* interrupt on level 4.0 */ | 226 | ICR2 = 0x90; /* interrupt on level 4.0 */ |
228 | and_l(~(1<<10), &IMR); | 227 | and_l(~(1<<10), &IMR); |
229 | TMR1 |= 1; /* start timer */ | 228 | TMR1 |= 1; /* start timer */ |
230 | #elif CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002 | 229 | #elif defined(CPU_PP) |
231 | /* unmask interrupt source */ | 230 | /* unmask interrupt source */ |
232 | CPU_INT_EN = TIMER2_MASK; | 231 | CPU_INT_EN = TIMER2_MASK; |
233 | #endif | 232 | #endif |
@@ -247,7 +246,7 @@ void timer_unregister(void) | |||
247 | #elif defined CPU_COLDFIRE | 246 | #elif defined CPU_COLDFIRE |
248 | TMR1 = 0; /* disable timer 1 */ | 247 | TMR1 = 0; /* disable timer 1 */ |
249 | or_l((1<<10), &IMR); /* disable interrupt */ | 248 | or_l((1<<10), &IMR); /* disable interrupt */ |
250 | #elif CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002 | 249 | #elif defined(CPU_PP) |
251 | TIMER2_CFG = 0; /* stop timer 2 */ | 250 | TIMER2_CFG = 0; /* stop timer 2 */ |
252 | CPU_INT_CLR = TIMER2_MASK; | 251 | CPU_INT_CLR = TIMER2_MASK; |
253 | #endif | 252 | #endif |