diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/s3c2440/crt0.S | 6 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c | 1 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/system-target.h | 22 |
3 files changed, 16 insertions, 13 deletions
diff --git a/firmware/target/arm/s3c2440/crt0.S b/firmware/target/arm/s3c2440/crt0.S index 3110c88be0..2188bc07da 100644 --- a/firmware/target/arm/s3c2440/crt0.S +++ b/firmware/target/arm/s3c2440/crt0.S | |||
@@ -138,13 +138,11 @@ | |||
138 | 138 | ||
139 | /* For Mini2440 board or compatible */ | 139 | /* For Mini2440 board or compatible */ |
140 | /* Clock and Power Management setup values */ | 140 | /* Clock and Power Management setup values */ |
141 | /* NB: clock settings must match values in s3c2440/system-target.h */ | ||
141 | #define VAL_CLKDIV 0x5 /* HCLK = FCLK/4, PCLK = HCLK/2 */ | 142 | #define VAL_CLKDIV 0x5 /* HCLK = FCLK/4, PCLK = HCLK/2 */ |
142 | #define VAL_UPLLCON 0x00038022 /* UCLK = 48 MHz */ | 143 | #define VAL_UPLLCON 0x00038022 /* UCLK = 48 MHz */ |
143 | #define VAL_MPLLCON 0x0007F021 /* FCLK = 405 MHz */ | 144 | #define VAL_MPLLCON 0x000C3041 /* FCLK = 406 MHz */ |
144 | 145 | ||
145 | #define FCLK 405000000 | ||
146 | #define HCLK (FCLK/4) /* = 101,250,000 */ | ||
147 | #define PCLK (HCLK/2) /* = 50,625,000 */ | ||
148 | 146 | ||
149 | /* Memory Controller setup */ | 147 | /* Memory Controller setup */ |
150 | #define VAL_BWSCON 0x22111112 | 148 | #define VAL_BWSCON 0x22111112 |
diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c index 9c898f88d9..7779639c8f 100644 --- a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c +++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c | |||
@@ -48,7 +48,6 @@ static struct | |||
48 | /* [prescaler, master clock rate] */ | 48 | /* [prescaler, master clock rate] */ |
49 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = | 49 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = |
50 | { | 50 | { |
51 | [HW_FREQ_64] = { 2, IISMOD_MASTER_CLOCK_256FS }, | ||
52 | [HW_FREQ_44] = { 2, IISMOD_MASTER_CLOCK_384FS }, | 51 | [HW_FREQ_44] = { 2, IISMOD_MASTER_CLOCK_384FS }, |
53 | [HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS }, | 52 | [HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS }, |
54 | [HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS }, | 53 | [HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS }, |
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index cf3db301eb..7bb49c01c4 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h | |||
@@ -24,13 +24,18 @@ | |||
24 | #include "system-arm.h" | 24 | #include "system-arm.h" |
25 | #include "mmu-arm.h" | 25 | #include "mmu-arm.h" |
26 | 26 | ||
27 | /* TODO: Needs checking/porting */ | 27 | /* NB: These values must match the register settings in s3c2440/crt0.S */ |
28 | 28 | ||
29 | #ifdef GIGABEAT_F | 29 | #ifdef GIGABEAT_F |
30 | #define CPUFREQ_DEFAULT 98784000 | 30 | #define CPUFREQ_DEFAULT 98784000 |
31 | #define CPUFREQ_NORMAL 98784000 | 31 | #define CPUFREQ_NORMAL 98784000 |
32 | #define CPUFREQ_MAX 296352000 | 32 | #define CPUFREQ_MAX 296352000 |
33 | 33 | ||
34 | /* Uses 1:3:6 */ | ||
35 | #define FCLK CPUFREQ_MAX | ||
36 | #define HCLK (FCLK/3) /* = 98,784,000 */ | ||
37 | #define PCLK (HCLK/2) /* = 49,392,000 */ | ||
38 | |||
34 | #ifdef BOOTLOADER | 39 | #ifdef BOOTLOADER |
35 | /* All addresses within rockbox are in IRAM in the bootloader so | 40 | /* All addresses within rockbox are in IRAM in the bootloader so |
36 | are therefore uncached */ | 41 | are therefore uncached */ |
@@ -42,17 +47,18 @@ | |||
42 | 47 | ||
43 | #elif defined(MINI2440) | 48 | #elif defined(MINI2440) |
44 | 49 | ||
45 | #define CPUFREQ_DEFAULT 101250000 | 50 | /* Uses 1:4:8 */ |
46 | #define CPUFREQ_NORMAL 101250000 | 51 | #define FCLK 406000000 |
47 | #define CPUFREQ_MAX 405000000 | 52 | #define HCLK (FCLK/4) /* = 101,250,000 */ |
53 | #define PCLK (HCLK/2) /* = 50,625,000 */ | ||
54 | |||
55 | #define CPUFREQ_DEFAULT FCLK /* 406 MHz */ | ||
56 | #define CPUFREQ_NORMAL (FCLK/4)/* 101.25 MHz */ | ||
57 | #define CPUFREQ_MAX FCLK /* 406 MHz */ | ||
48 | 58 | ||
49 | #define UNCACHED_BASE_ADDR 0x30000000 | 59 | #define UNCACHED_BASE_ADDR 0x30000000 |
50 | #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) | 60 | #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) |
51 | 61 | ||
52 | #define FCLK 405000000 | ||
53 | #define HCLK (FCLK/4) /* = 101,250,000 */ | ||
54 | #define PCLK (HCLK/2) /* = 50,625,000 */ | ||
55 | |||
56 | #else | 62 | #else |
57 | #error Unknown target | 63 | #error Unknown target |
58 | #endif | 64 | #endif |