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-rw-r--r--firmware/target/coldfire/iaudio/system-iaudio.c35
-rw-r--r--firmware/target/coldfire/iriver/system-iriver.c36
2 files changed, 48 insertions, 23 deletions
diff --git a/firmware/target/coldfire/iaudio/system-iaudio.c b/firmware/target/coldfire/iaudio/system-iaudio.c
index 30a4f6e71b..565f75aa6d 100644
--- a/firmware/target/coldfire/iaudio/system-iaudio.c
+++ b/firmware/target/coldfire/iaudio/system-iaudio.c
@@ -24,6 +24,28 @@
24#include "timer.h" 24#include "timer.h"
25#include "pcf50606.h" 25#include "pcf50606.h"
26 26
27/* Settings for all possible clock frequencies (with properly working timers)
28 *
29 * xxx_REFRESH_TIMER below
30 * system.h, CPUFREQ_xxx_MULT |
31 * | |
32 * V V
33 * PLLCR & Rftim. IDECONFIG1/IDECONFIG2
34 * CPUCLK/Hz MULT ~0x70c00000 16MB CSCR0 CSCR1 CS2Pre CS2Post CS2Wait
35 * -------------------------------------------------------------------------
36 * 11289600 1 0x00000200 4 0x0180 0x0180 1 1 0
37 * 22579200 2 0x05028049 10 0x0180 0x0180 1 1 0
38 * 33868800 3 0x03024049 15 0x0180 0x0180 1 1 0
39 * 45158400 4 0x05028045 21 0x0180 0x0180 1 1 0
40 * 56448000 5 0x02028049 26 0x0580 0x0580 2 1 0
41 * 67737600 6 0x03024045 32 0x0580 0x0980 2 1 0
42 * 79027200 7 0x0302a045 37 0x0580 0x0d80 2 1 0
43 * 90316800 8 0x03030045 43 0x0980 0x0d80 2 1 0
44 * 101606400 9 0x01024049 48 0x0980 0x1180 2 1 0
45 * 112896000 10 0x01028049 54 0x0980 0x1580 3 1 0
46 * 124185600 11 0x0102c049 59 0x0980 0x1180 3 1 1
47 */
48
27#define MAX_REFRESH_TIMER 59 49#define MAX_REFRESH_TIMER 59
28#define NORMAL_REFRESH_TIMER 21 50#define NORMAL_REFRESH_TIMER 21
29#define DEFAULT_REFRESH_TIMER 4 51#define DEFAULT_REFRESH_TIMER 4
@@ -42,7 +64,7 @@ void set_cpu_frequency(long frequency)
42 PLLCR &= ~1; /* Bypass mode */ 64 PLLCR &= ~1; /* Bypass mode */
43 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); 65 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
44 RECALC_DELAYS(CPUFREQ_MAX); 66 RECALC_DELAYS(CPUFREQ_MAX);
45 PLLCR = 0x03042045 | (PLLCR & 0x70C00000); 67 PLLCR = 0x0102c049 | (PLLCR & 0x70C00000);
46 CSCR0 = 0x00001180; /* Flash: 4 wait states */ 68 CSCR0 = 0x00001180; /* Flash: 4 wait states */
47 CSCR1 = 0x00000980; /* LCD: 2 wait states */ 69 CSCR1 = 0x00000980; /* LCD: 2 wait states */
48 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. 70 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -50,7 +72,8 @@ void set_cpu_frequency(long frequency)
50 timers_adjust_prescale(CPUFREQ_MAX_MULT, true); 72 timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
51 DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ 73 DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
52 cpu_frequency = CPUFREQ_MAX; 74 cpu_frequency = CPUFREQ_MAX;
53 IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ 75 IDECONFIG1 = 0x100000 | (1 << 13) | (3 << 10);
76 /* BUFEN2 enable | CS2Post | CS2Pre */
54 IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ 77 IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
55 break; 78 break;
56 79
@@ -60,7 +83,7 @@ void set_cpu_frequency(long frequency)
60 PLLCR &= ~1; /* Bypass mode */ 83 PLLCR &= ~1; /* Bypass mode */
61 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); 84 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
62 RECALC_DELAYS(CPUFREQ_NORMAL); 85 RECALC_DELAYS(CPUFREQ_NORMAL);
63 PLLCR = 0x06030045 | (PLLCR & 0x70C00000); 86 PLLCR = 0x05028045 | (PLLCR & 0x70C00000);
64 CSCR0 = 0x00000580; /* Flash: 1 wait state */ 87 CSCR0 = 0x00000580; /* Flash: 1 wait state */
65 CSCR1 = 0x00000180; /* LCD: 0 wait states */ 88 CSCR1 = 0x00000180; /* LCD: 0 wait states */
66 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. 89 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -68,7 +91,8 @@ void set_cpu_frequency(long frequency)
68 timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); 91 timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
69 DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ 92 DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
70 cpu_frequency = CPUFREQ_NORMAL; 93 cpu_frequency = CPUFREQ_NORMAL;
71 IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ 94 IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10);
95 /* BUFEN2 enable | CS2Post | CS2Pre */
72 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ 96 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
73 break; 97 break;
74 default: 98 default:
@@ -83,7 +107,8 @@ void set_cpu_frequency(long frequency)
83 CSCR1 = 0x00000180; /* LCD: 0 wait states */ 107 CSCR1 = 0x00000180; /* LCD: 0 wait states */
84 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ 108 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
85 cpu_frequency = CPUFREQ_DEFAULT; 109 cpu_frequency = CPUFREQ_DEFAULT;
86 IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ 110 IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10);
111 /* BUFEN2 enable | CS2Post | CS2Pre */
87 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ 112 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
88 break; 113 break;
89 } 114 }
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c
index 32fc44f963..f2973ac525 100644
--- a/firmware/target/coldfire/iriver/system-iriver.c
+++ b/firmware/target/coldfire/iriver/system-iriver.c
@@ -31,20 +31,20 @@
31 * system.h, CPUFREQ_xxx_MULT | 31 * system.h, CPUFREQ_xxx_MULT |
32 * | | 32 * | |
33 * V V 33 * V V
34 * Refreshtim. IDECONFIG1/IDECONFIG2 34 * PLLCR & Refreshtim. IDECONFIG1/IDECONFIG2
35 * CPUCLK/Hz MULT PLLCR 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait 35 * CPUCLK/Hz MULT ~0x70400000 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait
36 * --------------------------------------------------------------------------------------- 36 * ---------------------------------------------------------------------------------------
37 * 11289600 1 0x10c00200 4 1 0x0180 0x0180 0x0180 1 0 0 37 * 11289600 1 0x00800200 4 1 0x0180 0x0180 0x0180 1 1 0
38 * 22579200 2 0x15c9e025 10 4 0x0180 0x0180 0x0180 1 0 0 38 * 22579200 2 0x0589e025 10 4 0x0180 0x0180 0x0180 1 1 0
39 * 33868800 3 0x13c8e025 15 7 0x0180 0x0180 0x0180 1 0 0 39 * 33868800 3 0x0388e025 15 7 0x0180 0x0180 0x0180 1 1 0
40 * 45158400 4 0x15c9e021 21 10 0x0580 0x0180 0x0580 1 0 0 40 * 45158400 4 0x0589e021 21 10 0x0580 0x0180 0x0580 1 1 0
41 * 56448000 5 0x12c9e025 26 12 0x0580 0x0980 41 * 56448000 5 0x0289e025 26 12 0x0580 0x0580 0x0980 2 1 0
42 * 67737600 6 0x13c8e021 32 15 0x0980 0x0d80 42 * 67737600 6 0x0388e021 32 15 0x0980 0x0980 0x0d80 2 1 0
43 * 79027200 7 0x13ca6021 37 18 0x0980 0x1180 43 * 79027200 7 0x038a6021 37 18 0x0980 0x0d80 0x1180 2 1 0
44 * 90316800 8 0x13cbe021 43 21 0x0d80 0x1580 44 * 90316800 8 0x038be021 43 21 0x0d80 0x0d80 0x1580 2 1 0
45 * 101606400 9 0x11c92025 48 23 0x0d80 0x1980 45 * 101606400 9 0x01892025 48 23 0x0d80 0x1180 0x1980 2 1 0
46 * 112896000 10 0x11c9e025 54 26 0x1180 0x1d80 46 * 112896000 10 0x0189e025 54 26 0x1180 0x1580 0x1d80 3 1 0
47 * 124185600 11 0x11cae025 59 29 0x1180 0x1180 0x2180 2 1 2 47 * 124185600 11 0x018ae025 59 29 0x1180 0x1580 0x2180 3 1 1
48 */ 48 */
49 49
50#if MEM < 32 50#if MEM < 32
@@ -93,9 +93,9 @@ void set_cpu_frequency(long frequency)
93 timers_adjust_prescale(CPUFREQ_MAX_MULT, true); 93 timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
94 DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ 94 DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
95 cpu_frequency = CPUFREQ_MAX; 95 cpu_frequency = CPUFREQ_MAX;
96 IDECONFIG1 = 0x10100000 | (1 << 13) | (2 << 10); 96 IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10);
97 /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ 97 /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
98 IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */ 98 IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
99 99
100#ifdef HAVE_SERIAL 100#ifdef HAVE_SERIAL
101 UBG10 = BAUDRATE_DIV_MAX >> 8; 101 UBG10 = BAUDRATE_DIV_MAX >> 8;
@@ -109,7 +109,7 @@ void set_cpu_frequency(long frequency)
109 PLLCR &= ~1; /* Bypass mode */ 109 PLLCR &= ~1; /* Bypass mode */
110 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); 110 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
111 RECALC_DELAYS(CPUFREQ_NORMAL); 111 RECALC_DELAYS(CPUFREQ_NORMAL);
112 PLLCR = 0x038be025 | (PLLCR & 0x70400000); 112 PLLCR = 0x0589e021 | (PLLCR & 0x70400000);
113 CSCR0 = 0x00000580; /* Flash: 1 wait state */ 113 CSCR0 = 0x00000580; /* Flash: 1 wait state */
114 CSCR1 = 0x00000180; /* LCD: 0 wait states */ 114 CSCR1 = 0x00000180; /* LCD: 0 wait states */
115#if CONFIG_USBOTG == USBOTG_ISP1362 115#if CONFIG_USBOTG == USBOTG_ISP1362
@@ -120,7 +120,7 @@ void set_cpu_frequency(long frequency)
120 timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); 120 timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
121 DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ 121 DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
122 cpu_frequency = CPUFREQ_NORMAL; 122 cpu_frequency = CPUFREQ_NORMAL;
123 IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10); 123 IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
124 /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ 124 /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
125 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ 125 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
126 126
@@ -144,7 +144,7 @@ void set_cpu_frequency(long frequency)
144#endif 144#endif
145 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ 145 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
146 cpu_frequency = CPUFREQ_DEFAULT; 146 cpu_frequency = CPUFREQ_DEFAULT;
147 IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10); 147 IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
148 /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ 148 /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
149 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ 149 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
150 150
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-29 07:28:47 +0000