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-rw-r--r--firmware/target/coldfire/iriver/system-iriver.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c
index 1cb0a502be..32fc44f963 100644
--- a/firmware/target/coldfire/iriver/system-iriver.c
+++ b/firmware/target/coldfire/iriver/system-iriver.c
@@ -85,7 +85,7 @@ void set_cpu_frequency(long frequency)
85 PLLCR = 0x018ae025 | (PLLCR & 0x70400000); 85 PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
86 CSCR0 = 0x00001180; /* Flash: 4 wait states */ 86 CSCR0 = 0x00001180; /* Flash: 4 wait states */
87 CSCR1 = 0x00001580; /* LCD: 5 wait states */ 87 CSCR1 = 0x00001580; /* LCD: 5 wait states */
88#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 88#if CONFIG_USBOTG == USBOTG_ISP1362
89 CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ 89 CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
90#endif 90#endif
91 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. 91 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -112,7 +112,7 @@ void set_cpu_frequency(long frequency)
112 PLLCR = 0x038be025 | (PLLCR & 0x70400000); 112 PLLCR = 0x038be025 | (PLLCR & 0x70400000);
113 CSCR0 = 0x00000580; /* Flash: 1 wait state */ 113 CSCR0 = 0x00000580; /* Flash: 1 wait state */
114 CSCR1 = 0x00000180; /* LCD: 0 wait states */ 114 CSCR1 = 0x00000180; /* LCD: 0 wait states */
115#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 115#if CONFIG_USBOTG == USBOTG_ISP1362
116 CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ 116 CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
117#endif 117#endif
118 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. 118 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -139,7 +139,7 @@ void set_cpu_frequency(long frequency)
139 PLLCR = 0x00800200 | (PLLCR & 0x70400000); 139 PLLCR = 0x00800200 | (PLLCR & 0x70400000);
140 CSCR0 = 0x00000180; /* Flash: 0 wait states */ 140 CSCR0 = 0x00000180; /* Flash: 0 wait states */
141 CSCR1 = 0x00000180; /* LCD: 0 wait states */ 141 CSCR1 = 0x00000180; /* LCD: 0 wait states */
142#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 142#if CONFIG_USBOTG == USBOTG_ISP1362
143 CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ 143 CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
144#endif 144#endif
145 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ 145 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */