diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/tcc780x/app.lds | 9 | ||||
-rw-r--r-- | firmware/target/arm/tcc780x/crt0.S | 4 |
2 files changed, 5 insertions, 8 deletions
diff --git a/firmware/target/arm/tcc780x/app.lds b/firmware/target/arm/tcc780x/app.lds index a742908ce1..e31e46fde7 100644 --- a/firmware/target/arm/tcc780x/app.lds +++ b/firmware/target/arm/tcc780x/app.lds | |||
@@ -116,8 +116,7 @@ SECTIONS | |||
116 | *(.icode) | 116 | *(.icode) |
117 | . = ALIGN(0x4); | 117 | . = ALIGN(0x4); |
118 | _iramend = .; | 118 | _iramend = .; |
119 | /* } > SRAM AT> DRAM */ | 119 | } > SRAM AT> DRAM |
120 | } > DRAM | ||
121 | 120 | ||
122 | _iramcopy = LOADADDR(.iram); | 121 | _iramcopy = LOADADDR(.iram); |
123 | 122 | ||
@@ -127,8 +126,7 @@ SECTIONS | |||
127 | *(.ibss) | 126 | *(.ibss) |
128 | . = ALIGN(0x4); | 127 | . = ALIGN(0x4); |
129 | _iend = .; | 128 | _iend = .; |
130 | /* } > SRAM */ | 129 | } > SRAM |
131 | } > DRAM | ||
132 | 130 | ||
133 | .stack : | 131 | .stack : |
134 | { | 132 | { |
@@ -136,8 +134,7 @@ SECTIONS | |||
136 | stackbegin = .; | 134 | stackbegin = .; |
137 | . += 0x2000; | 135 | . += 0x2000; |
138 | stackend = .; | 136 | stackend = .; |
139 | /* } > SRAM */ | 137 | } > SRAM |
140 | } > DRAM | ||
141 | 138 | ||
142 | .bss : | 139 | .bss : |
143 | { | 140 | { |
diff --git a/firmware/target/arm/tcc780x/crt0.S b/firmware/target/arm/tcc780x/crt0.S index b1608915f1..f6eb6afbe9 100644 --- a/firmware/target/arm/tcc780x/crt0.S +++ b/firmware/target/arm/tcc780x/crt0.S | |||
@@ -155,8 +155,8 @@ copied_start: | |||
155 | ldr r0, =0x8001eec0 /* Region 6: 0x80000000-0xffffffff (2Gb) */ | 155 | ldr r0, =0x8001eec0 /* Region 6: 0x80000000-0xffffffff (2Gb) */ |
156 | str r0, [r1,#0x18] /* AP: 3 EN: 1 DO: 6 CACHE_NONE */ | 156 | str r0, [r1,#0x18] /* AP: 3 EN: 1 DO: 6 CACHE_NONE */ |
157 | 157 | ||
158 | ldr r0, =0x1001aee0 /* Region 7: 0x10000000-0x17ffffff (128Mb) */ | 158 | ldr r0, =0x1001aeec /* Region 7: 0x10000000-0x17ffffff (128Mb) */ |
159 | str r0, [r1,#0x1c] /* AP: 3 EN: 1 DO: 7 CACHE_NONE */ | 159 | str r0, [r1,#0x1c] /* AP: 3 EN: 1 DO: 7 CACHE_ALL */ |
160 | 160 | ||
161 | add r1, r1, #0x8000 | 161 | add r1, r1, #0x8000 |
162 | mcr p15, 0, r1, c2, c0, 0 /* Set TTBR = TABBASE (Virtual TLB) */ | 162 | mcr p15, 0, r1, c2, c0, 0 /* Set TTBR = TABBASE (Virtual TLB) */ |