diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/mmu-arm.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/debug-s3c2440.c | 51 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c | 12 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | 10 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | 18 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c | 19 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/system-target.h | 7 |
8 files changed, 62 insertions, 59 deletions
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c index fff201cbfc..d86cd430b5 100644 --- a/firmware/target/arm/mmu-arm.c +++ b/firmware/target/arm/mmu-arm.c | |||
@@ -56,7 +56,7 @@ void __attribute__((naked)) map_section(unsigned int pa, unsigned int va, int mb | |||
56 | : | 56 | : |
57 | ); | 57 | ); |
58 | 58 | ||
59 | register int *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */ | 59 | register unsigned long *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */ |
60 | 60 | ||
61 | asm volatile | 61 | asm volatile |
62 | ( | 62 | ( |
diff --git a/firmware/target/arm/s3c2440/debug-s3c2440.c b/firmware/target/arm/s3c2440/debug-s3c2440.c index 97b7123a43..6c01f8bc1a 100644 --- a/firmware/target/arm/s3c2440/debug-s3c2440.c +++ b/firmware/target/arm/s3c2440/debug-s3c2440.c | |||
@@ -46,39 +46,40 @@ bool __dbg_ports(void) | |||
46 | while(1) | 46 | while(1) |
47 | { | 47 | { |
48 | line = 0; | 48 | line = 0; |
49 | snprintf(buf, sizeof(buf), "[Ports and Registers]"); lcd_puts(0, line++, buf); | 49 | snprintf(buf, sizeof(buf), "[Ports and Registers]"); |
50 | lcd_puts(0, line++, buf); | ||
50 | 51 | ||
51 | snprintf(buf, sizeof(buf), "GPACON: %08x GPBCON: %08x", GPACON, GPBCON); lcd_puts(0, line++, buf); | 52 | snprintf(buf, sizeof(buf), "GPACON: %08lx GPBCON: %08lx", GPACON, GPBCON); lcd_puts(0, line++, buf); |
52 | snprintf(buf, sizeof(buf), "GPADAT: %08x GPBDAT: %08x", GPADAT, GPBDAT); lcd_puts(0, line++, buf); | 53 | snprintf(buf, sizeof(buf), "GPADAT: %08lx GPBDAT: %08lx", GPADAT, GPBDAT); lcd_puts(0, line++, buf); |
53 | snprintf(buf, sizeof(buf), "GPAUP: %08x GPBUP: %08x", 0, GPBUP); lcd_puts(0, line++, buf); | 54 | snprintf(buf, sizeof(buf), "GPAUP: %08lx GPBUP: %08lx", 0ul, GPBUP); lcd_puts(0, line++, buf); |
54 | snprintf(buf, sizeof(buf), "GPCCON: %08x GPDCON: %08x", GPCCON, GPDCON); lcd_puts(0, line++, buf); | 55 | snprintf(buf, sizeof(buf), "GPCCON: %08lx GPDCON: %08lx", GPCCON, GPDCON); lcd_puts(0, line++, buf); |
55 | snprintf(buf, sizeof(buf), "GPCDAT: %08x GPDDAT: %08x", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); | 56 | snprintf(buf, sizeof(buf), "GPCDAT: %08lx GPDDAT: %08lx", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); |
56 | snprintf(buf, sizeof(buf), "GPCUP: %08x GPDUP: %08x", GPCUP, GPDUP); lcd_puts(0, line++, buf); | 57 | snprintf(buf, sizeof(buf), "GPCUP: %08lx GPDUP: %08lx", GPCUP, GPDUP); lcd_puts(0, line++, buf); |
57 | 58 | ||
58 | snprintf(buf, sizeof(buf), "GPCCON: %08x GPDCON: %08x", GPCCON, GPDCON); lcd_puts(0, line++, buf); | 59 | snprintf(buf, sizeof(buf), "GPCCON: %08lx GPDCON: %08lx", GPCCON, GPDCON); lcd_puts(0, line++, buf); |
59 | snprintf(buf, sizeof(buf), "GPCDAT: %08x GPDDAT: %08x", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); | 60 | snprintf(buf, sizeof(buf), "GPCDAT: %08lx GPDDAT: %08lx", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); |
60 | snprintf(buf, sizeof(buf), "GPCUP: %08x GPDUP: %08x", GPCUP, GPDUP); lcd_puts(0, line++, buf); | 61 | snprintf(buf, sizeof(buf), "GPCUP: %08lx GPDUP: %08lx", GPCUP, GPDUP); lcd_puts(0, line++, buf); |
61 | 62 | ||
62 | snprintf(buf, sizeof(buf), "GPECON: %08x GPFCON: %08x", GPECON, GPFCON); lcd_puts(0, line++, buf); | 63 | snprintf(buf, sizeof(buf), "GPECON: %08lx GPFCON: %08lx", GPECON, GPFCON); lcd_puts(0, line++, buf); |
63 | snprintf(buf, sizeof(buf), "GPEDAT: %08x GPFDAT: %08x", GPEDAT, GPFDAT); lcd_puts(0, line++, buf); | 64 | snprintf(buf, sizeof(buf), "GPEDAT: %08lx GPFDAT: %08lx", GPEDAT, GPFDAT); lcd_puts(0, line++, buf); |
64 | snprintf(buf, sizeof(buf), "GPEUP: %08x GPFUP: %08x", GPEUP, GPFUP); lcd_puts(0, line++, buf); | 65 | snprintf(buf, sizeof(buf), "GPEUP: %08lx GPFUP: %08lx", GPEUP, GPFUP); lcd_puts(0, line++, buf); |
65 | 66 | ||
66 | snprintf(buf, sizeof(buf), "GPGCON: %08x GPHCON: %08x", GPGCON, GPHCON); lcd_puts(0, line++, buf); | 67 | snprintf(buf, sizeof(buf), "GPGCON: %08lx GPHCON: %08lx", GPGCON, GPHCON); lcd_puts(0, line++, buf); |
67 | snprintf(buf, sizeof(buf), "GPGDAT: %08x GPHDAT: %08x", GPGDAT, GPHDAT); lcd_puts(0, line++, buf); | 68 | snprintf(buf, sizeof(buf), "GPGDAT: %08lx GPHDAT: %08lx", GPGDAT, GPHDAT); lcd_puts(0, line++, buf); |
68 | snprintf(buf, sizeof(buf), "GPGUP: %08x GPHUP: %08x", GPGUP, GPHUP); lcd_puts(0, line++, buf); | 69 | snprintf(buf, sizeof(buf), "GPGUP: %08lx GPHUP: %08lx", GPGUP, GPHUP); lcd_puts(0, line++, buf); |
69 | 70 | ||
70 | snprintf(buf, sizeof(buf), "GPJCON: %08x", GPJCON); lcd_puts(0, line++, buf); | 71 | snprintf(buf, sizeof(buf), "GPJCON: %08lx", GPJCON); lcd_puts(0, line++, buf); |
71 | snprintf(buf, sizeof(buf), "GPJDAT: %08x", GPJDAT); lcd_puts(0, line++, buf); | 72 | snprintf(buf, sizeof(buf), "GPJDAT: %08lx", GPJDAT); lcd_puts(0, line++, buf); |
72 | snprintf(buf, sizeof(buf), "GPJUP: %08x", GPJUP); lcd_puts(0, line++, buf); | 73 | snprintf(buf, sizeof(buf), "GPJUP: %08lx", GPJUP); lcd_puts(0, line++, buf); |
73 | 74 | ||
74 | line++; | 75 | line++; |
75 | 76 | ||
76 | snprintf(buf, sizeof(buf), "SRCPND: %08x INTMOD: %08x", SRCPND, INTMOD); lcd_puts(0, line++, buf); | 77 | snprintf(buf, sizeof(buf), "SRCPND: %08lx INTMOD: %08lx", SRCPND, INTMOD); lcd_puts(0, line++, buf); |
77 | snprintf(buf, sizeof(buf), "INTMSK: %08x INTPND: %08x", INTMSK, INTPND); lcd_puts(0, line++, buf); | 78 | snprintf(buf, sizeof(buf), "INTMSK: %08lx INTPND: %08lx", INTMSK, INTPND); lcd_puts(0, line++, buf); |
78 | snprintf(buf, sizeof(buf), "CLKCON: %08x CLKSLOW: %08x", CLKCON, CLKSLOW); lcd_puts(0, line++, buf); | 79 | snprintf(buf, sizeof(buf), "CLKCON: %08lx CLKSLOW: %08lx", CLKCON, CLKSLOW); lcd_puts(0, line++, buf); |
79 | snprintf(buf, sizeof(buf), "MPLLCON: %08x UPLLCON: %08x", MPLLCON, UPLLCON); lcd_puts(0, line++, buf); | 80 | snprintf(buf, sizeof(buf), "MPLLCON: %08lx UPLLCON: %08lx", MPLLCON, UPLLCON); lcd_puts(0, line++, buf); |
80 | snprintf(buf, sizeof(buf), "CLKDIVN: %08x CAMDIVN: %08x", CLKDIVN, CAMDIVN); lcd_puts(0, line++, buf); | 81 | snprintf(buf, sizeof(buf), "CLKDIVN: %08lx CAMDIVN: %08lx", CLKDIVN, CAMDIVN); lcd_puts(0, line++, buf); |
81 | snprintf(buf, sizeof(buf), "BWSCON: %08x TCONSEL: %08x", BWSCON, TCONSEL); lcd_puts(0, line++, buf); | 82 | snprintf(buf, sizeof(buf), "BWSCON: %08lx TCONSEL: %08lx", BWSCON, TCONSEL); lcd_puts(0, line++, buf); |
82 | 83 | ||
83 | lcd_update(); | 84 | lcd_update(); |
84 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) | 85 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c index d821de4a30..fd5151a3bf 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c | |||
@@ -35,7 +35,7 @@ void adc_init(void) | |||
35 | int i; | 35 | int i; |
36 | 36 | ||
37 | /* Turn on the ADC PCLK */ | 37 | /* Turn on the ADC PCLK */ |
38 | s3c_regset(&CLKCON, 1<<15); | 38 | s3c_regset32(&CLKCON, 1<<15); |
39 | 39 | ||
40 | /* Set channel 0, normal mode, disable "start by read" */ | 40 | /* Set channel 0, normal mode, disable "start by read" */ |
41 | ADCCON &= ~(0x3F); | 41 | ADCCON &= ~(0x3F); |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c index 8300944243..836dedd462 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c | |||
@@ -43,7 +43,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
43 | mutex_lock(&i2c_mtx); | 43 | mutex_lock(&i2c_mtx); |
44 | 44 | ||
45 | /* Turn on I2C clock */ | 45 | /* Turn on I2C clock */ |
46 | s3c_regset(&CLKCON, 1 << 16); | 46 | s3c_regset32(&CLKCON, 1 << 16); |
47 | 47 | ||
48 | /* Set mode to master transmitter and enable lines */ | 48 | /* Set mode to master transmitter and enable lines */ |
49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; | 49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; |
@@ -76,7 +76,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
76 | IICSTAT = 0; | 76 | IICSTAT = 0; |
77 | 77 | ||
78 | /* Turn off I2C clock */ | 78 | /* Turn off I2C clock */ |
79 | s3c_regclr(&CLKCON, 1 << 16); | 79 | s3c_regclr32(&CLKCON, 1 << 16); |
80 | 80 | ||
81 | mutex_unlock(&i2c_mtx); | 81 | mutex_unlock(&i2c_mtx); |
82 | } | 82 | } |
@@ -92,11 +92,11 @@ void i2c_init(void) | |||
92 | INTPND = IIC_MASK; | 92 | INTPND = IIC_MASK; |
93 | 93 | ||
94 | /* Enable i2c interrupt in controller */ | 94 | /* Enable i2c interrupt in controller */ |
95 | s3c_regclr(&INTMOD, IIC_MASK); | 95 | s3c_regclr32(&INTMOD, IIC_MASK); |
96 | s3c_regclr(&INTMSK, IIC_MASK); | 96 | s3c_regclr32(&INTMSK, IIC_MASK); |
97 | 97 | ||
98 | /* Turn on I2C clock */ | 98 | /* Turn on I2C clock */ |
99 | s3c_regset(&CLKCON, 1 << 16); | 99 | s3c_regset32(&CLKCON, 1 << 16); |
100 | 100 | ||
101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ | 101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ |
102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | | 102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | |
@@ -110,7 +110,7 @@ void i2c_init(void) | |||
110 | IICLC = (0 << 0); | 110 | IICLC = (0 << 0); |
111 | 111 | ||
112 | /* Turn off I2C clock */ | 112 | /* Turn off I2C clock */ |
113 | s3c_regclr(&CLKCON, 1 << 16); | 113 | s3c_regclr32(&CLKCON, 1 << 16); |
114 | } | 114 | } |
115 | 115 | ||
116 | void IIC(void) | 116 | void IIC(void) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c index ac8dc380e2..f3461cfe91 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | |||
@@ -103,7 +103,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
103 | GPDCON |= 0xAAA0AAA0; | 103 | GPDCON |= 0xAAA0AAA0; |
104 | GPDUP |= 0xFCFC; | 104 | GPDUP |= 0xFCFC; |
105 | 105 | ||
106 | s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ | 106 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ |
107 | LCDCON1 |=0x01; | 107 | LCDCON1 |=0x01; |
108 | } | 108 | } |
109 | else | 109 | else |
@@ -115,7 +115,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
115 | GPDUP &= ~0xFCFC; | 115 | GPDUP &= ~0xFCFC; |
116 | 116 | ||
117 | LCDCON1 &= ~1; /* Must diable first or bus may freeze */ | 117 | LCDCON1 &= ~1; /* Must diable first or bus may freeze */ |
118 | s3c_regclr(&CLKCON, 0x20); /* disable LCD clock */ | 118 | s3c_regclr32(&CLKCON, 0x20); /* disable LCD clock */ |
119 | } | 119 | } |
120 | } | 120 | } |
121 | 121 | ||
@@ -162,7 +162,7 @@ static void LCD_SPI_SS(bool select) | |||
162 | 162 | ||
163 | static void LCD_SPI_start(void) | 163 | static void LCD_SPI_start(void) |
164 | { | 164 | { |
165 | s3c_regset(&CLKCON, 0x40000); /* enable SPI clock */ | 165 | s3c_regset32(&CLKCON, 0x40000); /* enable SPI clock */ |
166 | LCD_SPI_SS(false); | 166 | LCD_SPI_SS(false); |
167 | SPCON0=0x3E; | 167 | SPCON0=0x3E; |
168 | SPPRE0=24; | 168 | SPPRE0=24; |
@@ -176,7 +176,7 @@ static void LCD_SPI_stop(void) | |||
176 | LCD_SPI_SS(false); | 176 | LCD_SPI_SS(false); |
177 | 177 | ||
178 | SPCON0 &= ~0x10; | 178 | SPCON0 &= ~0x10; |
179 | s3c_regclr(&CLKCON, 0x40000); /* disable SPI clock */ | 179 | s3c_regclr32(&CLKCON, 0x40000); /* disable SPI clock */ |
180 | } | 180 | } |
181 | 181 | ||
182 | static void LCD_SPI_powerdown(void) | 182 | static void LCD_SPI_powerdown(void) |
@@ -271,7 +271,7 @@ void lcd_init_device(void) | |||
271 | 271 | ||
272 | GPBUP |= 0x181; | 272 | GPBUP |= 0x181; |
273 | 273 | ||
274 | s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ | 274 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ |
275 | 275 | ||
276 | LCD_CTRL_setup(); | 276 | LCD_CTRL_setup(); |
277 | LCD_SPI_init(); | 277 | LCD_SPI_init(); |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c index c219922607..14fbcd5cfe 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | |||
@@ -77,14 +77,14 @@ void pcm_apply_settings(void) | |||
77 | void pcm_play_lock(void) | 77 | void pcm_play_lock(void) |
78 | { | 78 | { |
79 | if (++dma_play_lock.locked == 1) | 79 | if (++dma_play_lock.locked == 1) |
80 | s3c_regset(&INTMSK, DMA2_MASK); | 80 | s3c_regset32(&INTMSK, DMA2_MASK); |
81 | } | 81 | } |
82 | 82 | ||
83 | /* Unmask the DMA interrupt if enabled */ | 83 | /* Unmask the DMA interrupt if enabled */ |
84 | void pcm_play_unlock(void) | 84 | void pcm_play_unlock(void) |
85 | { | 85 | { |
86 | if (--dma_play_lock.locked == 0) | 86 | if (--dma_play_lock.locked == 0) |
87 | s3c_regclr(&INTMSK, dma_play_lock.state); | 87 | s3c_regclr32(&INTMSK, dma_play_lock.state); |
88 | } | 88 | } |
89 | 89 | ||
90 | void pcm_play_dma_init(void) | 90 | void pcm_play_dma_init(void) |
@@ -94,7 +94,7 @@ void pcm_play_dma_init(void) | |||
94 | /* There seem to be problems when changing the IIS interface configuration | 94 | /* There seem to be problems when changing the IIS interface configuration |
95 | * when a clock is not present. | 95 | * when a clock is not present. |
96 | */ | 96 | */ |
97 | s3c_regset(&CLKCON, 1<<17); | 97 | s3c_regset32(&CLKCON, 1<<17); |
98 | /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - | 98 | /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - |
99 | BCLK 32fs */ | 99 | BCLK 32fs */ |
100 | IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); | 100 | IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); |
@@ -102,7 +102,7 @@ void pcm_play_dma_init(void) | |||
102 | /* RX,TX off,on */ | 102 | /* RX,TX off,on */ |
103 | IISCON |= (1<<3) | (1<<2); | 103 | IISCON |= (1<<3) | (1<<2); |
104 | 104 | ||
105 | s3c_regclr(&CLKCON, 1<<17); | 105 | s3c_regclr32(&CLKCON, 1<<17); |
106 | 106 | ||
107 | audiohw_init(); | 107 | audiohw_init(); |
108 | 108 | ||
@@ -115,11 +115,11 @@ void pcm_play_dma_init(void) | |||
115 | /* Do not service DMA requests, yet */ | 115 | /* Do not service DMA requests, yet */ |
116 | 116 | ||
117 | /* clear any pending int and mask it */ | 117 | /* clear any pending int and mask it */ |
118 | s3c_regset(&INTMSK, DMA2_MASK); | 118 | s3c_regset32(&INTMSK, DMA2_MASK); |
119 | SRCPND = DMA2_MASK; | 119 | SRCPND = DMA2_MASK; |
120 | 120 | ||
121 | /* connect to FIQ */ | 121 | /* connect to FIQ */ |
122 | s3c_regset(&INTMOD, DMA2_MASK); | 122 | s3c_regset32(&INTMOD, DMA2_MASK); |
123 | } | 123 | } |
124 | 124 | ||
125 | void pcm_postinit(void) | 125 | void pcm_postinit(void) |
@@ -159,7 +159,7 @@ static void play_start_pcm(void) | |||
159 | static void play_stop_pcm(void) | 159 | static void play_stop_pcm(void) |
160 | { | 160 | { |
161 | /* Mask DMA interrupt */ | 161 | /* Mask DMA interrupt */ |
162 | s3c_regset(&INTMSK, DMA2_MASK); | 162 | s3c_regset32(&INTMSK, DMA2_MASK); |
163 | 163 | ||
164 | /* De-Activate the DMA channel */ | 164 | /* De-Activate the DMA channel */ |
165 | DMASKTRIG2 = 0x4; | 165 | DMASKTRIG2 = 0x4; |
@@ -187,7 +187,7 @@ static void play_stop_pcm(void) | |||
187 | void pcm_play_dma_start(const void *addr, size_t size) | 187 | void pcm_play_dma_start(const void *addr, size_t size) |
188 | { | 188 | { |
189 | /* Enable the IIS clock */ | 189 | /* Enable the IIS clock */ |
190 | s3c_regset(&CLKCON, 1<<17); | 190 | s3c_regset32(&CLKCON, 1<<17); |
191 | 191 | ||
192 | /* stop any DMA in progress - idle IIS */ | 192 | /* stop any DMA in progress - idle IIS */ |
193 | play_stop_pcm(); | 193 | play_stop_pcm(); |
@@ -218,7 +218,7 @@ void pcm_play_dma_stop(void) | |||
218 | play_stop_pcm(); | 218 | play_stop_pcm(); |
219 | 219 | ||
220 | /* Disconnect the IIS clock */ | 220 | /* Disconnect the IIS clock */ |
221 | s3c_regclr(&CLKCON, 1<<17); | 221 | s3c_regclr32(&CLKCON, 1<<17); |
222 | } | 222 | } |
223 | 223 | ||
224 | void pcm_play_dma_pause(bool pause) | 224 | void pcm_play_dma_pause(bool pause) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c index 8065926e28..6d8108be49 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c | |||
@@ -118,34 +118,35 @@ static void set_page_tables(void) | |||
118 | map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */ | 118 | map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */ |
119 | } | 119 | } |
120 | 120 | ||
121 | void memory_init(void) { | 121 | void memory_init(void) |
122 | { | ||
122 | ttb_init(); | 123 | ttb_init(); |
123 | set_page_tables(); | 124 | set_page_tables(); |
124 | enable_mmu(); | 125 | enable_mmu(); |
125 | } | 126 | } |
126 | 127 | ||
127 | void s3c_regmod(volatile int *reg, unsigned int set, unsigned int clr) | 128 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, |
129 | unsigned long mask) | ||
128 | { | 130 | { |
129 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 131 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
130 | unsigned int val = *reg; | 132 | *reg = (*reg & ~mask) | (bits & mask); |
131 | *reg = (val | set) & ~clr; | ||
132 | restore_interrupt(oldstatus); | 133 | restore_interrupt(oldstatus); |
133 | } | 134 | } |
134 | 135 | ||
135 | void s3c_regset(volatile int *reg, unsigned int mask) | 136 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits) |
136 | { | 137 | { |
137 | s3c_regmod(reg, mask, 0); | 138 | s3c_regmod32(reg, bits, bits); |
138 | } | 139 | } |
139 | 140 | ||
140 | void s3c_regclr(volatile int *reg, unsigned int mask) | 141 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits) |
141 | { | 142 | { |
142 | s3c_regmod(reg, 0, mask); | 143 | s3c_regmod32(reg, 0, bits); |
143 | } | 144 | } |
144 | 145 | ||
145 | void system_init(void) | 146 | void system_init(void) |
146 | { | 147 | { |
147 | INTMSK = 0xFFFFFFFF; | 148 | INTMSK = 0xFFFFFFFF; |
148 | INTMOD = 0; | 149 | INTMOD = 0; |
149 | SRCPND = 0xFFFFFFFF; | 150 | SRCPND = 0xFFFFFFFF; |
150 | INTPND = 0xFFFFFFFF; | 151 | INTPND = 0xFFFFFFFF; |
151 | INTSUBMSK = 0xFFFFFFFF; | 152 | INTSUBMSK = 0xFFFFFFFF; |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h index 46b726869b..43758ece08 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h | |||
@@ -31,11 +31,12 @@ | |||
31 | /* Functions to set and clear regiser bits atomically */ | 31 | /* Functions to set and clear regiser bits atomically */ |
32 | 32 | ||
33 | /* Set and clear register bits */ | 33 | /* Set and clear register bits */ |
34 | void s3c_regmod(volatile int *reg, unsigned int set, unsigned int clr); | 34 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, |
35 | unsigned long mask); | ||
35 | /* Set register bits */ | 36 | /* Set register bits */ |
36 | void s3c_regset(volatile int *reg, unsigned int mask); | 37 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits); |
37 | /* Clear register bits */ | 38 | /* Clear register bits */ |
38 | void s3c_regclr(volatile int *reg, unsigned int mask); | 39 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); |
39 | 40 | ||
40 | #define HAVE_INVALIDATE_ICACHE | 41 | #define HAVE_INVALIDATE_ICACHE |
41 | static inline void invalidate_icache(void) | 42 | static inline void invalidate_icache(void) |