8 files changed, 10 insertions, 10 deletions

diff --git a/firmware/target/arm/as3525/system-target.h b/firmware/target/arm/as3525/system-target.h
index 6db16af040..7c9dcccc0c 100644
--- a/firmware/target/arm/as3525/system-target.h
+++ b/firmware/target/arm/as3525/system-target.h
@@ -42,7 +42,7 @@
 
 #define AS3525_UNCACHED_ADDR(a) ((typeof(a)) ((uintptr_t)(a) + 0x10000000))
 #define AS3525_PHYSICAL_ADDR(a) \
-    ((typeof(a)) ((((uintptr_t)(a)) & (MEM*0x100000)) \
+    ((typeof(a)) ((((uintptr_t)(a)) & (MEMORYSIZE*0x100000)) \
         ? (((uintptr_t)(a)) - IRAM_ORIG) \
         : ((uintptr_t)(a))))
 
diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S
index 585455f821..12c885068d 100644
--- a/firmware/target/arm/crt0-pp.S
+++ b/firmware/target/arm/crt0-pp.S
@@ -48,7 +48,7 @@ start:
     .equ    CACHE_CTRL,  0xcf004024
     .equ    MMAP_LOG,    0xf000f000 /* MMAP0 */
     .equ    MMAP_PHYS,   0xf000f004
-#if MEM > 32
+#if MEMORYSIZE > 32
     .equ    MMAP_MASK,   0x00003c00
 #else
     .equ    MMAP_MASK,   0x00003e00
@@ -69,7 +69,7 @@ start:
     .equ    CACHE_CTRL,  0x6000c000
     .equ    MMAP_LOG,    0xf000f000 /* MMAP0 */
     .equ    MMAP_PHYS,   0xf000f004
-#if MEM > 32
+#if MEMORYSIZE > 32
     .equ    MMAP_MASK,   0x00003c00
 #else
     .equ    MMAP_MASK,   0x00003e00
diff --git a/firmware/target/arm/crt0-pp502x-bl-usb.S b/firmware/target/arm/crt0-pp502x-bl-usb.S
index c360596001..c8b7fb4ee8 100644
--- a/firmware/target/arm/crt0-pp502x-bl-usb.S
+++ b/firmware/target/arm/crt0-pp502x-bl-usb.S
@@ -47,7 +47,7 @@
     .equ    CACHE_ENAB,  0x1
     .equ    CACHE_OP_COMMIT_DISCARD, 0x1
     .equ    CACHE_OP_COMMIT        , 0x0
-#if MEM > 32
+#if MEMORYSIZE > 32
     .equ    MMAP_MASK,   0x00003c00
 #else
     .equ    MMAP_MASK,   0x00003e00
diff --git a/firmware/target/arm/tcc77x/crt0.S b/firmware/target/arm/tcc77x/crt0.S
index 7c900212db..251fd0c903 100644
--- a/firmware/target/arm/tcc77x/crt0.S
+++ b/firmware/target/arm/tcc77x/crt0.S
@@ -109,7 +109,7 @@ start_loc:
     mov    r0, #0x20000000    /* Otherwise, load address is the start of DRAM */
 #endif
     mov    r1, #0x20000000    /* Destination: 1MB from end of DRAM */
-    add    r1, r1, #((MEM - 1) * 0x100000)
+    add    r1, r1, #((MEMORYSIZE - 1) * 0x100000)
 
     ldr    r2, =_dataend
 1:
diff --git a/firmware/target/arm/thread-pp.c b/firmware/target/arm/thread-pp.c
index 0c077779e5..3eb7238a25 100644
--- a/firmware/target/arm/thread-pp.c
+++ b/firmware/target/arm/thread-pp.c
@@ -21,7 +21,7 @@
  *
  ****************************************************************************/
 
-#if defined(MAX_PHYS_SECTOR_SIZE) && MEM == 64
+#if defined(MAX_PHYS_SECTOR_SIZE) && MEMORYSIZE == 64
 /* Support a special workaround object for large-sector disks */
 #define IF_NO_SKIP_YIELD(...) __VA_ARGS__
 #endif
diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S
index 7734970ff0..e6717710b1 100644
--- a/firmware/target/coldfire/crt0.S
+++ b/firmware/target/coldfire/crt0.S
@@ -138,7 +138,7 @@ start:
 
     /* Set up the DRAM controller. The refresh is based on the 11.2896MHz
        clock (5.6448MHz bus frequency). We haven't yet started the PLL */
-#if MEM < 32
+#if MEMORYSIZE < 32
     move.w  #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */
 #else
     move.w  #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */
@@ -153,7 +153,7 @@ start:
        In our case this means that we set the base address 16M ahead and
        use a 64M mask.
     */
-#if MEM < 32
+#if MEMORYSIZE < 32
     move.l  #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up,
                                CAS latency 2, Page mode, No refresh yet */
     move.l  %d0,(0x108,%a0)
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c
index 1916eec0cd..1ceb89bd16 100644
--- a/firmware/target/coldfire/iriver/system-iriver.c
+++ b/firmware/target/coldfire/iriver/system-iriver.c
@@ -49,7 +49,7 @@
  * 124185600   11   0x018ae025   59    29   0x1180  0x1580  0x2180     3      1       1
  */
 
-#if MEM < 32
+#if MEMORYSIZE < 32
 #define MAX_REFRESH_TIMER     59
 #define NORMAL_REFRESH_TIMER  21
 #define DEFAULT_REFRESH_TIMER 4
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c
index 5ea1015acf..31b07409d5 100644
--- a/firmware/target/mips/mmu-mips.c
+++ b/firmware/target/mips/mmu-mips.c
@@ -121,7 +121,7 @@ void mmu_init(void)
     local_flush_tlb_all();
 /*
     map_address(0x80000000, 0x80000000, 0x4000, K_CacheAttrC);
-    map_address(0x80004000, 0x80004000, MEM * 0x100000, K_CacheAttrC);
+    map_address(0x80004000, 0x80004000, MEMORYSIZE * 0x100000, K_CacheAttrC);
 */
 }