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Diffstat (limited to 'firmware/target/sh/archos/player')
-rwxr-xr-x | firmware/target/sh/archos/player/lcd-as-player.S | 230 |
1 files changed, 230 insertions, 0 deletions
diff --git a/firmware/target/sh/archos/player/lcd-as-player.S b/firmware/target/sh/archos/player/lcd-as-player.S new file mode 100755 index 0000000000..7a6324865f --- /dev/null +++ b/firmware/target/sh/archos/player/lcd-as-player.S | |||
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1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2004 by Jens Arnold | ||
11 | * Based on the work of Alan Korr and Jörg Hohensohn | ||
12 | * | ||
13 | * All files in this archive are subject to the GNU General Public License. | ||
14 | * See the file COPYING in the source tree root for full license agreement. | ||
15 | * | ||
16 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
17 | * KIND, either express or implied. | ||
18 | * | ||
19 | ****************************************************************************/ | ||
20 | |||
21 | #include "config.h" | ||
22 | #include "cpu.h" | ||
23 | |||
24 | #define LCDR (PBDR_ADDR+1) | ||
25 | |||
26 | #define LCD_DS 1 /* PB0 = 1 --- 0001 --- LCD-DS */ | ||
27 | #define LCD_CS 2 /* PB1 = 1 --- 0010 --- /LCD-CS */ | ||
28 | #define LCD_SD 4 /* PB2 = 1 --- 0100 --- LCD-SD */ | ||
29 | #define LCD_SC 8 /* PB3 = 1 --- 1000 --- LCD-SC */ | ||
30 | |||
31 | /* | ||
32 | * About /CS,DS,SC,SD | ||
33 | * ------------------ | ||
34 | * | ||
35 | * LCD on JBP and JBR uses a SPI protocol to receive orders (SDA and SCK lines) | ||
36 | * | ||
37 | * - /CS -> Chip Selection line : | ||
38 | * 0 : LCD chipset is activated. | ||
39 | * - DS -> Data Selection line, latched at the rising edge | ||
40 | * of the 8th serial clock (*) : | ||
41 | * 0 : instruction register, | ||
42 | * 1 : data register; | ||
43 | * - SC -> Serial Clock line (SDA). | ||
44 | * - SD -> Serial Data line (SCK), latched at the rising edge | ||
45 | * of each serial clock (*). | ||
46 | * | ||
47 | * _ _ | ||
48 | * /CS \ / | ||
49 | * \______________________________________________________/ | ||
50 | * _____ ____ ____ ____ ____ ____ ____ ____ ____ _____ | ||
51 | * SD \/ D7 \/ D6 \/ D5 \/ D4 \/ D3 \/ D2 \/ D1 \/ D0 \/ | ||
52 | * _____/\____/\____/\____/\____/\____/\____/\____/\____/\_____ | ||
53 | * | ||
54 | * _____ _ _ _ _ _ _ _ ________ | ||
55 | * SC \ * \ * \ * \ * \ * \ * \ * \ * | ||
56 | * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ | ||
57 | * _ _________________________________________________________ | ||
58 | * DS \/ | ||
59 | * _/\_________________________________________________________ | ||
60 | * | ||
61 | */ | ||
62 | |||
63 | .section .icode,"ax",@progbits | ||
64 | |||
65 | .align 2 | ||
66 | .global _lcd_write_command | ||
67 | .type _lcd_write_command,@function | ||
68 | |||
69 | /* Write a command byte to the lcd controller | ||
70 | * | ||
71 | * Arguments: | ||
72 | * r4 - data byte (int) | ||
73 | * | ||
74 | * Register usage: | ||
75 | * r0 - scratch | ||
76 | * r1 - data byte (copied) | ||
77 | * r2 - precalculated port value (CS, DS and SC low, SD high) | ||
78 | * r3 - lcd port address | ||
79 | * r5 - 1 (byte count for reuse of the loop in _lcd_write_data) | ||
80 | */ | ||
81 | |||
82 | _lcd_write_command: | ||
83 | mov.l .lcdr,r3 /* put lcd data port address in r3 */ | ||
84 | mov r4,r1 /* copy data byte to r1 */ | ||
85 | mov #1,r5 /* set byte count to 1 (!) */ | ||
86 | |||
87 | /* This code will fail if an interrupt changes the contents of PBDRL. | ||
88 | * If so, we must disable the interrupt here. */ | ||
89 | |||
90 | mov.b @r3,r0 /* r0 = PBDRL */ | ||
91 | or #(LCD_SD),r0 /* r0 |= LCD_SD */ | ||
92 | and #(~(LCD_CS|LCD_DS|LCD_SC)),r0 /* r0 &= ~(LCD_CS|LCD_DS|LCD_SC) */ | ||
93 | |||
94 | bra .single_transfer /* jump into the transfer loop */ | ||
95 | mov r0,r2 | ||
96 | |||
97 | |||
98 | .align 2 | ||
99 | .global _lcd_write_data | ||
100 | .type _lcd_write_data,@function | ||
101 | |||
102 | |||
103 | /* A high performance function to write data to the display, | ||
104 | * one or multiple bytes. | ||
105 | * | ||
106 | * Arguments: | ||
107 | * r4 - data address | ||
108 | * r5 - byte count | ||
109 | * | ||
110 | * Register usage: | ||
111 | * r0 - scratch | ||
112 | * r1 - current data byte | ||
113 | * r2 - precalculated port value (CS and SC low, DS and SD high), | ||
114 | * negated (neg)! | ||
115 | * r3 - lcd port address | ||
116 | */ | ||
117 | |||
118 | _lcd_write_data: | ||
119 | mov.l .lcdr,r3 /* put lcd data port address in r3 */ | ||
120 | nop /* align here */ | ||
121 | |||
122 | /* This code will fail if an interrupt changes the contents of PBDRL. | ||
123 | * If so, we must disable the interrupt here. If disabling interrupts | ||
124 | * for a long time (~9200 clks = ~830 µs for transferring 112 bytes on | ||
125 | * recorders)is undesirable, the loop has to be rewritten to | ||
126 | * disable/precalculate/transfer/enable for each iteration. However, | ||
127 | * this would significantly decrease performance. */ | ||
128 | |||
129 | mov.b @r3,r0 /* r0 = PBDRL */ | ||
130 | or #(LCD_DS|LCD_SD),r0 /* r0 |= LCD_DS|LCD_SD */ | ||
131 | and #(~(LCD_CS|LCD_SC)),r0 /* r0 &= ~(LCD_CS|LCD_SC) */ | ||
132 | mov r0,r2 | ||
133 | |||
134 | .align 2 | ||
135 | .multi_transfer: | ||
136 | mov.b @r4+,r1 /* load data byte from memory */ | ||
137 | |||
138 | .single_transfer: | ||
139 | shll16 r1 /* shift data to most significant byte */ | ||
140 | shll8 r1 | ||
141 | |||
142 | shll r1 /* shift the msb into carry */ | ||
143 | mov r2,r0 /* copy precalculated port value */ | ||
144 | bt 1f /* data bit = 1? */ | ||
145 | and #(~LCD_SD),r0 /* no: r0 &= ~LCD_SD */ | ||
146 | 1: | ||
147 | shll r1 /* next shift here for alignment */ | ||
148 | mov.b r0,@r3 /* set data to port */ | ||
149 | or #(LCD_SC),r0 /* rise SC (independent of SD level) */ | ||
150 | mov.b r0,@r3 /* set to port */ | ||
151 | |||
152 | mov r2,r0 | ||
153 | bt 1f | ||
154 | and #(~LCD_SD),r0 | ||
155 | 1: | ||
156 | mov.b r0,@r3 | ||
157 | or #(LCD_SC),r0 | ||
158 | mov.b r0,@r3 | ||
159 | |||
160 | shll r1 | ||
161 | mov r2,r0 | ||
162 | bt 1f | ||
163 | and #(~LCD_SD),r0 | ||
164 | 1: | ||
165 | shll r1 | ||
166 | mov.b r0,@r3 | ||
167 | or #(LCD_SC),r0 | ||
168 | mov.b r0,@r3 | ||
169 | |||
170 | mov r2,r0 | ||
171 | bt 1f | ||
172 | and #(~LCD_SD),r0 | ||
173 | 1: | ||
174 | mov.b r0,@r3 | ||
175 | or #(LCD_SC),r0 | ||
176 | mov.b r0,@r3 | ||
177 | |||
178 | shll r1 | ||
179 | mov r2,r0 | ||
180 | bt 1f | ||
181 | and #(~LCD_SD),r0 | ||
182 | 1: | ||
183 | shll r1 | ||
184 | mov.b r0,@r3 | ||
185 | or #(LCD_SC),r0 | ||
186 | mov.b r0,@r3 | ||
187 | |||
188 | mov r2,r0 | ||
189 | bt 1f | ||
190 | and #(~LCD_SD),r0 | ||
191 | 1: | ||
192 | mov.b r0,@r3 | ||
193 | or #(LCD_SC),r0 | ||
194 | mov.b r0,@r3 | ||
195 | |||
196 | shll r1 | ||
197 | mov r2,r0 | ||
198 | bt 1f | ||
199 | and #(~LCD_SD),r0 | ||
200 | 1: | ||
201 | shll r1 | ||
202 | mov.b r0,@r3 | ||
203 | or #(LCD_SC),r0 | ||
204 | mov.b r0,@r3 | ||
205 | |||
206 | mov r2,r0 | ||
207 | bt 1f | ||
208 | and #(~LCD_SD),r0 | ||
209 | 1: | ||
210 | mov.b r0,@r3 | ||
211 | or #(LCD_SC),r0 | ||
212 | mov.b r0,@r3 | ||
213 | |||
214 | add #-1,r5 /* decrease byte count */ | ||
215 | tst r5,r5 /* r5 == 0 ? */ | ||
216 | bf .multi_transfer /* no: next iteration */ | ||
217 | |||
218 | or #(LCD_CS|LCD_DS|LCD_SD|LCD_SC),r0 /* restore port */ | ||
219 | rts | ||
220 | mov.b r0,@r3 | ||
221 | |||
222 | /* This is the place to reenable the interrupts, if we have disabled | ||
223 | * them. See above. */ | ||
224 | |||
225 | .align 2 | ||
226 | .lcdr: | ||
227 | .long LCDR | ||
228 | |||
229 | .end: | ||
230 | .size _lcd_write_command,.end-_lcd_write_command | ||