diff options
Diffstat (limited to 'firmware/target/sh/adc-sh.c')
-rw-r--r-- | firmware/target/sh/adc-sh.c | 110 |
1 files changed, 0 insertions, 110 deletions
diff --git a/firmware/target/sh/adc-sh.c b/firmware/target/sh/adc-sh.c deleted file mode 100644 index 2e6d6407b8..0000000000 --- a/firmware/target/sh/adc-sh.c +++ /dev/null | |||
@@ -1,110 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "cpu.h" | ||
23 | #include "system.h" | ||
24 | #include "kernel.h" | ||
25 | #include "thread.h" | ||
26 | #include "string.h" | ||
27 | #include "adc.h" | ||
28 | |||
29 | /************************************************************************** | ||
30 | ** The A/D conversion is done every tick, in three steps: | ||
31 | ** | ||
32 | ** 1) On the tick interrupt, the conversion of channels 0-3 is started, and | ||
33 | ** the A/D interrupt is enabled. | ||
34 | ** | ||
35 | ** 2) After the conversion is done (approx. 256*4 cycles later), an interrupt | ||
36 | ** is generated at level 1, which is the same level as the tick interrupt | ||
37 | ** itself. This interrupt will be pending until the tick interrupt is | ||
38 | ** finished. | ||
39 | ** When the A/D interrupt is finally served, it will read the results | ||
40 | ** from the first conversion and start the conversion of channels 4-7. | ||
41 | ** | ||
42 | ** 3) When the conversion of channels 4-7 is finished, the interrupt is | ||
43 | ** triggered again, and the results are read. This time, no new | ||
44 | ** conversion is started, it will be done in the next tick interrupt. | ||
45 | ** | ||
46 | ** Thus, each channel will be updated HZ times per second. | ||
47 | ** | ||
48 | *************************************************************************/ | ||
49 | |||
50 | static int current_channel; | ||
51 | static unsigned short adcdata[NUM_ADC_CHANNELS]; | ||
52 | |||
53 | static void adc_tick(void) | ||
54 | { | ||
55 | /* Start a conversion of channel group 0. This will trigger an interrupt, | ||
56 | and the interrupt handler will take care of group 1. */ | ||
57 | |||
58 | current_channel = 0; | ||
59 | ADCSR = ADCSR_ADST | ADCSR_ADIE | ADCSR_SCAN | 3; | ||
60 | } | ||
61 | |||
62 | void ADITI(void) __attribute__((interrupt_handler)); | ||
63 | void ADITI(void) | ||
64 | { | ||
65 | if(ADCSR & ADCSR_ADF) | ||
66 | { | ||
67 | ADCSR = 0; | ||
68 | |||
69 | if(current_channel == 0) | ||
70 | { | ||
71 | adcdata[0] = ADDRA >> 6; | ||
72 | adcdata[1] = ADDRB >> 6; | ||
73 | adcdata[2] = ADDRC >> 6; | ||
74 | adcdata[3] = ADDRD >> 6; | ||
75 | current_channel = 4; | ||
76 | |||
77 | /* Convert the next group */ | ||
78 | ADCSR = ADCSR_ADST | ADCSR_ADIE | ADCSR_SCAN | 7; | ||
79 | } | ||
80 | else | ||
81 | { | ||
82 | adcdata[4] = ADDRA >> 6; | ||
83 | adcdata[5] = ADDRB >> 6; | ||
84 | adcdata[6] = ADDRC >> 6; | ||
85 | adcdata[7] = ADDRD >> 6; | ||
86 | } | ||
87 | } | ||
88 | } | ||
89 | |||
90 | unsigned short adc_read(int channel) | ||
91 | { | ||
92 | return adcdata[channel]; | ||
93 | } | ||
94 | |||
95 | void adc_init(void) | ||
96 | { | ||
97 | ADCR = 0x7f; /* No external trigger; other bits should be 1 according | ||
98 | to the manual... */ | ||
99 | |||
100 | ADCSR = 0; | ||
101 | |||
102 | current_channel = 0; | ||
103 | |||
104 | /* Enable the A/D IRQ on level 1 */ | ||
105 | IPRE = (IPRE & 0xf0ff) | 0x0100; | ||
106 | |||
107 | tick_add_task(adc_tick); | ||
108 | |||
109 | sleep(2); /* Ensure valid readings when adc_init returns */ | ||
110 | } | ||